AMDGPUAsmParser.cpp

Summary Report

Line number	Line	Number of hits	Tests that cover line
1	//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//	----
2	//	----
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.	----
4	// See https://llvm.org/LICENSE.txt for license information.	----
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception	----
6	//	----
7	//===----------------------------------------------------------------------===//	----
8		----
9	#include "AMDKernelCodeT.h"	----
10	#include "MCTargetDesc/AMDGPUMCTargetDesc.h"	----
11	#include "MCTargetDesc/AMDGPUTargetStreamer.h"	----
12	#include "SIDefines.h"	----
13	#include "SIInstrInfo.h"	----
14	#include "SIRegisterInfo.h"	----
15	#include "TargetInfo/AMDGPUTargetInfo.h"	----
16	#include "Utils/AMDGPUAsmUtils.h"	----
17	#include "Utils/AMDGPUBaseInfo.h"	----
18	#include "Utils/AMDKernelCodeTUtils.h"	----
19	#include "llvm/ADT/APFloat.h"	----
20	#include "llvm/ADT/SmallBitVector.h"	----
21	#include "llvm/ADT/StringSet.h"	----
22	#include "llvm/ADT/Twine.h"	----
23	#include "llvm/BinaryFormat/ELF.h"	----
24	#include "llvm/CodeGen/MachineValueType.h"	----
25	#include "llvm/MC/MCAsmInfo.h"	----
26	#include "llvm/MC/MCContext.h"	----
27	#include "llvm/MC/MCExpr.h"	----
28	#include "llvm/MC/MCInst.h"	----
29	#include "llvm/MC/MCInstrDesc.h"	----
30	#include "llvm/MC/MCParser/MCAsmLexer.h"	----
31	#include "llvm/MC/MCParser/MCAsmParser.h"	----
32	#include "llvm/MC/MCParser/MCParsedAsmOperand.h"	----
33	#include "llvm/MC/MCParser/MCTargetAsmParser.h"	----
34	#include "llvm/MC/MCSymbol.h"	----
35	#include "llvm/MC/TargetRegistry.h"	----
36	#include "llvm/Support/AMDGPUMetadata.h"	----
37	#include "llvm/Support/AMDHSAKernelDescriptor.h"	----
38	#include "llvm/Support/Casting.h"	----
39	#include "llvm/Support/MathExtras.h"	----
40	#include "llvm/TargetParser/TargetParser.h"	----
41	#include	----
42		----
43	using namespace llvm;	----
44	using namespace llvm::AMDGPU;	----
45	using namespace llvm::amdhsa;	----
46		----
47	namespace {	----
48		----
49	class AMDGPUAsmParser;	----
50		----
51	enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL };	----
52		----
53	//===----------------------------------------------------------------------===//	----
54	// Operand	----
55	//===----------------------------------------------------------------------===//	----
56		----
57	class AMDGPUOperand : public MCParsedAsmOperand {	----
58	enum KindTy {	----
59	Token,	----
60	Immediate,	----
61	Register,	----
62	Expression	----
63	} Kind;	----
64		----
65	SMLoc StartLoc, EndLoc;	----
66	const AMDGPUAsmParser *AsmParser;	----
67		----
68	public:	----
69	AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)	0
70	: Kind(Kind_), AsmParser(AsmParser_) {}	0
71		----
72	using Ptr = std::unique_ptr;	----
73		----
74	struct Modifiers {	----
75	bool Abs = false;	----
76	bool Neg = false;	----
77	bool Sext = false;	----
78		----
79	bool hasFPModifiers() const { return Abs \|\| Neg; }	0
80	bool hasIntModifiers() const { return Sext; }	0
81	bool hasModifiers() const { return hasFPModifiers() \|\| hasIntModifiers(); }	0
82		----
83	int64_t getFPModifiersOperand() const {	0
84	int64_t Operand = 0;	0
85	Operand \|= Abs ? SISrcMods::ABS : 0u;	0
86	Operand \|= Neg ? SISrcMods::NEG : 0u;	0
87	return Operand;	0
88	}	----
89		----
90	int64_t getIntModifiersOperand() const {	0
91	int64_t Operand = 0;	0
92	Operand \|= Sext ? SISrcMods::SEXT : 0u;	0
93	return Operand;	0
94	}	----
95		----
96	int64_t getModifiersOperand() const {	0
97	assert(!(hasFPModifiers() && hasIntModifiers())	0
98	&& "fp and int modifiers should not be used simultaneously");	----
99	if (hasFPModifiers()) {	0
100	return getFPModifiersOperand();	0
101	} else if (hasIntModifiers()) {	0
102	return getIntModifiersOperand();	0
103	} else {	----
104	return 0;	0
105	}	----
106	}	----
107		----
108	friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);	----
109	};	----
110		----
111	enum ImmTy {	----
112	ImmTyNone,	----
113	ImmTyGDS,	----
114	ImmTyLDS,	----
115	ImmTyOffen,	----
116	ImmTyIdxen,	----
117	ImmTyAddr64,	----
118	ImmTyOffset,	----
119	ImmTyInstOffset,	----
120	ImmTyOffset0,	----
121	ImmTyOffset1,	----
122	ImmTySMEMOffsetMod,	----
123	ImmTyCPol,	----
124	ImmTyTFE,	----
125	ImmTyD16,	----
126	ImmTyClampSI,	----
127	ImmTyOModSI,	----
128	ImmTySDWADstSel,	----
129	ImmTySDWASrc0Sel,	----
130	ImmTySDWASrc1Sel,	----
131	ImmTySDWADstUnused,	----
132	ImmTyDMask,	----
133	ImmTyDim,	----
134	ImmTyUNorm,	----
135	ImmTyDA,	----
136	ImmTyR128A16,	----
137	ImmTyA16,	----
138	ImmTyLWE,	----
139	ImmTyExpTgt,	----
140	ImmTyExpCompr,	----
141	ImmTyExpVM,	----
142	ImmTyFORMAT,	----
143	ImmTyHwreg,	----
144	ImmTyOff,	----
145	ImmTySendMsg,	----
146	ImmTyInterpSlot,	----
147	ImmTyInterpAttr,	----
148	ImmTyInterpAttrChan,	----
149	ImmTyOpSel,	----
150	ImmTyOpSelHi,	----
151	ImmTyNegLo,	----
152	ImmTyNegHi,	----
153	ImmTyDPP8,	----
154	ImmTyDppCtrl,	----
155	ImmTyDppRowMask,	----
156	ImmTyDppBankMask,	----
157	ImmTyDppBoundCtrl,	----
158	ImmTyDppFI,	----
159	ImmTySwizzle,	----
160	ImmTyGprIdxMode,	----
161	ImmTyHigh,	----
162	ImmTyBLGP,	----
163	ImmTyCBSZ,	----
164	ImmTyABID,	----
165	ImmTyEndpgm,	----
166	ImmTyWaitVDST,	----
167	ImmTyWaitEXP,	----
168	};	----
169		----
170	// Immediate operand kind.	----
171	// It helps to identify the location of an offending operand after an error.	----
172	// Note that regular literals and mandatory literals (KImm) must be handled	----
173	// differently. When looking for an offending operand, we should usually	----
174	// ignore mandatory literals because they are part of the instruction and	----
175	// cannot be changed. Report location of mandatory operands only for VOPD,	----
176	// when both OpX and OpY have a KImm and there are no other literals.	----
177	enum ImmKindTy {	----
178	ImmKindTyNone,	----
179	ImmKindTyLiteral,	----
180	ImmKindTyMandatoryLiteral,	----
181	ImmKindTyConst,	----
182	};	----
183		----
184	private:	----
185	struct TokOp {	----
186	const char *Data;	----
187	unsigned Length;	----
188	};	----
189		----
190	struct ImmOp {	----
191	int64_t Val;	----
192	ImmTy Type;	----
193	bool IsFPImm;	----
194	mutable ImmKindTy Kind;	----
195	Modifiers Mods;	----
196	};	----
197		----
198	struct RegOp {	----
199	unsigned RegNo;	----
200	Modifiers Mods;	----
201	};	----
202		----
203	union {	----
204	TokOp Tok;	----
205	ImmOp Imm;	----
206	RegOp Reg;	----
207	const MCExpr *Expr;	----
208	};	----
209		----
210	public:	----
211	bool isToken() const override { return Kind == Token; }	0
212		----
213	bool isSymbolRefExpr() const {	0
214	return isExpr() && Expr && isa(Expr);	0
215	}	----
216		----
217	bool isImm() const override {	0
218	return Kind == Immediate;	0
219	}	----
220		----
221	void setImmKindNone() const {	0
222	assert(isImm());	0
223	Imm.Kind = ImmKindTyNone;	0
224	}	0
225		----
226	void setImmKindLiteral() const {	0
227	assert(isImm());	0
228	Imm.Kind = ImmKindTyLiteral;	0
229	}	0
230		----
231	void setImmKindMandatoryLiteral() const {	0
232	assert(isImm());	0
233	Imm.Kind = ImmKindTyMandatoryLiteral;	0
234	}	0
235		----
236	void setImmKindConst() const {	0
237	assert(isImm());	0
238	Imm.Kind = ImmKindTyConst;	0
239	}	0
240		----
241	bool IsImmKindLiteral() const {	0
242	return isImm() && Imm.Kind == ImmKindTyLiteral;	0
243	}	----
244		----
245	bool IsImmKindMandatoryLiteral() const {	0
246	return isImm() && Imm.Kind == ImmKindTyMandatoryLiteral;	0
247	}	----
248		----
249	bool isImmKindConst() const {	0
250	return isImm() && Imm.Kind == ImmKindTyConst;	0
251	}	----
252		----
253	bool isInlinableImm(MVT type) const;	----
254	bool isLiteralImm(MVT type) const;	----
255		----
256	bool isRegKind() const {	0
257	return Kind == Register;	0
258	}	----
259		----
260	bool isReg() const override {	0
261	return isRegKind() && !hasModifiers();	0
262	}	----
263		----
264	bool isRegOrInline(unsigned RCID, MVT type) const {	0
265	return isRegClass(RCID) \|\| isInlinableImm(type);	0
266	}	----
267		----
268	bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {	0
269	return isRegOrInline(RCID, type) \|\| isLiteralImm(type);	0
270	}	----
271		----
272	bool isRegOrImmWithInt16InputMods() const {	----
273	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);	----
274	}	----
275		----
276	bool isRegOrImmWithInt32InputMods() const {	0
277	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);	0
278	}	----
279		----
280	bool isRegOrInlineImmWithInt16InputMods() const {	----
281	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16);	----
282	}	----
283		----
284	bool isRegOrInlineImmWithInt32InputMods() const {	0
285	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32);	0
286	}	----
287		----
288	bool isRegOrImmWithInt64InputMods() const {	0
289	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);	0
290	}	----
291		----
292	bool isRegOrImmWithFP16InputMods() const {	0
293	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);	0
294	}	----
295		----
296	bool isRegOrImmWithFP32InputMods() const {	0
297	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);	0
298	}	----
299		----
300	bool isRegOrImmWithFP64InputMods() const {	0
301	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);	0
302	}	----
303		----
304	bool isRegOrInlineImmWithFP16InputMods() const {	0
305	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16);	0
306	}	----
307		----
308	bool isRegOrInlineImmWithFP32InputMods() const {	0
309	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32);	0
310	}	----
311		----
312		----
313	bool isVReg() const {	----
314	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	----
315	isRegClass(AMDGPU::VReg_64RegClassID) \|\|	----
316	isRegClass(AMDGPU::VReg_96RegClassID) \|\|	----
317	isRegClass(AMDGPU::VReg_128RegClassID) \|\|	----
318	isRegClass(AMDGPU::VReg_160RegClassID) \|\|	----
319	isRegClass(AMDGPU::VReg_192RegClassID) \|\|	----
320	isRegClass(AMDGPU::VReg_256RegClassID) \|\|	----
321	isRegClass(AMDGPU::VReg_512RegClassID) \|\|	----
322	isRegClass(AMDGPU::VReg_1024RegClassID);	----
323	}	----
324		----
325	bool isVReg32() const {	0
326	return isRegClass(AMDGPU::VGPR_32RegClassID);	0
327	}	----
328		----
329	bool isVReg32OrOff() const {	0
330	return isOff() \|\| isVReg32();	0
331	}	----
332		----
333	bool isNull() const {	0
334	return isRegKind() && getReg() == AMDGPU::SGPR_NULL;	0
335	}	----
336		----
337	bool isVRegWithInputMods() const;	----
338	bool isT16VRegWithInputMods() const;	----
339		----
340	bool isSDWAOperand(MVT type) const;	----
341	bool isSDWAFP16Operand() const;	----
342	bool isSDWAFP32Operand() const;	----
343	bool isSDWAInt16Operand() const;	----
344	bool isSDWAInt32Operand() const;	----
345		----
346	bool isImmTy(ImmTy ImmT) const {	0
347	return isImm() && Imm.Type == ImmT;	0
348	}	----
349		----
350	bool isImmLiteral() const { return isImmTy(ImmTyNone); }	0
351		----
352	bool isImmModifier() const {	0
353	return isImm() && Imm.Type != ImmTyNone;	0
354	}	----
355		----
356	bool isClampSI() const { return isImmTy(ImmTyClampSI); }	0
357	bool isOModSI() const { return isImmTy(ImmTyOModSI); }	0
358	bool isDMask() const { return isImmTy(ImmTyDMask); }	0
359	bool isDim() const { return isImmTy(ImmTyDim); }	0
360	bool isUNorm() const { return isImmTy(ImmTyUNorm); }	0
361	bool isDA() const { return isImmTy(ImmTyDA); }	0
362	bool isR128A16() const { return isImmTy(ImmTyR128A16); }	0
363	bool isA16() const { return isImmTy(ImmTyA16); }	0
364	bool isLWE() const { return isImmTy(ImmTyLWE); }	0
365	bool isOff() const { return isImmTy(ImmTyOff); }	0
366	bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }	0
367	bool isExpVM() const { return isImmTy(ImmTyExpVM); }	0
368	bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }	0
369	bool isOffen() const { return isImmTy(ImmTyOffen); }	0
370	bool isIdxen() const { return isImmTy(ImmTyIdxen); }	0
371	bool isAddr64() const { return isImmTy(ImmTyAddr64); }	0
372	bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }	0
373	bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }	0
374	bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }	0
375	bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }	0
376	bool isFlatOffset() const { return isImmTy(ImmTyOffset) \|\| isImmTy(ImmTyInstOffset); }	0
377	bool isGDS() const { return isImmTy(ImmTyGDS); }	0
378	bool isLDS() const { return isImmTy(ImmTyLDS); }	0
379	bool isCPol() const { return isImmTy(ImmTyCPol); }	0
380	bool isTFE() const { return isImmTy(ImmTyTFE); }	0
381	bool isD16() const { return isImmTy(ImmTyD16); }	0
382	bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }	0
383	bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }	0
384	bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }	0
385	bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }	0
386	bool isDppFI() const { return isImmTy(ImmTyDppFI); }	0
387	bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }	0
388	bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }	0
389	bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); }	0
390	bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }	0
391	bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }	0
392	bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }	0
393	bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }	0
394	bool isOpSel() const { return isImmTy(ImmTyOpSel); }	0
395	bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }	0
396	bool isNegLo() const { return isImmTy(ImmTyNegLo); }	0
397	bool isNegHi() const { return isImmTy(ImmTyNegHi); }	0
398	bool isHigh() const { return isImmTy(ImmTyHigh); }	0
399		----
400	bool isRegOrImm() const {	0
401	return isReg() \|\| isImm();	0
402	}	----
403		----
404	bool isRegClass(unsigned RCID) const;	----
405		----
406	bool isInlineValue() const;	----
407		----
408	bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {	0
409	return isRegOrInline(RCID, type) && !hasModifiers();	0
410	}	----
411		----
412	bool isSCSrcB16() const {	----
413	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);	----
414	}	----
415		----
416	bool isSCSrcV2B16() const {	----
417	return isSCSrcB16();	----
418	}	----
419		----
420	bool isSCSrcB32() const {	0
421	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);	0
422	}	----
423		----
424	bool isSCSrcB64() const {	0
425	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);	0
426	}	----
427		----
428	bool isBoolReg() const;	----
429		----
430	bool isSCSrcF16() const {	----
431	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);	----
432	}	----
433		----
434	bool isSCSrcV2F16() const {	----
435	return isSCSrcF16();	----
436	}	----
437		----
438	bool isSCSrcF32() const {	----
439	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);	----
440	}	----
441		----
442	bool isSCSrcF64() const {	----
443	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);	----
444	}	----
445		----
446	bool isSSrcB32() const {	0
447	return isSCSrcB32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	0
448	}	----
449		----
450	bool isSSrcB16() const {	----
451	return isSCSrcB16() \|\| isLiteralImm(MVT::i16);	----
452	}	----
453		----
454	bool isSSrcV2B16() const {	----
455	llvm_unreachable("cannot happen");	----
456	return isSSrcB16();	----
457	}	----
458		----
459	bool isSSrcB64() const {	0
460	// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.	----
461	// See isVSrc64().	----
462	return isSCSrcB64() \|\| isLiteralImm(MVT::i64);	0
463	}	----
464		----
465	bool isSSrcF32() const {	0
466	return isSCSrcB32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	0
467	}	----
468		----
469	bool isSSrcF64() const {	----
470	return isSCSrcB64() \|\| isLiteralImm(MVT::f64);	----
471	}	----
472		----
473	bool isSSrcF16() const {	----
474	return isSCSrcB16() \|\| isLiteralImm(MVT::f16);	----
475	}	----
476		----
477	bool isSSrcV2F16() const {	----
478	llvm_unreachable("cannot happen");	----
479	return isSSrcF16();	----
480	}	----
481		----
482	bool isSSrcV2FP32() const {	----
483	llvm_unreachable("cannot happen");	----
484	return isSSrcF32();	----
485	}	----
486		----
487	bool isSCSrcV2FP32() const {	----
488	llvm_unreachable("cannot happen");	----
489	return isSCSrcF32();	----
490	}	----
491		----
492	bool isSSrcV2INT32() const {	----
493	llvm_unreachable("cannot happen");	----
494	return isSSrcB32();	----
495	}	----
496		----
497	bool isSCSrcV2INT32() const {	----
498	llvm_unreachable("cannot happen");	----
499	return isSCSrcB32();	----
500	}	----
501		----
502	bool isSSrcOrLdsB32() const {	0
503	return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) \|\|	0
504	isLiteralImm(MVT::i32) \|\| isExpr();	0
505	}	----
506		----
507	bool isVCSrcB32() const {	0
508	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);	0
509	}	----
510		----
511	bool isVCSrcB64() const {	----
512	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);	----
513	}	----
514		----
515	bool isVCSrcTB16_Lo128() const {	0
516	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16);	0
517	}	----
518		----
519	bool isVCSrcB16() const {	0
520	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16);	0
521	}	----
522		----
523	bool isVCSrcV2B16() const {	0
524	return isVCSrcB16();	0
525	}	----
526		----
527	bool isVCSrcF32() const {	0
528	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);	0
529	}	----
530		----
531	bool isVCSrcF64() const {	0
532	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);	0
533	}	----
534		----
535	bool isVCSrcTF16_Lo128() const {	0
536	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16);	0
537	}	----
538		----
539	bool isVCSrcF16() const {	0
540	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);	0
541	}	----
542		----
543	bool isVCSrcV2F16() const {	0
544	return isVCSrcF16();	0
545	}	----
546		----
547	bool isVSrcB32() const {	0
548	return isVCSrcF32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	0
549	}	----
550		----
551	bool isVSrcB64() const {	0
552	return isVCSrcF64() \|\| isLiteralImm(MVT::i64);	0
553	}	----
554		----
555	bool isVSrcTB16_Lo128() const {	0
556	return isVCSrcTB16_Lo128() \|\| isLiteralImm(MVT::i16);	0
557	}	----
558		----
559	bool isVSrcB16() const {	0
560	return isVCSrcB16() \|\| isLiteralImm(MVT::i16);	0
561	}	----
562		----
563	bool isVSrcV2B16() const {	0
564	return isVSrcB16() \|\| isLiteralImm(MVT::v2i16);	0
565	}	----
566		----
567	bool isVCSrcV2FP32() const {	----
568	return isVCSrcF64();	----
569	}	----
570		----
571	bool isVSrcV2FP32() const {	0
572	return isVSrcF64() \|\| isLiteralImm(MVT::v2f32);	0
573	}	----
574		----
575	bool isVCSrcV2INT32() const {	----
576	return isVCSrcB64();	----
577	}	----
578		----
579	bool isVSrcV2INT32() const {	0
580	return isVSrcB64() \|\| isLiteralImm(MVT::v2i32);	0
581	}	----
582		----
583	bool isVSrcF32() const {	0
584	return isVCSrcF32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	0
585	}	----
586		----
587	bool isVSrcF64() const {	0
588	return isVCSrcF64() \|\| isLiteralImm(MVT::f64);	0
589	}	----
590		----
591	bool isVSrcTF16_Lo128() const {	0
592	return isVCSrcTF16_Lo128() \|\| isLiteralImm(MVT::f16);	0
593	}	----
594		----
595	bool isVSrcF16() const {	0
596	return isVCSrcF16() \|\| isLiteralImm(MVT::f16);	0
597	}	----
598		----
599	bool isVSrcV2F16() const {	0
600	return isVSrcF16() \|\| isLiteralImm(MVT::v2f16);	0
601	}	----
602		----
603	bool isVISrcB32() const {	----
604	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32);	----
605	}	----
606		----
607	bool isVISrcB16() const {	----
608	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16);	----
609	}	----
610		----
611	bool isVISrcV2B16() const {	----
612	return isVISrcB16();	----
613	}	----
614		----
615	bool isVISrcF32() const {	----
616	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32);	----
617	}	----
618		----
619	bool isVISrcF16() const {	----
620	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16);	----
621	}	----
622		----
623	bool isVISrcV2F16() const {	----
624	return isVISrcF16() \|\| isVISrcB32();	----
625	}	----
626		----
627	bool isVISrc_64B64() const {	----
628	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64);	----
629	}	----
630		----
631	bool isVISrc_64F64() const {	0
632	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64);	0
633	}	----
634		----
635	bool isVISrc_64V2FP32() const {	----
636	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32);	----
637	}	----
638		----
639	bool isVISrc_64V2INT32() const {	----
640	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32);	----
641	}	----
642		----
643	bool isVISrc_256B64() const {	----
644	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64);	----
645	}	----
646		----
647	bool isVISrc_256F64() const {	0
648	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64);	0
649	}	----
650		----
651	bool isVISrc_128B16() const {	----
652	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16);	----
653	}	----
654		----
655	bool isVISrc_128V2B16() const {	----
656	return isVISrc_128B16();	----
657	}	----
658		----
659	bool isVISrc_128B32() const {	0
660	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32);	0
661	}	----
662		----
663	bool isVISrc_128F32() const {	0
664	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32);	0
665	}	----
666		----
667	bool isVISrc_256V2FP32() const {	----
668	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32);	----
669	}	----
670		----
671	bool isVISrc_256V2INT32() const {	----
672	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32);	----
673	}	----
674		----
675	bool isVISrc_512B32() const {	0
676	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32);	0
677	}	----
678		----
679	bool isVISrc_512B16() const {	----
680	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16);	----
681	}	----
682		----
683	bool isVISrc_512V2B16() const {	----
684	return isVISrc_512B16();	----
685	}	----
686		----
687	bool isVISrc_512F32() const {	0
688	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32);	0
689	}	----
690		----
691	bool isVISrc_512F16() const {	----
692	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16);	----
693	}	----
694		----
695	bool isVISrc_512V2F16() const {	----
696	return isVISrc_512F16() \|\| isVISrc_512B32();	----
697	}	----
698		----
699	bool isVISrc_1024B32() const {	0
700	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32);	0
701	}	----
702		----
703	bool isVISrc_1024B16() const {	----
704	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16);	----
705	}	----
706		----
707	bool isVISrc_1024V2B16() const {	----
708	return isVISrc_1024B16();	----
709	}	----
710		----
711	bool isVISrc_1024F32() const {	0
712	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32);	0
713	}	----
714		----
715	bool isVISrc_1024F16() const {	----
716	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16);	----
717	}	----
718		----
719	bool isVISrc_1024V2F16() const {	----
720	return isVISrc_1024F16() \|\| isVISrc_1024B32();	----
721	}	----
722		----
723	bool isAISrcB32() const {	----
724	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32);	----
725	}	----
726		----
727	bool isAISrcB16() const {	----
728	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16);	----
729	}	----
730		----
731	bool isAISrcV2B16() const {	----
732	return isAISrcB16();	----
733	}	----
734		----
735	bool isAISrcF32() const {	----
736	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);	----
737	}	----
738		----
739	bool isAISrcF16() const {	----
740	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);	----
741	}	----
742		----
743	bool isAISrcV2F16() const {	----
744	return isAISrcF16() \|\| isAISrcB32();	----
745	}	----
746		----
747	bool isAISrc_64B64() const {	----
748	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64);	----
749	}	----
750		----
751	bool isAISrc_64F64() const {	0
752	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64);	0
753	}	----
754		----
755	bool isAISrc_128B32() const {	0
756	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32);	0
757	}	----
758		----
759	bool isAISrc_128B16() const {	----
760	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16);	----
761	}	----
762		----
763	bool isAISrc_128V2B16() const {	----
764	return isAISrc_128B16();	----
765	}	----
766		----
767	bool isAISrc_128F32() const {	0
768	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);	0
769	}	----
770		----
771	bool isAISrc_128F16() const {	----
772	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);	----
773	}	----
774		----
775	bool isAISrc_128V2F16() const {	----
776	return isAISrc_128F16() \|\| isAISrc_128B32();	----
777	}	----
778		----
779	bool isVISrc_128F16() const {	----
780	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16);	----
781	}	----
782		----
783	bool isVISrc_128V2F16() const {	----
784	return isVISrc_128F16() \|\| isVISrc_128B32();	----
785	}	----
786		----
787	bool isAISrc_256B64() const {	----
788	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64);	----
789	}	----
790		----
791	bool isAISrc_256F64() const {	0
792	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64);	0
793	}	----
794		----
795	bool isAISrc_512B32() const {	0
796	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32);	0
797	}	----
798		----
799	bool isAISrc_512B16() const {	----
800	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16);	----
801	}	----
802		----
803	bool isAISrc_512V2B16() const {	----
804	return isAISrc_512B16();	----
805	}	----
806		----
807	bool isAISrc_512F32() const {	0
808	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);	0
809	}	----
810		----
811	bool isAISrc_512F16() const {	----
812	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);	----
813	}	----
814		----
815	bool isAISrc_512V2F16() const {	----
816	return isAISrc_512F16() \|\| isAISrc_512B32();	----
817	}	----
818		----
819	bool isAISrc_1024B32() const {	0
820	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32);	0
821	}	----
822		----
823	bool isAISrc_1024B16() const {	----
824	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16);	----
825	}	----
826		----
827	bool isAISrc_1024V2B16() const {	----
828	return isAISrc_1024B16();	----
829	}	----
830		----
831	bool isAISrc_1024F32() const {	0
832	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);	0
833	}	----
834		----
835	bool isAISrc_1024F16() const {	----
836	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);	----
837	}	----
838		----
839	bool isAISrc_1024V2F16() const {	----
840	return isAISrc_1024F16() \|\| isAISrc_1024B32();	----
841	}	----
842		----
843	bool isKImmFP32() const {	0
844	return isLiteralImm(MVT::f32);	0
845	}	----
846		----
847	bool isKImmFP16() const {	0
848	return isLiteralImm(MVT::f16);	0
849	}	----
850		----
851	bool isMem() const override {	0
852	return false;	0
853	}	----
854		----
855	bool isExpr() const {	0
856	return Kind == Expression;	0
857	}	----
858		----
859	bool isSOPPBrTarget() const { return isExpr() \|\| isImm(); }	0
860		----
861	bool isSWaitCnt() const;	----
862	bool isDepCtr() const;	----
863	bool isSDelayALU() const;	----
864	bool isHwreg() const;	----
865	bool isSendMsg() const;	----
866	bool isSwizzle() const;	----
867	bool isSMRDOffset8() const;	----
868	bool isSMEMOffset() const;	----
869	bool isSMRDLiteralOffset() const;	----
870	bool isDPP8() const;	----
871	bool isDPPCtrl() const;	----
872	bool isBLGP() const;	----
873	bool isCBSZ() const;	----
874	bool isABID() const;	----
875	bool isGPRIdxMode() const;	----
876	bool isS16Imm() const;	----
877	bool isU16Imm() const;	----
878	bool isEndpgm() const;	----
879	bool isWaitVDST() const;	----
880	bool isWaitEXP() const;	----
881		----
882	StringRef getToken() const {	0
883	assert(isToken());	0
884	return StringRef(Tok.Data, Tok.Length);	0
885	}	----
886		----
887	int64_t getImm() const {	0
888	assert(isImm());	0
889	return Imm.Val;	0
890	}	----
891		----
892	void setImm(int64_t Val) {	0
893	assert(isImm());	0
894	Imm.Val = Val;	0
895	}	0
896		----
897	ImmTy getImmTy() const {	0
898	assert(isImm());	0
899	return Imm.Type;	0
900	}	----
901		----
902	unsigned getReg() const override {	0
903	assert(isRegKind());	0
904	return Reg.RegNo;	0
905	}	----
906		----
907	SMLoc getStartLoc() const override {	0
908	return StartLoc;	0
909	}	----
910		----
911	SMLoc getEndLoc() const override {	0
912	return EndLoc;	0
913	}	----
914		----
915	SMRange getLocRange() const {	----
916	return SMRange(StartLoc, EndLoc);	----
917	}	----
918		----
919	Modifiers getModifiers() const {	0
920	assert(isRegKind() \|\| isImmTy(ImmTyNone));	0
921	return isRegKind() ? Reg.Mods : Imm.Mods;	0
922	}	----
923		----
924	void setModifiers(Modifiers Mods) {	0
925	assert(isRegKind() \|\| isImmTy(ImmTyNone));	0
926	if (isRegKind())	0
927	Reg.Mods = Mods;	0
928	else	----
929	Imm.Mods = Mods;	0
930	}	0
931		----
932	bool hasModifiers() const {	0
933	return getModifiers().hasModifiers();	0
934	}	----
935		----
936	bool hasFPModifiers() const {	0
937	return getModifiers().hasFPModifiers();	0
938	}	----
939		----
940	bool hasIntModifiers() const {	0
941	return getModifiers().hasIntModifiers();	0
942	}	----
943		----
944	uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;	----
945		----
946	void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;	----
947		----
948	void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;	----
949		----
950	void addRegOperands(MCInst &Inst, unsigned N) const;	----
951		----
952	void addRegOrImmOperands(MCInst &Inst, unsigned N) const {	0
953	if (isRegKind())	0
954	addRegOperands(Inst, N);	0
955	else	----
956	addImmOperands(Inst, N);	0
957	}	0
958		----
959	void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {	0
960	Modifiers Mods = getModifiers();	0
961	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	0
962	if (isRegKind()) {	0
963	addRegOperands(Inst, N);	0
964	} else {	----
965	addImmOperands(Inst, N, false);	0
966	}	----
967	}	0
968		----
969	void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	0
970	assert(!hasIntModifiers());	0
971	addRegOrImmWithInputModsOperands(Inst, N);	0
972	}	0
973		----
974	void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	----
975	assert(!hasFPModifiers());	----
976	addRegOrImmWithInputModsOperands(Inst, N);	----
977	}	----
978		----
979	void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {	0
980	Modifiers Mods = getModifiers();	0
981	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	0
982	assert(isRegKind());	0
983	addRegOperands(Inst, N);	0
984	}	0
985		----
986	void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	0
987	assert(!hasIntModifiers());	0
988	addRegWithInputModsOperands(Inst, N);	0
989	}	0
990		----
991	void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	----
992	assert(!hasFPModifiers());	----
993	addRegWithInputModsOperands(Inst, N);	----
994	}	----
995		----
996	static void printImmTy(raw_ostream& OS, ImmTy Type) {	0
997	switch (Type) {	0
998	case ImmTyNone: OS << "None"; break;	0
999	case ImmTyGDS: OS << "GDS"; break;	0
1000	case ImmTyLDS: OS << "LDS"; break;	0
1001	case ImmTyOffen: OS << "Offen"; break;	0
1002	case ImmTyIdxen: OS << "Idxen"; break;	0
1003	case ImmTyAddr64: OS << "Addr64"; break;	0
1004	case ImmTyOffset: OS << "Offset"; break;	0
1005	case ImmTyInstOffset: OS << "InstOffset"; break;	0
1006	case ImmTyOffset0: OS << "Offset0"; break;	0
1007	case ImmTyOffset1: OS << "Offset1"; break;	0
1008	case ImmTySMEMOffsetMod: OS << "SMEMOffsetMod"; break;	0
1009	case ImmTyCPol: OS << "CPol"; break;	0
1010	case ImmTyTFE: OS << "TFE"; break;	0
1011	case ImmTyD16: OS << "D16"; break;	0
1012	case ImmTyFORMAT: OS << "FORMAT"; break;	0
1013	case ImmTyClampSI: OS << "ClampSI"; break;	0
1014	case ImmTyOModSI: OS << "OModSI"; break;	0
1015	case ImmTyDPP8: OS << "DPP8"; break;	0
1016	case ImmTyDppCtrl: OS << "DppCtrl"; break;	0
1017	case ImmTyDppRowMask: OS << "DppRowMask"; break;	0
1018	case ImmTyDppBankMask: OS << "DppBankMask"; break;	0
1019	case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;	0
1020	case ImmTyDppFI: OS << "DppFI"; break;	0
1021	case ImmTySDWADstSel: OS << "SDWADstSel"; break;	0
1022	case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break;	0
1023	case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break;	0
1024	case ImmTySDWADstUnused: OS << "SDWADstUnused"; break;	0
1025	case ImmTyDMask: OS << "DMask"; break;	0
1026	case ImmTyDim: OS << "Dim"; break;	0
1027	case ImmTyUNorm: OS << "UNorm"; break;	0
1028	case ImmTyDA: OS << "DA"; break;	0
1029	case ImmTyR128A16: OS << "R128A16"; break;	0
1030	case ImmTyA16: OS << "A16"; break;	0
1031	case ImmTyLWE: OS << "LWE"; break;	0
1032	case ImmTyOff: OS << "Off"; break;	0
1033	case ImmTyExpTgt: OS << "ExpTgt"; break;	0
1034	case ImmTyExpCompr: OS << "ExpCompr"; break;	0
1035	case ImmTyExpVM: OS << "ExpVM"; break;	0
1036	case ImmTyHwreg: OS << "Hwreg"; break;	0
1037	case ImmTySendMsg: OS << "SendMsg"; break;	0
1038	case ImmTyInterpSlot: OS << "InterpSlot"; break;	0
1039	case ImmTyInterpAttr: OS << "InterpAttr"; break;	0
1040	case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;	0
1041	case ImmTyOpSel: OS << "OpSel"; break;	0
1042	case ImmTyOpSelHi: OS << "OpSelHi"; break;	0
1043	case ImmTyNegLo: OS << "NegLo"; break;	0
1044	case ImmTyNegHi: OS << "NegHi"; break;	0
1045	case ImmTySwizzle: OS << "Swizzle"; break;	0
1046	case ImmTyGprIdxMode: OS << "GprIdxMode"; break;	0
1047	case ImmTyHigh: OS << "High"; break;	0
1048	case ImmTyBLGP: OS << "BLGP"; break;	0
1049	case ImmTyCBSZ: OS << "CBSZ"; break;	0
1050	case ImmTyABID: OS << "ABID"; break;	0
1051	case ImmTyEndpgm: OS << "Endpgm"; break;	0
1052	case ImmTyWaitVDST: OS << "WaitVDST"; break;	0
1053	case ImmTyWaitEXP: OS << "WaitEXP"; break;	0
1054	}	----
1055	}	0
1056		----
1057	void print(raw_ostream &OS) const override {	0
1058	switch (Kind) {	0
1059	case Register:	0
1060	OS << "';	0
1061	break;	0
1062	case Immediate:	0
1063	OS << '<' << getImm();	0
1064	if (getImmTy() != ImmTyNone) {	0
1065	OS << " type: "; printImmTy(OS, getImmTy());	0
1066	}	----
1067	OS << " mods: " << Imm.Mods << '>';	0
1068	break;	0
1069	case Token:	0
1070	OS << '\'' << getToken() << '\'';	0
1071	break;	0
1072	case Expression:	0
1073	OS << "';	0
1074	break;	0
1075	}	----
1076	}	0
1077		----
1078	static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,	0
1079	int64_t Val, SMLoc Loc,	----
1080	ImmTy Type = ImmTyNone,	----
1081	bool IsFPImm = false) {	----
1082	auto Op = std::make_unique(Immediate, AsmParser);	0
1083	Op->Imm.Val = Val;	0
1084	Op->Imm.IsFPImm = IsFPImm;	0
1085	Op->Imm.Kind = ImmKindTyNone;	0
1086	Op->Imm.Type = Type;	0
1087	Op->Imm.Mods = Modifiers();	0
1088	Op->StartLoc = Loc;	0
1089	Op->EndLoc = Loc;	0
1090	return Op;	0
1091	}	----
1092		----
1093	static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,	0
1094	StringRef Str, SMLoc Loc,	----
1095	bool HasExplicitEncodingSize = true) {	----
1096	auto Res = std::make_unique(Token, AsmParser);	0
1097	Res->Tok.Data = Str.data();	0
1098	Res->Tok.Length = Str.size();	0
1099	Res->StartLoc = Loc;	0
1100	Res->EndLoc = Loc;	0
1101	return Res;	0
1102	}	----
1103		----
1104	static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,	0
1105	unsigned RegNo, SMLoc S,	----
1106	SMLoc E) {	----
1107	auto Op = std::make_unique(Register, AsmParser);	0
1108	Op->Reg.RegNo = RegNo;	0
1109	Op->Reg.Mods = Modifiers();	0
1110	Op->StartLoc = S;	0
1111	Op->EndLoc = E;	0
1112	return Op;	0
1113	}	----
1114		----
1115	static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,	0
1116	const class MCExpr *Expr, SMLoc S) {	----
1117	auto Op = std::make_unique(Expression, AsmParser);	0
1118	Op->Expr = Expr;	0
1119	Op->StartLoc = S;	0
1120	Op->EndLoc = S;	0
1121	return Op;	0
1122	}	----
1123	};	----
1124		----
1125	raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) {	0
1126	OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;	0
1127	return OS;	0
1128	}	----
1129		----
1130	//===----------------------------------------------------------------------===//	----
1131	// AsmParser	----
1132	//===----------------------------------------------------------------------===//	----
1133		----
1134	// Holds info related to the current kernel, e.g. count of SGPRs used.	----
1135	// Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next	----
1136	// .amdgpu_hsa_kernel or at EOF.	----
1137	class KernelScopeInfo {	----
1138	int SgprIndexUnusedMin = -1;	----
1139	int VgprIndexUnusedMin = -1;	----
1140	int AgprIndexUnusedMin = -1;	----
1141	MCContext *Ctx = nullptr;	----
1142	MCSubtargetInfo const *MSTI = nullptr;	----
1143		----
1144	void usesSgprAt(int i) {	0
1145	if (i >= SgprIndexUnusedMin) {	0
1146	SgprIndexUnusedMin = ++i;	0
1147	if (Ctx) {	0
1148	MCSymbol* const Sym =	----
1149	Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));	0
1150	Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));	0
1151	}	----
1152	}	----
1153	}	0
1154		----
1155	void usesVgprAt(int i) {	0
1156	if (i >= VgprIndexUnusedMin) {	0
1157	VgprIndexUnusedMin = ++i;	0
1158	if (Ctx) {	0
1159	MCSymbol* const Sym =	----
1160	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	0
1161	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	0
1162	VgprIndexUnusedMin);	----
1163	Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	0
1164	}	----
1165	}	----
1166	}	0
1167		----
1168	void usesAgprAt(int i) {	0
1169	// Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction	----
1170	if (!hasMAIInsts(*MSTI))	0
1171	return;	0
1172		----
1173	if (i >= AgprIndexUnusedMin) {	0
1174	AgprIndexUnusedMin = ++i;	0
1175	if (Ctx) {	0
1176	MCSymbol* const Sym =	----
1177	Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count"));	0
1178	Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx));	0
1179		----
1180	// Also update vgpr_count (dependent on agpr_count for gfx908/gfx90a)	----
1181	MCSymbol* const vSym =	----
1182	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	0
1183	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	0
1184	VgprIndexUnusedMin);	----
1185	vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	0
1186	}	----
1187	}	----
1188	}	----
1189		----
1190	public:	----
1191	KernelScopeInfo() = default;	0
1192		----
1193	void initialize(MCContext &Context) {	0
1194	Ctx = &Context;	0
1195	MSTI = Ctx->getSubtargetInfo();	0
1196		----
1197	usesSgprAt(SgprIndexUnusedMin = -1);	0
1198	usesVgprAt(VgprIndexUnusedMin = -1);	0
1199	if (hasMAIInsts(*MSTI)) {	0
1200	usesAgprAt(AgprIndexUnusedMin = -1);	0
1201	}	----
1202	}	0
1203		----
1204	void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex,	0
1205	unsigned RegWidth) {	----
1206	switch (RegKind) {	0
1207	case IS_SGPR:	0
1208	usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0
1209	break;	0
1210	case IS_AGPR:	0
1211	usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0
1212	break;	0
1213	case IS_VGPR:	0
1214	usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0
1215	break;	0
1216	default:	0
1217	break;	0
1218	}	----
1219	}	0
1220	};	----
1221		----
1222	class AMDGPUAsmParser : public MCTargetAsmParser {	----
1223	MCAsmParser &Parser;	----
1224		----
1225	unsigned ForcedEncodingSize = 0;	----
1226	bool ForcedDPP = false;	----
1227	bool ForcedSDWA = false;	----
1228	KernelScopeInfo KernelScope;	----
1229		----
1230	/// @name Auto-generated Match Functions	----
1231	/// {	----
1232		----
1233	#define GET_ASSEMBLER_HEADER	----
1234	#include "AMDGPUGenAsmMatcher.inc"	----
1235		----
1236	/// }	----
1237		----
1238	private:	----
1239	bool ParseAsAbsoluteExpression(uint32_t &Ret);	----
1240	bool OutOfRangeError(SMRange Range);	----
1241	/// Calculate VGPR/SGPR blocks required for given target, reserved	----
1242	/// registers, and user-specified NextFreeXGPR values.	----
1243	///	----
1244	/// \param Features [in] Target features, used for bug corrections.	----
1245	/// \param VCCUsed [in] Whether VCC special SGPR is reserved.	----
1246	/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.	----
1247	/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.	----
1248	/// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel	----
1249	/// descriptor field, if valid.	----
1250	/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.	----
1251	/// \param VGPRRange [in] Token range, used for VGPR diagnostics.	----
1252	/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.	----
1253	/// \param SGPRRange [in] Token range, used for SGPR diagnostics.	----
1254	/// \param VGPRBlocks [out] Result VGPR block count.	----
1255	/// \param SGPRBlocks [out] Result SGPR block count.	----
1256	bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,	----
1257	bool FlatScrUsed, bool XNACKUsed,	----
1258	std::optional EnableWavefrontSize32,	----
1259	unsigned NextFreeVGPR, SMRange VGPRRange,	----
1260	unsigned NextFreeSGPR, SMRange SGPRRange,	----
1261	unsigned &VGPRBlocks, unsigned &SGPRBlocks);	----
1262	bool ParseDirectiveAMDGCNTarget();	----
1263	bool ParseDirectiveAMDHSAKernel();	----
1264	bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);	----
1265	bool ParseDirectiveHSACodeObjectVersion();	----
1266	bool ParseDirectiveHSACodeObjectISA();	----
1267	bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);	----
1268	bool ParseDirectiveAMDKernelCodeT();	----
1269	// TODO: Possibly make subtargetHasRegister const.	----
1270	bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);	----
1271	bool ParseDirectiveAMDGPUHsaKernel();	----
1272		----
1273	bool ParseDirectiveISAVersion();	----
1274	bool ParseDirectiveHSAMetadata();	----
1275	bool ParseDirectivePALMetadataBegin();	----
1276	bool ParseDirectivePALMetadata();	----
1277	bool ParseDirectiveAMDGPULDS();	----
1278		----
1279	/// Common code to parse out a block of text (typically YAML) between start and	----
1280	/// end directives.	----
1281	bool ParseToEndDirective(const char *AssemblerDirectiveBegin,	----
1282	const char *AssemblerDirectiveEnd,	----
1283	std::string &CollectString);	----
1284		----
1285	bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,	----
1286	RegisterKind RegKind, unsigned Reg1, SMLoc Loc);	----
1287	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	----
1288	unsigned &RegNum, unsigned &RegWidth,	----
1289	bool RestoreOnFailure = false);	----
1290	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	----
1291	unsigned &RegNum, unsigned &RegWidth,	----
1292	SmallVectorImpl &Tokens);	----
1293	unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,	----
1294	unsigned &RegWidth,	----
1295	SmallVectorImpl &Tokens);	----
1296	unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,	----
1297	unsigned &RegWidth,	----
1298	SmallVectorImpl &Tokens);	----
1299	unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	----
1300	unsigned &RegWidth, SmallVectorImpl &Tokens);	----
1301	bool ParseRegRange(unsigned& Num, unsigned& Width);	----
1302	unsigned getRegularReg(RegisterKind RegKind,	----
1303	unsigned RegNum,	----
1304	unsigned RegWidth,	----
1305	SMLoc Loc);	----
1306		----
1307	bool isRegister();	----
1308	bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;	----
1309	std::optional getGprCountSymbolName(RegisterKind RegKind);	----
1310	void initializeGprCountSymbol(RegisterKind RegKind);	----
1311	bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,	----
1312	unsigned RegWidth);	----
1313	void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,	----
1314	bool IsAtomic);	----
1315		----
1316	public:	----
1317	enum AMDGPUMatchResultTy {	----
1318	Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY	----
1319	};	----
1320	enum OperandMode {	----
1321	OperandMode_Default,	----
1322	OperandMode_NSA,	----
1323	};	----
1324		----
1325	using OptionalImmIndexMap = std::map;	----
1326		----
1327	AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,	0
1328	const MCInstrInfo &MII,	----
1329	const MCTargetOptions &Options)	----
1330	: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {	0
1331	MCAsmParserExtension::Initialize(Parser);	0
1332		----
1333	if (getFeatureBits().none()) {	0
1334	// Set default features.	----
1335	copySTI().ToggleFeature("southern-islands");	0
1336	}	----
1337		----
1338	setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));	0
1339		----
1340	{	----
1341	// TODO: make those pre-defined variables read-only.	----
1342	// Currently there is none suitable machinery in the core llvm-mc for this.	----
1343	// MCSymbol::isRedefinable is intended for another purpose, and	----
1344	// AsmParser::parseDirectiveSet() cannot be specialized for specific target.	----
1345	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
1346	MCContext &Ctx = getContext();	0
1347	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	0
1348	MCSymbol *Sym =	----
1349	Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));	0
1350	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	0
1351	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));	0
1352	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	0
1353	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));	0
1354	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	0
1355	} else {	----
1356	MCSymbol *Sym =	----
1357	Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));	0
1358	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	0
1359	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));	0
1360	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	0
1361	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));	0
1362	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	0
1363	}	----
1364	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	0
1365	initializeGprCountSymbol(IS_VGPR);	0
1366	initializeGprCountSymbol(IS_SGPR);	0
1367	} else	----
1368	KernelScope.initialize(getContext());	0
1369	}	----
1370	}	0
1371		----
1372	bool hasMIMG_R128() const {	0
1373	return AMDGPU::hasMIMG_R128(getSTI());	0
1374	}	----
1375		----
1376	bool hasPackedD16() const {	0
1377	return AMDGPU::hasPackedD16(getSTI());	0
1378	}	----
1379		----
1380	bool hasA16() const { return AMDGPU::hasA16(getSTI()); }	0
1381		----
1382	bool hasG16() const { return AMDGPU::hasG16(getSTI()); }	0
1383		----
1384	bool isSI() const {	0
1385	return AMDGPU::isSI(getSTI());	0
1386	}	----
1387		----
1388	bool isCI() const {	0
1389	return AMDGPU::isCI(getSTI());	0
1390	}	----
1391		----
1392	bool isVI() const {	0
1393	return AMDGPU::isVI(getSTI());	0
1394	}	----
1395		----
1396	bool isGFX9() const {	0
1397	return AMDGPU::isGFX9(getSTI());	0
1398	}	----
1399		----
1400	// TODO: isGFX90A is also true for GFX940. We need to clean it.	----
1401	bool isGFX90A() const {	0
1402	return AMDGPU::isGFX90A(getSTI());	0
1403	}	----
1404		----
1405	bool isGFX940() const {	0
1406	return AMDGPU::isGFX940(getSTI());	0
1407	}	----
1408		----
1409	bool isGFX9Plus() const {	0
1410	return AMDGPU::isGFX9Plus(getSTI());	0
1411	}	----
1412		----
1413	bool isGFX10() const {	----
1414	return AMDGPU::isGFX10(getSTI());	----
1415	}	----
1416		----
1417	bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); }	0
1418		----
1419	bool isGFX11() const {	----
1420	return AMDGPU::isGFX11(getSTI());	----
1421	}	----
1422		----
1423	bool isGFX11Plus() const {	0
1424	return AMDGPU::isGFX11Plus(getSTI());	0
1425	}	----
1426		----
1427	bool isGFX10_AEncoding() const { return AMDGPU::isGFX10_AEncoding(getSTI()); }	0
1428		----
1429	bool isGFX10_BEncoding() const {	----
1430	return AMDGPU::isGFX10_BEncoding(getSTI());	----
1431	}	----
1432		----
1433	bool hasInv2PiInlineImm() const {	0
1434	return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];	0
1435	}	----
1436		----
1437	bool hasFlatOffsets() const {	0
1438	return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];	0
1439	}	----
1440		----
1441	bool hasArchitectedFlatScratch() const {	0
1442	return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];	0
1443	}	----
1444		----
1445	bool hasSGPR102_SGPR103() const {	0
1446	return !isVI() && !isGFX9();	0
1447	}	----
1448		----
1449	bool hasSGPR104_SGPR105() const { return isGFX10Plus(); }	0
1450		----
1451	bool hasIntClamp() const {	0
1452	return getFeatureBits()[AMDGPU::FeatureIntClamp];	0
1453	}	----
1454		----
1455	bool hasPartialNSAEncoding() const {	0
1456	return getFeatureBits()[AMDGPU::FeaturePartialNSAEncoding];	0
1457	}	----
1458		----
1459	unsigned getNSAMaxSize() const {	0
1460	return AMDGPU::getNSAMaxSize(getSTI());	0
1461	}	----
1462		----
1463	AMDGPUTargetStreamer &getTargetStreamer() {	0
1464	MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();	0
1465	return static_cast(TS);	0
1466	}	----
1467		----
1468	const MCRegisterInfo *getMRI() const {	0
1469	// We need this const_cast because for some reason getContext() is not const	----
1470	// in MCAsmParser.	----
1471	return const_cast(this)->getContext().getRegisterInfo();	0
1472	}	----
1473		----
1474	const MCInstrInfo *getMII() const {	0
1475	return &MII;	0
1476	}	----
1477		----
1478	const FeatureBitset &getFeatureBits() const {	0
1479	return getSTI().getFeatureBits();	0
1480	}	----
1481		----
1482	void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }	0
1483	void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }	0
1484	void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }	0
1485		----
1486	unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }	0
1487	bool isForcedVOP3() const { return ForcedEncodingSize == 64; }	0
1488	bool isForcedDPP() const { return ForcedDPP; }	0
1489	bool isForcedSDWA() const { return ForcedSDWA; }	0
1490	ArrayRef getMatchedVariants() const;	----
1491	StringRef getMatchedVariantName() const;	----
1492		----
1493	std::unique_ptr parseRegister(bool RestoreOnFailure = false);	----
1494	bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,	----
1495	bool RestoreOnFailure);	----
1496	bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	----
1497	SMLoc &EndLoc) override;	----
1498	OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	----
1499	SMLoc &EndLoc) override;	----
1500	unsigned checkTargetMatchPredicate(MCInst &Inst) override;	----
1501	unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,	----
1502	unsigned Kind) override;	----
1503	bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	----
1504	OperandVector &Operands, MCStreamer &Out,	----
1505	uint64_t &ErrorInfo,	----
1506	bool MatchingInlineAsm) override;	----
1507	bool ParseDirective(AsmToken DirectiveID) override;	----
1508	ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,	----
1509	OperandMode Mode = OperandMode_Default);	----
1510	StringRef parseMnemonicSuffix(StringRef Name);	----
1511	bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,	----
1512	SMLoc NameLoc, OperandVector &Operands) override;	----
1513	//bool ProcessInstruction(MCInst &Inst);	----
1514		----
1515	ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);	----
1516		----
1517	ParseStatus parseIntWithPrefix(const char *Prefix, int64_t &Int);	----
1518		----
1519	ParseStatus	----
1520	parseIntWithPrefix(const char *Prefix, OperandVector &Operands,	----
1521	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	----
1522	std::function ConvertResult = nullptr);	----
1523		----
1524	ParseStatus parseOperandArrayWithPrefix(	----
1525	const char *Prefix, OperandVector &Operands,	----
1526	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	----
1527	bool (*ConvertResult)(int64_t &) = nullptr);	----
1528		----
1529	ParseStatus	----
1530	parseNamedBit(StringRef Name, OperandVector &Operands,	----
1531	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);	----
1532	unsigned getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const;	----
1533	ParseStatus parseCPol(OperandVector &Operands);	----
1534	ParseStatus parseStringWithPrefix(StringRef Prefix, StringRef &Value,	----
1535	SMLoc &StringLoc);	----
1536		----
1537	bool isModifier();	----
1538	bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	----
1539	bool isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	----
1540	bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	----
1541	bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;	----
1542	bool parseSP3NegModifier();	----
1543	ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);	----
1544	ParseStatus parseReg(OperandVector &Operands);	----
1545	ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);	----
1546	ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,	----
1547	bool AllowImm = true);	----
1548	ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,	----
1549	bool AllowImm = true);	----
1550	ParseStatus parseRegWithFPInputMods(OperandVector &Operands);	----
1551	ParseStatus parseRegWithIntInputMods(OperandVector &Operands);	----
1552	ParseStatus parseVReg32OrOff(OperandVector &Operands);	----
1553	ParseStatus parseDfmtNfmt(int64_t &Format);	----
1554	ParseStatus parseUfmt(int64_t &Format);	----
1555	ParseStatus parseSymbolicSplitFormat(StringRef FormatStr, SMLoc Loc,	----
1556	int64_t &Format);	----
1557	ParseStatus parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc,	----
1558	int64_t &Format);	----
1559	ParseStatus parseFORMAT(OperandVector &Operands);	----
1560	ParseStatus parseSymbolicOrNumericFormat(int64_t &Format);	----
1561	ParseStatus parseNumericFormat(int64_t &Format);	----
1562	ParseStatus parseFlatOffset(OperandVector &Operands);	----
1563	ParseStatus parseR128A16(OperandVector &Operands);	----
1564	ParseStatus parseBLGP(OperandVector &Operands);	----
1565	bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);	----
1566	bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);	----
1567		----
1568	void cvtExp(MCInst &Inst, const OperandVector &Operands);	----
1569		----
1570	bool parseCnt(int64_t &IntVal);	----
1571	ParseStatus parseSWaitCnt(OperandVector &Operands);	----
1572		----
1573	bool parseDepCtr(int64_t &IntVal, unsigned &Mask);	----
1574	void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);	----
1575	ParseStatus parseDepCtr(OperandVector &Operands);	----
1576		----
1577	bool parseDelay(int64_t &Delay);	----
1578	ParseStatus parseSDelayALU(OperandVector &Operands);	----
1579		----
1580	ParseStatus parseHwreg(OperandVector &Operands);	----
1581		----
1582	private:	----
1583	struct OperandInfoTy {	----
1584	SMLoc Loc;	----
1585	int64_t Id;	----
1586	bool IsSymbolic = false;	----
1587	bool IsDefined = false;	----
1588		----
1589	OperandInfoTy(int64_t Id_) : Id(Id_) {}	0
1590	};	----
1591		----
1592	bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);	----
1593	bool validateSendMsg(const OperandInfoTy &Msg,	----
1594	const OperandInfoTy &Op,	----
1595	const OperandInfoTy &Stream);	----
1596		----
1597	bool parseHwregBody(OperandInfoTy &HwReg,	----
1598	OperandInfoTy &Offset,	----
1599	OperandInfoTy &Width);	----
1600	bool validateHwreg(const OperandInfoTy &HwReg,	----
1601	const OperandInfoTy &Offset,	----
1602	const OperandInfoTy &Width);	----
1603		----
1604	SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;	----
1605	SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;	----
1606	SMLoc getBLGPLoc(const OperandVector &Operands) const;	----
1607		----
1608	SMLoc getOperandLoc(std::function Test,	----
1609	const OperandVector &Operands) const;	----
1610	SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;	----
1611	SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;	----
1612	SMLoc getLitLoc(const OperandVector &Operands,	----
1613	bool SearchMandatoryLiterals = false) const;	----
1614	SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;	----
1615	SMLoc getConstLoc(const OperandVector &Operands) const;	----
1616	SMLoc getInstLoc(const OperandVector &Operands) const;	----
1617		----
1618	bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);	----
1619	bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);	----
1620	bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);	----
1621	bool validateSOPLiteral(const MCInst &Inst) const;	----
1622	bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);	----
1623	bool validateVOPDRegBankConstraints(const MCInst &Inst,	----
1624	const OperandVector &Operands);	----
1625	bool validateIntClampSupported(const MCInst &Inst);	----
1626	bool validateMIMGAtomicDMask(const MCInst &Inst);	----
1627	bool validateMIMGGatherDMask(const MCInst &Inst);	----
1628	bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);	----
1629	bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);	----
1630	bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);	----
1631	bool validateMIMGD16(const MCInst &Inst);	----
1632	bool validateMIMGMSAA(const MCInst &Inst);	----
1633	bool validateOpSel(const MCInst &Inst);	----
1634	bool validateDPP(const MCInst &Inst, const OperandVector &Operands);	----
1635	bool validateVccOperand(unsigned Reg) const;	----
1636	bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);	----
1637	bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);	----
1638	bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);	----
1639	bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);	----
1640	bool validateAGPRLdSt(const MCInst &Inst) const;	----
1641	bool validateVGPRAlign(const MCInst &Inst) const;	----
1642	bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);	----
1643	bool validateGWS(const MCInst &Inst, const OperandVector &Operands);	----
1644	bool validateDivScale(const MCInst &Inst);	----
1645	bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);	----
1646	bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,	----
1647	const SMLoc &IDLoc);	----
1648	bool validateExeczVcczOperands(const OperandVector &Operands);	----
1649	bool validateTFE(const MCInst &Inst, const OperandVector &Operands);	----
1650	std::optional validateLdsDirect(const MCInst &Inst);	----
1651	unsigned getConstantBusLimit(unsigned Opcode) const;	----
1652	bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);	----
1653	bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;	----
1654	unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;	----
1655		----
1656	bool isSupportedMnemo(StringRef Mnemo,	----
1657	const FeatureBitset &FBS);	----
1658	bool isSupportedMnemo(StringRef Mnemo,	----
1659	const FeatureBitset &FBS,	----
1660	ArrayRef Variants);	----
1661	bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);	----
1662		----
1663	bool isId(const StringRef Id) const;	----
1664	bool isId(const AsmToken &Token, const StringRef Id) const;	----
1665	bool isToken(const AsmToken::TokenKind Kind) const;	----
1666	StringRef getId() const;	----
1667	bool trySkipId(const StringRef Id);	----
1668	bool trySkipId(const StringRef Pref, const StringRef Id);	----
1669	bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind);	----
1670	bool trySkipToken(const AsmToken::TokenKind Kind);	----
1671	bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);	----
1672	bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");	----
1673	bool parseId(StringRef &Val, const StringRef ErrMsg = "");	----
1674		----
1675	void peekTokens(MutableArrayRef Tokens);	----
1676	AsmToken::TokenKind getTokenKind() const;	----
1677	bool parseExpr(int64_t &Imm, StringRef Expected = "");	----
1678	bool parseExpr(OperandVector &Operands);	----
1679	StringRef getTokenStr() const;	----
1680	AsmToken peekToken(bool ShouldSkipSpace = true);	----
1681	AsmToken getToken() const;	----
1682	SMLoc getLoc() const;	----
1683	void lex();	----
1684		----
1685	public:	----
1686	void onBeginOfFile() override;	----
1687		----
1688	ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);	----
1689		----
1690	ParseStatus parseExpTgt(OperandVector &Operands);	----
1691	ParseStatus parseSendMsg(OperandVector &Operands);	----
1692	ParseStatus parseInterpSlot(OperandVector &Operands);	----
1693	ParseStatus parseInterpAttr(OperandVector &Operands);	----
1694	ParseStatus parseSOPPBrTarget(OperandVector &Operands);	----
1695	ParseStatus parseBoolReg(OperandVector &Operands);	----
1696		----
1697	bool parseSwizzleOperand(int64_t &Op,	----
1698	const unsigned MinVal,	----
1699	const unsigned MaxVal,	----
1700	const StringRef ErrMsg,	----
1701	SMLoc &Loc);	----
1702	bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	----
1703	const unsigned MinVal,	----
1704	const unsigned MaxVal,	----
1705	const StringRef ErrMsg);	----
1706	ParseStatus parseSwizzle(OperandVector &Operands);	----
1707	bool parseSwizzleOffset(int64_t &Imm);	----
1708	bool parseSwizzleMacro(int64_t &Imm);	----
1709	bool parseSwizzleQuadPerm(int64_t &Imm);	----
1710	bool parseSwizzleBitmaskPerm(int64_t &Imm);	----
1711	bool parseSwizzleBroadcast(int64_t &Imm);	----
1712	bool parseSwizzleSwap(int64_t &Imm);	----
1713	bool parseSwizzleReverse(int64_t &Imm);	----
1714		----
1715	ParseStatus parseGPRIdxMode(OperandVector &Operands);	----
1716	int64_t parseGPRIdxMacro();	----
1717		----
1718	void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }	0
1719	void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }	0
1720		----
1721	ParseStatus parseOModSI(OperandVector &Operands);	----
1722		----
1723	void cvtVOP3(MCInst &Inst, const OperandVector &Operands,	----
1724	OptionalImmIndexMap &OptionalIdx);	----
1725	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);	----
1726	void cvtVOP3(MCInst &Inst, const OperandVector &Operands);	----
1727	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);	----
1728	void cvtVOPD(MCInst &Inst, const OperandVector &Operands);	----
1729	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	----
1730	OptionalImmIndexMap &OptionalIdx);	----
1731	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	----
1732	OptionalImmIndexMap &OptionalIdx);	----
1733		----
1734	void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);	----
1735	void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);	----
1736	void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);	----
1737		----
1738	bool parseDimId(unsigned &Encoding);	----
1739	ParseStatus parseDim(OperandVector &Operands);	----
1740	bool convertDppBoundCtrl(int64_t &BoundCtrl);	----
1741	ParseStatus parseDPP8(OperandVector &Operands);	----
1742	ParseStatus parseDPPCtrl(OperandVector &Operands);	----
1743	bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);	----
1744	int64_t parseDPPCtrlSel(StringRef Ctrl);	----
1745	int64_t parseDPPCtrlPerm();	----
1746	void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);	----
1747	void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {	0
1748	cvtDPP(Inst, Operands, true);	0
1749	}	0
1750	void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	----
1751	bool IsDPP8 = false);	----
1752	void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {	0
1753	cvtVOP3DPP(Inst, Operands, true);	0
1754	}	0
1755		----
1756	ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,	----
1757	AMDGPUOperand::ImmTy Type);	----
1758	ParseStatus parseSDWADstUnused(OperandVector &Operands);	----
1759	void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);	----
1760	void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);	----
1761	void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);	----
1762	void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);	----
1763	void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);	----
1764	void cvtSDWA(MCInst &Inst, const OperandVector &Operands,	----
1765	uint64_t BasicInstType,	----
1766	bool SkipDstVcc = false,	----
1767	bool SkipSrcVcc = false);	----
1768		----
1769	ParseStatus parseEndpgm(OperandVector &Operands);	----
1770		----
1771	ParseStatus parseVOPD(OperandVector &Operands);	----
1772	};	----
1773		----
1774	} // end anonymous namespace	----
1775		----
1776	// May be called with integer type with equivalent bitwidth.	----
1777	static const fltSemantics *getFltSemantics(unsigned Size) {	0
1778	switch (Size) {	0
1779	case 4:	0
1780	return &APFloat::IEEEsingle();	0
1781	case 8:	0
1782	return &APFloat::IEEEdouble();	0
1783	case 2:	0
1784	return &APFloat::IEEEhalf();	0
1785	default:	0
1786	llvm_unreachable("unsupported fp type");	0
1787	}	----
1788	}	----
1789		----
1790	static const fltSemantics *getFltSemantics(MVT VT) {	0
1791	return getFltSemantics(VT.getSizeInBits() / 8);	0
1792	}	----
1793		----
1794	static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {	0
1795	switch (OperandType) {	0
1796	case AMDGPU::OPERAND_REG_IMM_INT32:	0
1797	case AMDGPU::OPERAND_REG_IMM_FP32:	----
1798	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	----
1799	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	----
1800	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	----
1801	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	----
1802	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	----
1803	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	----
1804	case AMDGPU::OPERAND_REG_IMM_V2FP32:	----
1805	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	----
1806	case AMDGPU::OPERAND_REG_IMM_V2INT32:	----
1807	case AMDGPU::OPERAND_KIMM32:	----
1808	return &APFloat::IEEEsingle();	0
1809	case AMDGPU::OPERAND_REG_IMM_INT64:	0
1810	case AMDGPU::OPERAND_REG_IMM_FP64:	----
1811	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	----
1812	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	----
1813	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	----
1814	return &APFloat::IEEEdouble();	0
1815	case AMDGPU::OPERAND_REG_IMM_INT16:	0
1816	case AMDGPU::OPERAND_REG_IMM_FP16:	----
1817	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	----
1818	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	----
1819	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	----
1820	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	----
1821	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	----
1822	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	----
1823	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	----
1824	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	----
1825	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	----
1826	case AMDGPU::OPERAND_REG_IMM_V2INT16:	----
1827	case AMDGPU::OPERAND_REG_IMM_V2FP16:	----
1828	case AMDGPU::OPERAND_KIMM16:	----
1829	return &APFloat::IEEEhalf();	0
1830	default:	0
1831	llvm_unreachable("unsupported fp type");	0
1832	}	----
1833	}	----
1834		----
1835	//===----------------------------------------------------------------------===//	----
1836	// Operand	----
1837	//===----------------------------------------------------------------------===//	----
1838		----
1839	static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) {	0
1840	bool Lost;	----
1841		----
1842	// Convert literal to single precision	----
1843	APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT),	0
1844	APFloat::rmNearestTiesToEven,	----
1845	&Lost);	----
1846	// We allow precision lost but not overflow or underflow	----
1847	if (Status != APFloat::opOK &&	0
1848	Lost &&	0
1849	((Status & APFloat::opOverflow) != 0 \|\|	0
1850	(Status & APFloat::opUnderflow) != 0)) {	0
1851	return false;	0
1852	}	----
1853		----
1854	return true;	0
1855	}	----
1856		----
1857	static bool isSafeTruncation(int64_t Val, unsigned Size) {	0
1858	return isUIntN(Size, Val) \|\| isIntN(Size, Val);	0
1859	}	----
1860		----
1861	static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) {	0
1862	if (VT.getScalarType() == MVT::i16) {	0
1863	// FP immediate values are broken.	----
1864	return isInlinableIntLiteral(Val);	0
1865	}	----
1866		----
1867	// f16/v2f16 operands work correctly for all values.	----
1868	return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi);	0
1869	}	----
1870		----
1871	bool AMDGPUOperand::isInlinableImm(MVT type) const {	0
1872		----
1873	// This is a hack to enable named inline values like	----
1874	// shared_base with both 32-bit and 64-bit operands.	----
1875	// Note that these values are defined as	----
1876	// 32-bit operands only.	----
1877	if (isInlineValue()) {	0
1878	return true;	0
1879	}	----
1880		----
1881	if (!isImmTy(ImmTyNone)) {	0
1882	// Only plain immediates are inlinable (e.g. "clamp" attribute is not)	----
1883	return false;	0
1884	}	----
1885	// TODO: We should avoid using host float here. It would be better to	----
1886	// check the float bit values which is what a few other places do.	----
1887	// We've had bot failures before due to weird NaN support on mips hosts.	----
1888		----
1889	APInt Literal(64, Imm.Val);	0
1890		----
1891	if (Imm.IsFPImm) { // We got fp literal token	0
1892	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	0
1893	return AMDGPU::isInlinableLiteral64(Imm.Val,	0
1894	AsmParser->hasInv2PiInlineImm());	0
1895	}	----
1896		----
1897	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	0
1898	if (!canLosslesslyConvertToFPType(FPLiteral, type))	0
1899	return false;	0
1900		----
1901	if (type.getScalarSizeInBits() == 16) {	0
1902	return isInlineableLiteralOp16(	0
1903	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	0
1904	type, AsmParser->hasInv2PiInlineImm());	0
1905	}	----
1906		----
1907	// Check if single precision literal is inlinable	----
1908	return AMDGPU::isInlinableLiteral32(	0
1909	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	0
1910	AsmParser->hasInv2PiInlineImm());	0
1911	}	0
1912		----
1913	// We got int literal token.	----
1914	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	0
1915	return AMDGPU::isInlinableLiteral64(Imm.Val,	0
1916	AsmParser->hasInv2PiInlineImm());	0
1917	}	----
1918		----
1919	if (!isSafeTruncation(Imm.Val, type.getScalarSizeInBits())) {	0
1920	return false;	0
1921	}	----
1922		----
1923	if (type.getScalarSizeInBits() == 16) {	0
1924	return isInlineableLiteralOp16(	0
1925	static_cast(Literal.getLoBits(16).getSExtValue()),	0
1926	type, AsmParser->hasInv2PiInlineImm());	0
1927	}	----
1928		----
1929	return AMDGPU::isInlinableLiteral32(	0
1930	static_cast(Literal.getLoBits(32).getZExtValue()),	0
1931	AsmParser->hasInv2PiInlineImm());	0
1932	}	0
1933		----
1934	bool AMDGPUOperand::isLiteralImm(MVT type) const {	0
1935	// Check that this immediate can be added as literal	----
1936	if (!isImmTy(ImmTyNone)) {	0
1937	return false;	0
1938	}	----
1939		----
1940	if (!Imm.IsFPImm) {	0
1941	// We got int literal token.	----
1942		----
1943	if (type == MVT::f64 && hasFPModifiers()) {	0
1944	// Cannot apply fp modifiers to int literals preserving the same semantics	----
1945	// for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,	----
1946	// disable these cases.	----
1947	return false;	0
1948	}	----
1949		----
1950	unsigned Size = type.getSizeInBits();	0
1951	if (Size == 64)	0
1952	Size = 32;	0
1953		----
1954	// FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP	----
1955	// types.	----
1956	return isSafeTruncation(Imm.Val, Size);	0
1957	}	----
1958		----
1959	// We got fp literal token	----
1960	if (type == MVT::f64) { // Expected 64-bit fp operand	0
1961	// We would set low 64-bits of literal to zeroes but we accept this literals	----
1962	return true;	0
1963	}	----
1964		----
1965	if (type == MVT::i64) { // Expected 64-bit int operand	0
1966	// We don't allow fp literals in 64-bit integer instructions. It is	----
1967	// unclear how we should encode them.	----
1968	return false;	0
1969	}	----
1970		----
1971	// We allow fp literals with f16x2 operands assuming that the specified	----
1972	// literal goes into the lower half and the upper half is zero. We also	----
1973	// require that the literal may be losslessly converted to f16.	----
1974	MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :	0
1975	(type == MVT::v2i16)? MVT::i16 :	0
1976	(type == MVT::v2f32)? MVT::f32 : type;	0
1977		----
1978	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	0
1979	return canLosslesslyConvertToFPType(FPLiteral, ExpectedType);	0
1980	}	0
1981		----
1982	bool AMDGPUOperand::isRegClass(unsigned RCID) const {	0
1983	return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());	0
1984	}	----
1985		----
1986	bool AMDGPUOperand::isVRegWithInputMods() const {	0
1987	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	0
1988	// GFX90A allows DPP on 64-bit operands.	----
1989	(isRegClass(AMDGPU::VReg_64RegClassID) &&	0
1990	AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]);	0
1991	}	----
1992		----
1993	bool AMDGPUOperand::isT16VRegWithInputMods() const {	0
1994	return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID);	0
1995	}	----
1996		----
1997	bool AMDGPUOperand::isSDWAOperand(MVT type) const {	0
1998	if (AsmParser->isVI())	0
1999	return isVReg32();	0
2000	else if (AsmParser->isGFX9Plus())	0
2001	return isRegClass(AMDGPU::VS_32RegClassID) \|\| isInlinableImm(type);	0
2002	else	----
2003	return false;	0
2004	}	----
2005		----
2006	bool AMDGPUOperand::isSDWAFP16Operand() const {	0
2007	return isSDWAOperand(MVT::f16);	0
2008	}	----
2009		----
2010	bool AMDGPUOperand::isSDWAFP32Operand() const {	0
2011	return isSDWAOperand(MVT::f32);	0
2012	}	----
2013		----
2014	bool AMDGPUOperand::isSDWAInt16Operand() const {	0
2015	return isSDWAOperand(MVT::i16);	0
2016	}	----
2017		----
2018	bool AMDGPUOperand::isSDWAInt32Operand() const {	0
2019	return isSDWAOperand(MVT::i32);	0
2020	}	----
2021		----
2022	bool AMDGPUOperand::isBoolReg() const {	0
2023	auto FB = AsmParser->getFeatureBits();	0
2024	return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) \|\|	0
2025	(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));	0
2026	}	----
2027		----
2028	uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const	0
2029	{	----
2030	assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	0
2031	assert(Size == 2 \|\| Size == 4 \|\| Size == 8);	0
2032		----
2033	const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));	0
2034		----
2035	if (Imm.Mods.Abs) {	0
2036	Val &= ~FpSignMask;	0
2037	}	----
2038	if (Imm.Mods.Neg) {	0
2039	Val ^= FpSignMask;	0
2040	}	----
2041		----
2042	return Val;	0
2043	}	----
2044		----
2045	void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {	0
2046	if (isExpr()) {	0
2047	Inst.addOperand(MCOperand::createExpr(Expr));	0
2048	return;	0
2049	}	----
2050		----
2051	if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),	0
2052	Inst.getNumOperands())) {	----
2053	addLiteralImmOperand(Inst, Imm.Val,	0
2054	ApplyModifiers &	0
2055	isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	0
2056	} else {	----
2057	assert(!isImmTy(ImmTyNone) \|\| !hasModifiers());	0
2058	Inst.addOperand(MCOperand::createImm(Imm.Val));	0
2059	setImmKindNone();	0
2060	}	----
2061	}	----
2062		----
2063	void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {	0
2064	const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());	0
2065	auto OpNum = Inst.getNumOperands();	0
2066	// Check that this operand accepts literals	----
2067	assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));	0
2068		----
2069	if (ApplyModifiers) {	0
2070	assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));	0
2071	const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);	0
2072	Val = applyInputFPModifiers(Val, Size);	0
2073	}	----
2074		----
2075	APInt Literal(64, Val);	0
2076	uint8_t OpTy = InstDesc.operands()[OpNum].OperandType;	0
2077		----
2078	if (Imm.IsFPImm) { // We got fp literal token	0
2079	switch (OpTy) {	0
2080	case AMDGPU::OPERAND_REG_IMM_INT64:	0
2081	case AMDGPU::OPERAND_REG_IMM_FP64:	----
2082	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	----
2083	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	----
2084	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	----
2085	if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),	0
2086	AsmParser->hasInv2PiInlineImm())) {	0
2087	Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));	0
2088	setImmKindConst();	0
2089	return;	0
2090	}	----
2091		----
2092	// Non-inlineable	----
2093	if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand	0
2094	// For fp operands we check if low 32 bits are zeros	----
2095	if (Literal.getLoBits(32) != 0) {	0
2096	const_cast(AsmParser)->Warning(Inst.getLoc(),	0
2097	"Can't encode literal as exact 64-bit floating-point operand. "	----
2098	"Low 32-bits will be set to zero");	----
2099	}	----
2100		----
2101	Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue()));	0
2102	setImmKindLiteral();	0
2103	return;	0
2104	}	----
2105		----
2106	// We don't allow fp literals in 64-bit integer instructions. It is	----
2107	// unclear how we should encode them. This case should be checked earlier	----
2108	// in predicate methods (isLiteralImm())	----
2109	llvm_unreachable("fp literal in 64-bit integer instruction.");	0
2110		----
2111	case AMDGPU::OPERAND_REG_IMM_INT32:	0
2112	case AMDGPU::OPERAND_REG_IMM_FP32:	----
2113	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	----
2114	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	----
2115	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	----
2116	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	----
2117	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	----
2118	case AMDGPU::OPERAND_REG_IMM_INT16:	----
2119	case AMDGPU::OPERAND_REG_IMM_FP16:	----
2120	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	----
2121	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	----
2122	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	----
2123	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	----
2124	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	----
2125	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	----
2126	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	----
2127	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	----
2128	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	----
2129	case AMDGPU::OPERAND_REG_IMM_V2INT16:	----
2130	case AMDGPU::OPERAND_REG_IMM_V2FP16:	----
2131	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	----
2132	case AMDGPU::OPERAND_REG_IMM_V2FP32:	----
2133	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	----
2134	case AMDGPU::OPERAND_REG_IMM_V2INT32:	----
2135	case AMDGPU::OPERAND_KIMM32:	----
2136	case AMDGPU::OPERAND_KIMM16: {	----
2137	bool lost;	----
2138	APFloat FPLiteral(APFloat::IEEEdouble(), Literal);	0
2139	// Convert literal to single precision	----
2140	FPLiteral.convert(*getOpFltSemantics(OpTy),	0
2141	APFloat::rmNearestTiesToEven, &lost);	----
2142	// We allow precision lost but not overflow or underflow. This should be	----
2143	// checked earlier in isLiteralImm()	----
2144		----
2145	uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();	0
2146	Inst.addOperand(MCOperand::createImm(ImmVal));	0
2147	if (OpTy == AMDGPU::OPERAND_KIMM32 \|\| OpTy == AMDGPU::OPERAND_KIMM16) {	0
2148	setImmKindMandatoryLiteral();	0
2149	} else {	----
2150	setImmKindLiteral();	0
2151	}	----
2152	return;	0
2153	}	0
2154	default:	0
2155	llvm_unreachable("invalid operand size");	0
2156	}	----
2157		----
2158	return;	----
2159	}	----
2160		----
2161	// We got int literal token.	----
2162	// Only sign extend inline immediates.	----
2163	switch (OpTy) {	0
2164	case AMDGPU::OPERAND_REG_IMM_INT32:	0
2165	case AMDGPU::OPERAND_REG_IMM_FP32:	----
2166	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	----
2167	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	----
2168	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	----
2169	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	----
2170	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	----
2171	case AMDGPU::OPERAND_REG_IMM_V2INT16:	----
2172	case AMDGPU::OPERAND_REG_IMM_V2FP16:	----
2173	case AMDGPU::OPERAND_REG_IMM_V2FP32:	----
2174	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	----
2175	case AMDGPU::OPERAND_REG_IMM_V2INT32:	----
2176	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	----
2177	if (isSafeTruncation(Val, 32) &&	0
2178	AMDGPU::isInlinableLiteral32(static_cast(Val),	0
2179	AsmParser->hasInv2PiInlineImm())) {	0
2180	Inst.addOperand(MCOperand::createImm(Val));	0
2181	setImmKindConst();	0
2182	return;	0
2183	}	----
2184		----
2185	Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));	0
2186	setImmKindLiteral();	0
2187	return;	0
2188		----
2189	case AMDGPU::OPERAND_REG_IMM_INT64:	0
2190	case AMDGPU::OPERAND_REG_IMM_FP64:	----
2191	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	----
2192	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	----
2193	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	----
2194	if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {	0
2195	Inst.addOperand(MCOperand::createImm(Val));	0
2196	setImmKindConst();	0
2197	return;	0
2198	}	----
2199		----
2200	Inst.addOperand(MCOperand::createImm(Lo_32(Val)));	0
2201	setImmKindLiteral();	0
2202	return;	0
2203		----
2204	case AMDGPU::OPERAND_REG_IMM_INT16:	0
2205	case AMDGPU::OPERAND_REG_IMM_FP16:	----
2206	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	----
2207	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	----
2208	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	----
2209	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	----
2210	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	----
2211	if (isSafeTruncation(Val, 16) &&	0
2212	AMDGPU::isInlinableLiteral16(static_cast(Val),	0
2213	AsmParser->hasInv2PiInlineImm())) {	0
2214	Inst.addOperand(MCOperand::createImm(Val));	0
2215	setImmKindConst();	0
2216	return;	0
2217	}	----
2218		----
2219	Inst.addOperand(MCOperand::createImm(Val & 0xffff));	0
2220	setImmKindLiteral();	0
2221	return;	0
2222		----
2223	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	0
2224	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	----
2225	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	----
2226	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {	----
2227	assert(isSafeTruncation(Val, 16));	0
2228	assert(AMDGPU::isInlinableLiteral16(static_cast(Val),	0
2229	AsmParser->hasInv2PiInlineImm()));	----
2230		----
2231	Inst.addOperand(MCOperand::createImm(Val));	0
2232	return;	0
2233	}	----
2234	case AMDGPU::OPERAND_KIMM32:	0
2235	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));	0
2236	setImmKindMandatoryLiteral();	0
2237	return;	0
2238	case AMDGPU::OPERAND_KIMM16:	0
2239	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));	0
2240	setImmKindMandatoryLiteral();	0
2241	return;	0
2242	default:	0
2243	llvm_unreachable("invalid operand size");	0
2244	}	----
2245	}	0
2246		----
2247	void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {	0
2248	Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));	0
2249	}	0
2250		----
2251	bool AMDGPUOperand::isInlineValue() const {	0
2252	return isRegKind() && ::isInlineValue(getReg());	0
2253	}	----
2254		----
2255	//===----------------------------------------------------------------------===//	----
2256	// AsmParser	----
2257	//===----------------------------------------------------------------------===//	----
2258		----
2259	static int getRegClass(RegisterKind Is, unsigned RegWidth) {	0
2260	if (Is == IS_VGPR) {	0
2261	switch (RegWidth) {	0
2262	default: return -1;	0
2263	case 32:	0
2264	return AMDGPU::VGPR_32RegClassID;	0
2265	case 64:	0
2266	return AMDGPU::VReg_64RegClassID;	0
2267	case 96:	0
2268	return AMDGPU::VReg_96RegClassID;	0
2269	case 128:	0
2270	return AMDGPU::VReg_128RegClassID;	0
2271	case 160:	0
2272	return AMDGPU::VReg_160RegClassID;	0
2273	case 192:	0
2274	return AMDGPU::VReg_192RegClassID;	0
2275	case 224:	0
2276	return AMDGPU::VReg_224RegClassID;	0
2277	case 256:	0
2278	return AMDGPU::VReg_256RegClassID;	0
2279	case 288:	0
2280	return AMDGPU::VReg_288RegClassID;	0
2281	case 320:	0
2282	return AMDGPU::VReg_320RegClassID;	0
2283	case 352:	0
2284	return AMDGPU::VReg_352RegClassID;	0
2285	case 384:	0
2286	return AMDGPU::VReg_384RegClassID;	0
2287	case 512:	0
2288	return AMDGPU::VReg_512RegClassID;	0
2289	case 1024:	0
2290	return AMDGPU::VReg_1024RegClassID;	0
2291	}	----
2292	} else if (Is == IS_TTMP) {	0
2293	switch (RegWidth) {	0
2294	default: return -1;	0
2295	case 32:	0
2296	return AMDGPU::TTMP_32RegClassID;	0
2297	case 64:	0
2298	return AMDGPU::TTMP_64RegClassID;	0
2299	case 128:	0
2300	return AMDGPU::TTMP_128RegClassID;	0
2301	case 256:	0
2302	return AMDGPU::TTMP_256RegClassID;	0
2303	case 512:	0
2304	return AMDGPU::TTMP_512RegClassID;	0
2305	}	----
2306	} else if (Is == IS_SGPR) {	0
2307	switch (RegWidth) {	0
2308	default: return -1;	0
2309	case 32:	0
2310	return AMDGPU::SGPR_32RegClassID;	0
2311	case 64:	0
2312	return AMDGPU::SGPR_64RegClassID;	0
2313	case 96:	0
2314	return AMDGPU::SGPR_96RegClassID;	0
2315	case 128:	0
2316	return AMDGPU::SGPR_128RegClassID;	0
2317	case 160:	0
2318	return AMDGPU::SGPR_160RegClassID;	0
2319	case 192:	0
2320	return AMDGPU::SGPR_192RegClassID;	0
2321	case 224:	0
2322	return AMDGPU::SGPR_224RegClassID;	0
2323	case 256:	0
2324	return AMDGPU::SGPR_256RegClassID;	0
2325	case 288:	0
2326	return AMDGPU::SGPR_288RegClassID;	0
2327	case 320:	0
2328	return AMDGPU::SGPR_320RegClassID;	0
2329	case 352:	0
2330	return AMDGPU::SGPR_352RegClassID;	0
2331	case 384:	0
2332	return AMDGPU::SGPR_384RegClassID;	0
2333	case 512:	0
2334	return AMDGPU::SGPR_512RegClassID;	0
2335	}	----
2336	} else if (Is == IS_AGPR) {	0
2337	switch (RegWidth) {	0
2338	default: return -1;	0
2339	case 32:	0
2340	return AMDGPU::AGPR_32RegClassID;	0
2341	case 64:	0
2342	return AMDGPU::AReg_64RegClassID;	0
2343	case 96:	0
2344	return AMDGPU::AReg_96RegClassID;	0
2345	case 128:	0
2346	return AMDGPU::AReg_128RegClassID;	0
2347	case 160:	0
2348	return AMDGPU::AReg_160RegClassID;	0
2349	case 192:	0
2350	return AMDGPU::AReg_192RegClassID;	0
2351	case 224:	0
2352	return AMDGPU::AReg_224RegClassID;	0
2353	case 256:	0
2354	return AMDGPU::AReg_256RegClassID;	0
2355	case 288:	0
2356	return AMDGPU::AReg_288RegClassID;	0
2357	case 320:	0
2358	return AMDGPU::AReg_320RegClassID;	0
2359	case 352:	0
2360	return AMDGPU::AReg_352RegClassID;	0
2361	case 384:	0
2362	return AMDGPU::AReg_384RegClassID;	0
2363	case 512:	0
2364	return AMDGPU::AReg_512RegClassID;	0
2365	case 1024:	0
2366	return AMDGPU::AReg_1024RegClassID;	0
2367	}	----
2368	}	----
2369	return -1;	0
2370	}	----
2371		----
2372	static unsigned getSpecialRegForName(StringRef RegName) {	0
2373	return StringSwitch(RegName)	0
2374	.Case("exec", AMDGPU::EXEC)	0
2375	.Case("vcc", AMDGPU::VCC)	0
2376	.Case("flat_scratch", AMDGPU::FLAT_SCR)	0
2377	.Case("xnack_mask", AMDGPU::XNACK_MASK)	0
2378	.Case("shared_base", AMDGPU::SRC_SHARED_BASE)	0
2379	.Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)	0
2380	.Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT)	0
2381	.Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)	0
2382	.Case("private_base", AMDGPU::SRC_PRIVATE_BASE)	0
2383	.Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)	0
2384	.Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	0
2385	.Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	0
2386	.Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	0
2387	.Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	0
2388	.Case("lds_direct", AMDGPU::LDS_DIRECT)	0
2389	.Case("src_lds_direct", AMDGPU::LDS_DIRECT)	0
2390	.Case("m0", AMDGPU::M0)	0
2391	.Case("vccz", AMDGPU::SRC_VCCZ)	0
2392	.Case("src_vccz", AMDGPU::SRC_VCCZ)	0
2393	.Case("execz", AMDGPU::SRC_EXECZ)	0
2394	.Case("src_execz", AMDGPU::SRC_EXECZ)	0
2395	.Case("scc", AMDGPU::SRC_SCC)	0
2396	.Case("src_scc", AMDGPU::SRC_SCC)	0
2397	.Case("tba", AMDGPU::TBA)	0
2398	.Case("tma", AMDGPU::TMA)	0
2399	.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)	0
2400	.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)	0
2401	.Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)	0
2402	.Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)	0
2403	.Case("vcc_lo", AMDGPU::VCC_LO)	0
2404	.Case("vcc_hi", AMDGPU::VCC_HI)	0
2405	.Case("exec_lo", AMDGPU::EXEC_LO)	0
2406	.Case("exec_hi", AMDGPU::EXEC_HI)	0
2407	.Case("tma_lo", AMDGPU::TMA_LO)	0
2408	.Case("tma_hi", AMDGPU::TMA_HI)	0
2409	.Case("tba_lo", AMDGPU::TBA_LO)	0
2410	.Case("tba_hi", AMDGPU::TBA_HI)	0
2411	.Case("pc", AMDGPU::PC_REG)	0
2412	.Case("null", AMDGPU::SGPR_NULL)	0
2413	.Default(AMDGPU::NoRegister);	0
2414	}	----
2415		----
2416	bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	0
2417	SMLoc &EndLoc, bool RestoreOnFailure) {	----
2418	auto R = parseRegister();	0
2419	if (!R) return true;	0
2420	assert(R->isReg());	0
2421	RegNo = R->getReg();	0
2422	StartLoc = R->getStartLoc();	0
2423	EndLoc = R->getEndLoc();	0
2424	return false;	0
2425	}	0
2426		----
2427	bool AMDGPUAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	0
2428	SMLoc &EndLoc) {	----
2429	return ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/false);	0
2430	}	----
2431		----
2432	OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(MCRegister &RegNo,	0
2433	SMLoc &StartLoc,	----
2434	SMLoc &EndLoc) {	----
2435	bool Result =	----
2436	ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/true);	0
2437	bool PendingErrors = getParser().hasPendingError();	0
2438	getParser().clearPendingErrors();	0
2439	if (PendingErrors)	0
2440	return MatchOperand_ParseFail;	0
2441	if (Result)	0
2442	return MatchOperand_NoMatch;	0
2443	return MatchOperand_Success;	0
2444	}	----
2445		----
2446	bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,	0
2447	RegisterKind RegKind, unsigned Reg1,	----
2448	SMLoc Loc) {	----
2449	switch (RegKind) {	0
2450	case IS_SPECIAL:	0
2451	if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {	0
2452	Reg = AMDGPU::EXEC;	0
2453	RegWidth = 64;	0
2454	return true;	0
2455	}	----
2456	if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {	0
2457	Reg = AMDGPU::FLAT_SCR;	0
2458	RegWidth = 64;	0
2459	return true;	0
2460	}	----
2461	if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {	0
2462	Reg = AMDGPU::XNACK_MASK;	0
2463	RegWidth = 64;	0
2464	return true;	0
2465	}	----
2466	if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {	0
2467	Reg = AMDGPU::VCC;	0
2468	RegWidth = 64;	0
2469	return true;	0
2470	}	----
2471	if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {	0
2472	Reg = AMDGPU::TBA;	0
2473	RegWidth = 64;	0
2474	return true;	0
2475	}	----
2476	if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {	0
2477	Reg = AMDGPU::TMA;	0
2478	RegWidth = 64;	0
2479	return true;	0
2480	}	----
2481	Error(Loc, "register does not fit in the list");	0
2482	return false;	0
2483	case IS_VGPR:	0
2484	case IS_SGPR:	----
2485	case IS_AGPR:	----
2486	case IS_TTMP:	----
2487	if (Reg1 != Reg + RegWidth / 32) {	0
2488	Error(Loc, "registers in a list must have consecutive indices");	0
2489	return false;	0
2490	}	----
2491	RegWidth += 32;	0
2492	return true;	0
2493	default:	0
2494	llvm_unreachable("unexpected register kind");	0
2495	}	----
2496	}	----
2497		----
2498	struct RegInfo {	----
2499	StringLiteral Name;	----
2500	RegisterKind Kind;	----
2501	};	----
2502		----
2503	static constexpr RegInfo RegularRegisters[] = {	----
2504	{{"v"}, IS_VGPR},	----
2505	{{"s"}, IS_SGPR},	----
2506	{{"ttmp"}, IS_TTMP},	----
2507	{{"acc"}, IS_AGPR},	----
2508	{{"a"}, IS_AGPR},	----
2509	};	----
2510		----
2511	static bool isRegularReg(RegisterKind Kind) {	0
2512	return Kind == IS_VGPR \|\|	0
2513	Kind == IS_SGPR \|\|	0
2514	Kind == IS_TTMP \|\|	0
2515	Kind == IS_AGPR;	0
2516	}	----
2517		----
2518	static const RegInfo* getRegularRegInfo(StringRef Str) {	0
2519	for (const RegInfo &Reg : RegularRegisters)	0
2520	if (Str.startswith(Reg.Name))	0
2521	return &Reg;	0
2522	return nullptr;	0
2523	}	----
2524		----
2525	static bool getRegNum(StringRef Str, unsigned& Num) {	0
2526	return !Str.getAsInteger(10, Num);	0
2527	}	----
2528		----
2529	bool	----
2530	AMDGPUAsmParser::isRegister(const AsmToken &Token,	0
2531	const AsmToken &NextToken) const {	----
2532		----
2533	// A list of consecutive registers: [s0,s1,s2,s3]	----
2534	if (Token.is(AsmToken::LBrac))	0
2535	return true;	0
2536		----
2537	if (!Token.is(AsmToken::Identifier))	0
2538	return false;	0
2539		----
2540	// A single register like s0 or a range of registers like s[0:1]	----
2541		----
2542	StringRef Str = Token.getString();	0
2543	const RegInfo *Reg = getRegularRegInfo(Str);	0
2544	if (Reg) {	0
2545	StringRef RegName = Reg->Name;	0
2546	StringRef RegSuffix = Str.substr(RegName.size());	0
2547	if (!RegSuffix.empty()) {	0
2548	unsigned Num;	----
2549	// A single register with an index: rXX	----
2550	if (getRegNum(RegSuffix, Num))	0
2551	return true;	0
2552	} else {	----
2553	// A range of registers: r[XX:YY].	----
2554	if (NextToken.is(AsmToken::LBrac))	0
2555	return true;	0
2556	}	----
2557	}	----
2558		----
2559	return getSpecialRegForName(Str) != AMDGPU::NoRegister;	0
2560	}	----
2561		----
2562	bool	----
2563	AMDGPUAsmParser::isRegister()	0
2564	{	----
2565	return isRegister(getToken(), peekToken());	0
2566	}	----
2567		----
2568	unsigned	----
2569	AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,	0
2570	unsigned RegNum,	----
2571	unsigned RegWidth,	----
2572	SMLoc Loc) {	----
2573		----
2574	assert(isRegularReg(RegKind));	0
2575		----
2576	unsigned AlignSize = 1;	0
2577	if (RegKind == IS_SGPR \|\| RegKind == IS_TTMP) {	0
2578	// SGPR and TTMP registers must be aligned.	----
2579	// Max required alignment is 4 dwords.	----
2580	AlignSize = std::min(RegWidth / 32, 4u);	0
2581	}	----
2582		----
2583	if (RegNum % AlignSize != 0) {	0
2584	Error(Loc, "invalid register alignment");	0
2585	return AMDGPU::NoRegister;	0
2586	}	----
2587		----
2588	unsigned RegIdx = RegNum / AlignSize;	0
2589	int RCID = getRegClass(RegKind, RegWidth);	0
2590	if (RCID == -1) {	0
2591	Error(Loc, "invalid or unsupported register size");	0
2592	return AMDGPU::NoRegister;	0
2593	}	----
2594		----
2595	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
2596	const MCRegisterClass RC = TRI->getRegClass(RCID);	0
2597	if (RegIdx >= RC.getNumRegs()) {	0
2598	Error(Loc, "register index is out of range");	0
2599	return AMDGPU::NoRegister;	0
2600	}	----
2601		----
2602	return RC.getRegister(RegIdx);	0
2603	}	----
2604		----
2605	bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {	0
2606	int64_t RegLo, RegHi;	----
2607	if (!skipToken(AsmToken::LBrac, "missing register index"))	0
2608	return false;	0
2609		----
2610	SMLoc FirstIdxLoc = getLoc();	0
2611	SMLoc SecondIdxLoc;	0
2612		----
2613	if (!parseExpr(RegLo))	0
2614	return false;	0
2615		----
2616	if (trySkipToken(AsmToken::Colon)) {	0
2617	SecondIdxLoc = getLoc();	0
2618	if (!parseExpr(RegHi))	0
2619	return false;	0
2620	} else {	----
2621	RegHi = RegLo;	0
2622	}	----
2623		----
2624	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
2625	return false;	0
2626		----
2627	if (!isUInt<32>(RegLo)) {	0
2628	Error(FirstIdxLoc, "invalid register index");	0
2629	return false;	0
2630	}	----
2631		----
2632	if (!isUInt<32>(RegHi)) {	0
2633	Error(SecondIdxLoc, "invalid register index");	0
2634	return false;	0
2635	}	----
2636		----
2637	if (RegLo > RegHi) {	0
2638	Error(FirstIdxLoc, "first register index should not exceed second index");	0
2639	return false;	0
2640	}	----
2641		----
2642	Num = static_cast(RegLo);	0
2643	RegWidth = 32 * ((RegHi - RegLo) + 1);	0
2644	return true;	0
2645	}	----
2646		----
2647	unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,	0
2648	unsigned &RegNum, unsigned &RegWidth,	----
2649	SmallVectorImpl &Tokens) {	----
2650	assert(isToken(AsmToken::Identifier));	0
2651	unsigned Reg = getSpecialRegForName(getTokenStr());	0
2652	if (Reg) {	0
2653	RegNum = 0;	0
2654	RegWidth = 32;	0
2655	RegKind = IS_SPECIAL;	0
2656	Tokens.push_back(getToken());	0
2657	lex(); // skip register name	0
2658	}	----
2659	return Reg;	0
2660	}	----
2661		----
2662	unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,	0
2663	unsigned &RegNum, unsigned &RegWidth,	----
2664	SmallVectorImpl &Tokens) {	----
2665	assert(isToken(AsmToken::Identifier));	0
2666	StringRef RegName = getTokenStr();	0
2667	auto Loc = getLoc();	0
2668		----
2669	const RegInfo *RI = getRegularRegInfo(RegName);	0
2670	if (!RI) {	0
2671	Error(Loc, "invalid register name");	0
2672	return AMDGPU::NoRegister;	0
2673	}	----
2674		----
2675	Tokens.push_back(getToken());	0
2676	lex(); // skip register name	0
2677		----
2678	RegKind = RI->Kind;	0
2679	StringRef RegSuffix = RegName.substr(RI->Name.size());	0
2680	if (!RegSuffix.empty()) {	0
2681	// Single 32-bit register: vXX.	----
2682	if (!getRegNum(RegSuffix, RegNum)) {	0
2683	Error(Loc, "invalid register index");	0
2684	return AMDGPU::NoRegister;	0
2685	}	----
2686	RegWidth = 32;	0
2687	} else {	----
2688	// Range of registers: v[XX:YY]. ":YY" is optional.	----
2689	if (!ParseRegRange(RegNum, RegWidth))	0
2690	return AMDGPU::NoRegister;	0
2691	}	----
2692		----
2693	return getRegularReg(RegKind, RegNum, RegWidth, Loc);	0
2694	}	----
2695		----
2696	unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	0
2697	unsigned &RegWidth,	----
2698	SmallVectorImpl &Tokens) {	----
2699	unsigned Reg = AMDGPU::NoRegister;	0
2700	auto ListLoc = getLoc();	0
2701		----
2702	if (!skipToken(AsmToken::LBrac,	0
2703	"expected a register or a list of registers")) {	----
2704	return AMDGPU::NoRegister;	0
2705	}	----
2706		----
2707	// List of consecutive registers, e.g.: [s0,s1,s2,s3]	----
2708		----
2709	auto Loc = getLoc();	0
2710	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))	0
2711	return AMDGPU::NoRegister;	0
2712	if (RegWidth != 32) {	0
2713	Error(Loc, "expected a single 32-bit register");	0
2714	return AMDGPU::NoRegister;	0
2715	}	----
2716		----
2717	for (; trySkipToken(AsmToken::Comma); ) {	0
2718	RegisterKind NextRegKind;	----
2719	unsigned NextReg, NextRegNum, NextRegWidth;	----
2720	Loc = getLoc();	0
2721		----
2722	if (!ParseAMDGPURegister(NextRegKind, NextReg,	0
2723	NextRegNum, NextRegWidth,	----
2724	Tokens)) {	----
2725	return AMDGPU::NoRegister;	0
2726	}	----
2727	if (NextRegWidth != 32) {	0
2728	Error(Loc, "expected a single 32-bit register");	0
2729	return AMDGPU::NoRegister;	0
2730	}	----
2731	if (NextRegKind != RegKind) {	0
2732	Error(Loc, "registers in a list must be of the same kind");	0
2733	return AMDGPU::NoRegister;	0
2734	}	----
2735	if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))	0
2736	return AMDGPU::NoRegister;	0
2737	}	----
2738		----
2739	if (!skipToken(AsmToken::RBrac,	0
2740	"expected a comma or a closing square bracket")) {	----
2741	return AMDGPU::NoRegister;	0
2742	}	----
2743		----
2744	if (isRegularReg(RegKind))	0
2745	Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);	0
2746		----
2747	return Reg;	0
2748	}	----
2749		----
2750	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	0
2751	unsigned &RegNum, unsigned &RegWidth,	----
2752	SmallVectorImpl &Tokens) {	----
2753	auto Loc = getLoc();	0
2754	Reg = AMDGPU::NoRegister;	0
2755		----
2756	if (isToken(AsmToken::Identifier)) {	0
2757	Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);	0
2758	if (Reg == AMDGPU::NoRegister)	0
2759	Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);	0
2760	} else {	----
2761	Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);	0
2762	}	----
2763		----
2764	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
2765	if (Reg == AMDGPU::NoRegister) {	0
2766	assert(Parser.hasPendingError());	0
2767	return false;	0
2768	}	----
2769		----
2770	if (!subtargetHasRegister(*TRI, Reg)) {	0
2771	if (Reg == AMDGPU::SGPR_NULL) {	0
2772	Error(Loc, "'null' operand is not supported on this GPU");	0
2773	} else {	----
2774	Error(Loc, "register not available on this GPU");	0
2775	}	----
2776	return false;	0
2777	}	----
2778		----
2779	return true;	0
2780	}	----
2781		----
2782	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	0
2783	unsigned &RegNum, unsigned &RegWidth,	----
2784	bool RestoreOnFailure /=false/) {	----
2785	Reg = AMDGPU::NoRegister;	0
2786		----
2787	SmallVector Tokens;	0
2788	if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {	0
2789	if (RestoreOnFailure) {	0
2790	while (!Tokens.empty()) {	0
2791	getLexer().UnLex(Tokens.pop_back_val());	0
2792	}	----
2793	}	----
2794	return true;	0
2795	}	----
2796	return false;	0
2797	}	0
2798		----
2799	std::optional	----
2800	AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {	0
2801	switch (RegKind) {	0
2802	case IS_VGPR:	0
2803	return StringRef(".amdgcn.next_free_vgpr");	0
2804	case IS_SGPR:	0
2805	return StringRef(".amdgcn.next_free_sgpr");	0
2806	default:	0
2807	return std::nullopt;	0
2808	}	----
2809	}	----
2810		----
2811	void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {	0
2812	auto SymbolName = getGprCountSymbolName(RegKind);	0
2813	assert(SymbolName && "initializing invalid register kind");	0
2814	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	0
2815	Sym->setVariableValue(MCConstantExpr::create(0, getContext()));	0
2816	}	0
2817		----
2818	bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,	0
2819	unsigned DwordRegIndex,	----
2820	unsigned RegWidth) {	----
2821	// Symbols are only defined for GCN targets	----
2822	if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)	0
2823	return true;	0
2824		----
2825	auto SymbolName = getGprCountSymbolName(RegKind);	0
2826	if (!SymbolName)	0
2827	return true;	0
2828	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	0
2829		----
2830	int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;	0
2831	int64_t OldCount;	----
2832		----
2833	if (!Sym->isVariable())	0
2834	return !Error(getLoc(),	0
2835	".amdgcn.next_free_{v,s}gpr symbols must be variable");	0
2836	if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))	0
2837	return !Error(	0
2838	getLoc(),	----
2839	".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");	0
2840		----
2841	if (OldCount <= NewMax)	0
2842	Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));	0
2843		----
2844	return true;	0
2845	}	----
2846		----
2847	std::unique_ptr	----
2848	AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {	0
2849	const auto &Tok = getToken();	0
2850	SMLoc StartLoc = Tok.getLoc();	0
2851	SMLoc EndLoc = Tok.getEndLoc();	0
2852	RegisterKind RegKind;	----
2853	unsigned Reg, RegNum, RegWidth;	----
2854		----
2855	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {	0
2856	return nullptr;	0
2857	}	----
2858	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0
2859	if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))	0
2860	return nullptr;	0
2861	} else	----
2862	KernelScope.usesRegister(RegKind, RegNum, RegWidth);	0
2863	return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);	0
2864	}	0
2865		----
2866	ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,	0
2867	bool HasSP3AbsModifier) {	----
2868	// TODO: add syntactic sugar for 1/(2*PI)	----
2869		----
2870	if (isRegister())	0
2871	return ParseStatus::NoMatch;	0
2872	assert(!isModifier());	0
2873		----
2874	const auto& Tok = getToken();	0
2875	const auto& NextTok = peekToken();	0
2876	bool IsReal = Tok.is(AsmToken::Real);	0
2877	SMLoc S = getLoc();	0
2878	bool Negate = false;	0
2879		----
2880	if (!IsReal && Tok.is(AsmToken::Minus) && NextTok.is(AsmToken::Real)) {	0
2881	lex();	0
2882	IsReal = true;	0
2883	Negate = true;	0
2884	}	----
2885		----
2886	if (IsReal) {	0
2887	// Floating-point expressions are not supported.	----
2888	// Can only allow floating-point literals with an	----
2889	// optional sign.	----
2890		----
2891	StringRef Num = getTokenStr();	0
2892	lex();	0
2893		----
2894	APFloat RealVal(APFloat::IEEEdouble());	0
2895	auto roundMode = APFloat::rmNearestTiesToEven;	0
2896	if (errorToBool(RealVal.convertFromString(Num, roundMode).takeError()))	0
2897	return ParseStatus::Failure;	0
2898	if (Negate)	0
2899	RealVal.changeSign();	0
2900		----
2901	Operands.push_back(	0
2902	AMDGPUOperand::CreateImm(this, RealVal.bitcastToAPInt().getZExtValue(), S,	0
2903	AMDGPUOperand::ImmTyNone, true));	----
2904		----
2905	return ParseStatus::Success;	0
2906		----
2907	} else {	0
2908	int64_t IntVal;	----
2909	const MCExpr *Expr;	----
2910	SMLoc S = getLoc();	0
2911		----
2912	if (HasSP3AbsModifier) {	0
2913	// This is a workaround for handling expressions	----
2914	// as arguments of SP3 'abs' modifier, for example:	----
2915	// \|1.0\|	----
2916	// \|-1\|	----
2917	// \|1+x\|	----
2918	// This syntax is not compatible with syntax of standard	----
2919	// MC expressions (due to the trailing '\|').	----
2920	SMLoc EndLoc;	0
2921	if (getParser().parsePrimaryExpr(Expr, EndLoc, nullptr))	0
2922	return ParseStatus::Failure;	0
2923	} else {	----
2924	if (Parser.parseExpression(Expr))	0
2925	return ParseStatus::Failure;	0
2926	}	----
2927		----
2928	if (Expr->evaluateAsAbsolute(IntVal)) {	0
2929	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	0
2930	} else {	----
2931	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	0
2932	}	----
2933		----
2934	return ParseStatus::Success;	0
2935	}	----
2936		----
2937	return ParseStatus::NoMatch;	----
2938	}	0
2939		----
2940	ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {	0
2941	if (!isRegister())	0
2942	return ParseStatus::NoMatch;	0
2943		----
2944	if (auto R = parseRegister()) {	0
2945	assert(R->isReg());	0
2946	Operands.push_back(std::move(R));	0
2947	return ParseStatus::Success;	0
2948	}	0
2949	return ParseStatus::Failure;	0
2950	}	----
2951		----
2952	ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,	0
2953	bool HasSP3AbsMod) {	----
2954	ParseStatus Res = parseReg(Operands);	0
2955	if (!Res.isNoMatch())	0
2956	return Res;	0
2957	if (isModifier())	0
2958	return ParseStatus::NoMatch;	0
2959	return parseImm(Operands, HasSP3AbsMod);	0
2960	}	----
2961		----
2962	bool	----
2963	AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0
2964	if (Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::LParen)) {	0
2965	const auto &str = Token.getString();	0
2966	return str == "abs" \|\| str == "neg" \|\| str == "sext";	0
2967	}	----
2968	return false;	0
2969	}	----
2970		----
2971	bool	----
2972	AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {	0
2973	return Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::Colon);	0
2974	}	----
2975		----
2976	bool	----
2977	AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0
2978	return isNamedOperandModifier(Token, NextToken) \|\| Token.is(AsmToken::Pipe);	0
2979	}	----
2980		----
2981	bool	----
2982	AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0
2983	return isRegister(Token, NextToken) \|\| isOperandModifier(Token, NextToken);	0
2984	}	----
2985		----
2986	// Check if this is an operand modifier or an opcode modifier	----
2987	// which may look like an expression but it is not. We should	----
2988	// avoid parsing these modifiers as expressions. Currently	----
2989	// recognized sequences are:	----
2990	// \|...\|	----
2991	// abs(...)	----
2992	// neg(...)	----
2993	// sext(...)	----
2994	// -reg	----
2995	// -\|...\|	----
2996	// -abs(...)	----
2997	// name:...	----
2998	//	----
2999	bool	----
3000	AMDGPUAsmParser::isModifier() {	0
3001		----
3002	AsmToken Tok = getToken();	0
3003	AsmToken NextToken[2];	0
3004	peekTokens(NextToken);	0
3005		----
3006	return isOperandModifier(Tok, NextToken[0]) \|\|	0
3007	(Tok.is(AsmToken::Minus) && isRegOrOperandModifier(NextToken[0], NextToken[1])) \|\|	0
3008	isOpcodeModifierWithVal(Tok, NextToken[0]);	0
3009	}	0
3010		----
3011	// Check if the current token is an SP3 'neg' modifier.	----
3012	// Currently this modifier is allowed in the following context:	----
3013	//	----
3014	// 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".	----
3015	// 2. Before an 'abs' modifier: -abs(...)	----
3016	// 3. Before an SP3 'abs' modifier: -\|...\|	----
3017	//	----
3018	// In all other cases "-" is handled as a part	----
3019	// of an expression that follows the sign.	----
3020	//	----
3021	// Note: When "-" is followed by an integer literal,	----
3022	// this is interpreted as integer negation rather	----
3023	// than a floating-point NEG modifier applied to N.	----
3024	// Beside being contr-intuitive, such use of floating-point	----
3025	// NEG modifier would have resulted in different meaning	----
3026	// of integer literals used with VOP1/2/C and VOP3,	----
3027	// for example:	----
3028	// v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF	----
3029	// v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001	----
3030	// Negative fp literals with preceding "-" are	----
3031	// handled likewise for uniformity	----
3032	//	----
3033	bool	----
3034	AMDGPUAsmParser::parseSP3NegModifier() {	0
3035		----
3036	AsmToken NextToken[2];	0
3037	peekTokens(NextToken);	0
3038		----
3039	if (isToken(AsmToken::Minus) &&	0
3040	(isRegister(NextToken[0], NextToken[1]) \|\|	0
3041	NextToken[0].is(AsmToken::Pipe) \|\|	0
3042	isId(NextToken[0], "abs"))) {	0
3043	lex();	0
3044	return true;	0
3045	}	----
3046		----
3047	return false;	0
3048	}	0
3049		----
3050	ParseStatus	----
3051	AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,	0
3052	bool AllowImm) {	----
3053	bool Neg, SP3Neg;	----
3054	bool Abs, SP3Abs;	----
3055	SMLoc Loc;	0
3056		----
3057	// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.	----
3058	if (isToken(AsmToken::Minus) && peekToken().is(AsmToken::Minus))	0
3059	return Error(getLoc(), "invalid syntax, expected 'neg' modifier");	0
3060		----
3061	SP3Neg = parseSP3NegModifier();	0
3062		----
3063	Loc = getLoc();	0
3064	Neg = trySkipId("neg");	0
3065	if (Neg && SP3Neg)	0
3066	return Error(Loc, "expected register or immediate");	0
3067	if (Neg && !skipToken(AsmToken::LParen, "expected left paren after neg"))	0
3068	return ParseStatus::Failure;	0
3069		----
3070	Abs = trySkipId("abs");	0
3071	if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))	0
3072	return ParseStatus::Failure;	0
3073		----
3074	Loc = getLoc();	0
3075	SP3Abs = trySkipToken(AsmToken::Pipe);	0
3076	if (Abs && SP3Abs)	0
3077	return Error(Loc, "expected register or immediate");	0
3078		----
3079	ParseStatus Res;	0
3080	if (AllowImm) {	0
3081	Res = parseRegOrImm(Operands, SP3Abs);	0
3082	} else {	----
3083	Res = parseReg(Operands);	0
3084	}	----
3085	if (!Res.isSuccess())	0
3086	return (SP3Neg \|\| Neg \|\| SP3Abs \|\| Abs) ? ParseStatus::Failure : Res;	0
3087		----
3088	if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))	0
3089	return ParseStatus::Failure;	0
3090	if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0
3091	return ParseStatus::Failure;	0
3092	if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0
3093	return ParseStatus::Failure;	0
3094		----
3095	AMDGPUOperand::Modifiers Mods;	0
3096	Mods.Abs = Abs \|\| SP3Abs;	0
3097	Mods.Neg = Neg \|\| SP3Neg;	0
3098		----
3099	if (Mods.hasFPModifiers()) {	0
3100	AMDGPUOperand &Op = static_cast(*Operands.back());	0
3101	if (Op.isExpr())	0
3102	return Error(Op.getStartLoc(), "expected an absolute expression");	0
3103	Op.setModifiers(Mods);	0
3104	}	----
3105	return ParseStatus::Success;	0
3106	}	----
3107		----
3108	ParseStatus	----
3109	AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,	0
3110	bool AllowImm) {	----
3111	bool Sext = trySkipId("sext");	0
3112	if (Sext && !skipToken(AsmToken::LParen, "expected left paren after sext"))	0
3113	return ParseStatus::Failure;	0
3114		----
3115	ParseStatus Res;	0
3116	if (AllowImm) {	0
3117	Res = parseRegOrImm(Operands);	0
3118	} else {	----
3119	Res = parseReg(Operands);	0
3120	}	----
3121	if (!Res.isSuccess())	0
3122	return Sext ? ParseStatus::Failure : Res;	0
3123		----
3124	if (Sext && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0
3125	return ParseStatus::Failure;	0
3126		----
3127	AMDGPUOperand::Modifiers Mods;	0
3128	Mods.Sext = Sext;	0
3129		----
3130	if (Mods.hasIntModifiers()) {	0
3131	AMDGPUOperand &Op = static_cast(*Operands.back());	0
3132	if (Op.isExpr())	0
3133	return Error(Op.getStartLoc(), "expected an absolute expression");	0
3134	Op.setModifiers(Mods);	0
3135	}	----
3136		----
3137	return ParseStatus::Success;	0
3138	}	----
3139		----
3140	ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {	0
3141	return parseRegOrImmWithFPInputMods(Operands, false);	0
3142	}	----
3143		----
3144	ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {	0
3145	return parseRegOrImmWithIntInputMods(Operands, false);	0
3146	}	----
3147		----
3148	ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {	0
3149	auto Loc = getLoc();	0
3150	if (trySkipId("off")) {	0
3151	Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,	0
3152	AMDGPUOperand::ImmTyOff, false));	----
3153	return ParseStatus::Success;	0
3154	}	----
3155		----
3156	if (!isRegister())	0
3157	return ParseStatus::NoMatch;	0
3158		----
3159	std::unique_ptr Reg = parseRegister();	0
3160	if (Reg) {	0
3161	Operands.push_back(std::move(Reg));	0
3162	return ParseStatus::Success;	0
3163	}	----
3164		----
3165	return ParseStatus::Failure;	0
3166	}	0
3167		----
3168	unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {	0
3169	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
3170		----
3171	if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) \|\|	0
3172	(getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) \|\|	0
3173	(isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) \|\|	0
3174	(isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )	0
3175	return Match_InvalidOperand;	0
3176		----
3177	if ((TSFlags & SIInstrFlags::VOP3) &&	0
3178	(TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&	0
3179	getForcedEncodingSize() != 64)	0
3180	return Match_PreferE32;	0
3181		----
3182	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	0
3183	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	0
3184	// v_mac_f32/16 allow only dst_sel == DWORD;	----
3185	auto OpNum =	----
3186	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);	0
3187	const auto &Op = Inst.getOperand(OpNum);	0
3188	if (!Op.isImm() \|\| Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {	0
3189	return Match_InvalidOperand;	0
3190	}	----
3191	}	----
3192		----
3193	return Match_Success;	0
3194	}	----
3195		----
3196	static ArrayRef getAllVariants() {	0
3197	static const unsigned Variants[] = {	----
3198	AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,	----
3199	AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9,	----
3200	AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP	----
3201	};	----
3202		----
3203	return ArrayRef(Variants);	0
3204	}	----
3205		----
3206	// What asm variants we should check	----
3207	ArrayRef AMDGPUAsmParser::getMatchedVariants() const {	0
3208	if (isForcedDPP() && isForcedVOP3()) {	0
3209	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3_DPP};	----
3210	return ArrayRef(Variants);	0
3211	}	----
3212	if (getForcedEncodingSize() == 32) {	0
3213	static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};	----
3214	return ArrayRef(Variants);	0
3215	}	----
3216		----
3217	if (isForcedVOP3()) {	0
3218	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};	----
3219	return ArrayRef(Variants);	0
3220	}	----
3221		----
3222	if (isForcedSDWA()) {	0
3223	static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,	----
3224	AMDGPUAsmVariants::SDWA9};	----
3225	return ArrayRef(Variants);	0
3226	}	----
3227		----
3228	if (isForcedDPP()) {	0
3229	static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};	----
3230	return ArrayRef(Variants);	0
3231	}	----
3232		----
3233	return getAllVariants();	0
3234	}	----
3235		----
3236	StringRef AMDGPUAsmParser::getMatchedVariantName() const {	0
3237	if (isForcedDPP() && isForcedVOP3())	0
3238	return "e64_dpp";	0
3239		----
3240	if (getForcedEncodingSize() == 32)	0
3241	return "e32";	0
3242		----
3243	if (isForcedVOP3())	0
3244	return "e64";	0
3245		----
3246	if (isForcedSDWA())	0
3247	return "sdwa";	0
3248		----
3249	if (isForcedDPP())	0
3250	return "dpp";	0
3251		----
3252	return "";	0
3253	}	----
3254		----
3255	unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {	0
3256	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
3257	for (MCPhysReg Reg : Desc.implicit_uses()) {	0
3258	switch (Reg) {	0
3259	case AMDGPU::FLAT_SCR:	0
3260	case AMDGPU::VCC:	----
3261	case AMDGPU::VCC_LO:	----
3262	case AMDGPU::VCC_HI:	----
3263	case AMDGPU::M0:	----
3264	return Reg;	0
3265	default:	0
3266	break;	0
3267	}	----
3268	}	----
3269	return AMDGPU::NoRegister;	0
3270	}	----
3271		----
3272	// NB: This code is correct only when used to check constant	----
3273	// bus limitations because GFX7 support no f16 inline constants.	----
3274	// Note that there are no cases when a GFX7 opcode violates	----
3275	// constant bus limitations due to the use of an f16 constant.	----
3276	bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,	0
3277	unsigned OpIdx) const {	----
3278	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
3279		----
3280	if (!AMDGPU::isSISrcOperand(Desc, OpIdx) \|\|	0
3281	AMDGPU::isKImmOperand(Desc, OpIdx)) {	0
3282	return false;	0
3283	}	----
3284		----
3285	const MCOperand &MO = Inst.getOperand(OpIdx);	0
3286		----
3287	int64_t Val = MO.getImm();	0
3288	auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);	0
3289		----
3290	switch (OpSize) { // expected operand size	0
3291	case 8:	0
3292	return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());	0
3293	case 4:	0
3294	return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());	0
3295	case 2: {	0
3296	const unsigned OperandType = Desc.operands()[OpIdx].OperandType;	0
3297	if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 \|\|	0
3298	OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 \|\|	0
3299	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16)	----
3300	return AMDGPU::isInlinableIntLiteral(Val);	0
3301		----
3302	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 \|\|	0
3303	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 \|\|	0
3304	OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16)	----
3305	return AMDGPU::isInlinableIntLiteralV216(Val);	0
3306		----
3307	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 \|\|	0
3308	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 \|\|	0
3309	OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)	----
3310	return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());	0
3311		----
3312	return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());	0
3313	}	----
3314	default:	0
3315	llvm_unreachable("invalid operand size");	0
3316	}	----
3317	}	----
3318		----
3319	unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {	0
3320	if (!isGFX10Plus())	0
3321	return 1;	0
3322		----
3323	switch (Opcode) {	0
3324	// 64-bit shift instructions can use only one scalar value input	----
3325	case AMDGPU::V_LSHLREV_B64_e64:	0
3326	case AMDGPU::V_LSHLREV_B64_gfx10:	----
3327	case AMDGPU::V_LSHLREV_B64_e64_gfx11:	----
3328	case AMDGPU::V_LSHRREV_B64_e64:	----
3329	case AMDGPU::V_LSHRREV_B64_gfx10:	----
3330	case AMDGPU::V_LSHRREV_B64_e64_gfx11:	----
3331	case AMDGPU::V_ASHRREV_I64_e64:	----
3332	case AMDGPU::V_ASHRREV_I64_gfx10:	----
3333	case AMDGPU::V_ASHRREV_I64_e64_gfx11:	----
3334	case AMDGPU::V_LSHL_B64_e64:	----
3335	case AMDGPU::V_LSHR_B64_e64:	----
3336	case AMDGPU::V_ASHR_I64_e64:	----
3337	return 1;	0
3338	default:	0
3339	return 2;	0
3340	}	----
3341	}	----
3342		----
3343	constexpr unsigned MAX_SRC_OPERANDS_NUM = 6;	----
3344	using OperandIndices = SmallVector;	----
3345		----
3346	// Get regular operand indices in the same order as specified	----
3347	// in the instruction (but append mandatory literals to the end).	----
3348	static OperandIndices getSrcOperandIndices(unsigned Opcode,	0
3349	bool AddMandatoryLiterals = false) {	----
3350		----
3351	int16_t ImmIdx =	0
3352	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;	0
3353		----
3354	if (isVOPD(Opcode)) {	0
3355	int16_t ImmDeferredIdx =	0
3356	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred)	0
3357	: -1;	----
3358		----
3359	return {getNamedOperandIdx(Opcode, OpName::src0X),	0
3360	getNamedOperandIdx(Opcode, OpName::vsrc1X),	0
3361	getNamedOperandIdx(Opcode, OpName::src0Y),	0
3362	getNamedOperandIdx(Opcode, OpName::vsrc1Y),	0
3363	ImmDeferredIdx,	----
3364	ImmIdx};	0
3365	}	----
3366		----
3367	return {getNamedOperandIdx(Opcode, OpName::src0),	0
3368	getNamedOperandIdx(Opcode, OpName::src1),	0
3369	getNamedOperandIdx(Opcode, OpName::src2), ImmIdx};	0
3370	}	----
3371		----
3372	bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {	0
3373	const MCOperand &MO = Inst.getOperand(OpIdx);	0
3374	if (MO.isImm()) {	0
3375	return !isInlineConstant(Inst, OpIdx);	0
3376	} else if (MO.isReg()) {	0
3377	auto Reg = MO.getReg();	0
3378	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3379	auto PReg = mc2PseudoReg(Reg);	0
3380	return isSGPR(PReg, TRI) && PReg != SGPR_NULL;	0
3381	} else {	----
3382	return true;	0
3383	}	----
3384	}	----
3385		----
3386	bool AMDGPUAsmParser::validateConstantBusLimitations(	0
3387	const MCInst &Inst, const OperandVector &Operands) {	----
3388	const unsigned Opcode = Inst.getOpcode();	0
3389	const MCInstrDesc &Desc = MII.get(Opcode);	0
3390	unsigned LastSGPR = AMDGPU::NoRegister;	0
3391	unsigned ConstantBusUseCount = 0;	0
3392	unsigned NumLiterals = 0;	0
3393	unsigned LiteralSize;	----
3394		----
3395	if (!(Desc.TSFlags &	0
3396	(SIInstrFlags::VOPC \| SIInstrFlags::VOP1 \| SIInstrFlags::VOP2 \|	----
3397	SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P \| SIInstrFlags::SDWA)) &&	0
3398	!isVOPD(Opcode))	0
3399	return true;	0
3400		----
3401	// Check special imm operands (used by madmk, etc)	----
3402	if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {	0
3403	++NumLiterals;	0
3404	LiteralSize = 4;	0
3405	}	----
3406		----
3407	SmallDenseSet SGPRsUsed;	0
3408	unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);	0
3409	if (SGPRUsed != AMDGPU::NoRegister) {	0
3410	SGPRsUsed.insert(SGPRUsed);	0
3411	++ConstantBusUseCount;	0
3412	}	----
3413		----
3414	OperandIndices OpIndices = getSrcOperandIndices(Opcode);	0
3415		----
3416	for (int OpIdx : OpIndices) {	0
3417	if (OpIdx == -1)	0
3418	continue;	0
3419		----
3420	const MCOperand &MO = Inst.getOperand(OpIdx);	0
3421	if (usesConstantBus(Inst, OpIdx)) {	0
3422	if (MO.isReg()) {	0
3423	LastSGPR = mc2PseudoReg(MO.getReg());	0
3424	// Pairs of registers with a partial intersections like these	----
3425	// s0, s[0:1]	----
3426	// flat_scratch_lo, flat_scratch	----
3427	// flat_scratch_lo, flat_scratch_hi	----
3428	// are theoretically valid but they are disabled anyway.	----
3429	// Note that this code mimics SIInstrInfo::verifyInstruction	----
3430	if (SGPRsUsed.insert(LastSGPR).second) {	0
3431	++ConstantBusUseCount;	0
3432	}	----
3433	} else { // Expression or a literal	----
3434		----
3435	if (Desc.operands()[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)	0
3436	continue; // special operand like VINTERP attr_chan	0
3437		----
3438	// An instruction may use only one literal.	----
3439	// This has been validated on the previous step.	----
3440	// See validateVOPLiteral.	----
3441	// This literal may be used as more than one operand.	----
3442	// If all these operands are of the same size,	----
3443	// this literal counts as one scalar value.	----
3444	// Otherwise it counts as 2 scalar values.	----
3445	// See "GFX10 Shader Programming", section 3.6.2.3.	----
3446		----
3447	unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);	0
3448	if (Size < 4)	0
3449	Size = 4;	0
3450		----
3451	if (NumLiterals == 0) {	0
3452	NumLiterals = 1;	0
3453	LiteralSize = Size;	0
3454	} else if (LiteralSize != Size) {	0
3455	NumLiterals = 2;	0
3456	}	----
3457	}	----
3458	}	----
3459	}	----
3460	ConstantBusUseCount += NumLiterals;	0
3461		----
3462	if (ConstantBusUseCount <= getConstantBusLimit(Opcode))	0
3463	return true;	0
3464		----
3465	SMLoc LitLoc = getLitLoc(Operands);	0
3466	SMLoc RegLoc = getRegLoc(LastSGPR, Operands);	0
3467	SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;	0
3468	Error(Loc, "invalid operand (violates constant bus restrictions)");	0
3469	return false;	0
3470	}	0
3471		----
3472	bool AMDGPUAsmParser::validateVOPDRegBankConstraints(	0
3473	const MCInst &Inst, const OperandVector &Operands) {	----
3474		----
3475	const unsigned Opcode = Inst.getOpcode();	0
3476	if (!isVOPD(Opcode))	0
3477	return true;	0
3478		----
3479	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3480		----
3481	auto getVRegIdx = [&](unsigned, unsigned OperandIdx) {	0
3482	const MCOperand &Opr = Inst.getOperand(OperandIdx);	0
3483	return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI))	0
3484	? Opr.getReg()	0
3485	: MCRegister::NoRegister;	0
3486	};	0
3487		----
3488	const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);	0
3489	auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(getVRegIdx);	0
3490	if (!InvalidCompOprIdx)	0
3491	return true;	0
3492		----
3493	auto CompOprIdx = *InvalidCompOprIdx;	0
3494	auto ParsedIdx =	----
3495	std::max(InstInfo[VOPD::X].getIndexInParsedOperands(CompOprIdx),	0
3496	InstInfo[VOPD::Y].getIndexInParsedOperands(CompOprIdx));	0
3497	assert(ParsedIdx > 0 && ParsedIdx < Operands.size());	0
3498		----
3499	auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();	0
3500	if (CompOprIdx == VOPD::Component::DST) {	0
3501	Error(Loc, "one dst register must be even and the other odd");	0
3502	} else {	----
3503	auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM;	0
3504	Error(Loc, Twine("src") + Twine(CompSrcIdx) +	0
3505	" operands must use different VGPR banks");	0
3506	}	----
3507		----
3508	return false;	0
3509	}	----
3510		----
3511	bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {	0
3512		----
3513	const unsigned Opc = Inst.getOpcode();	0
3514	const MCInstrDesc &Desc = MII.get(Opc);	0
3515		----
3516	if ((Desc.TSFlags & SIInstrFlags::IntClamp) != 0 && !hasIntClamp()) {	0
3517	int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);	0
3518	assert(ClampIdx != -1);	0
3519	return Inst.getOperand(ClampIdx).getImm() == 0;	0
3520	}	----
3521		----
3522	return true;	0
3523	}	----
3524		----
3525	bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,	0
3526	const SMLoc &IDLoc) {	----
3527		----
3528	const unsigned Opc = Inst.getOpcode();	0
3529	const MCInstrDesc &Desc = MII.get(Opc);	0
3530		----
3531	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3532	return true;	0
3533		----
3534	int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);	0
3535	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0
3536	int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);	0
3537		----
3538	assert(VDataIdx != -1);	0
3539		----
3540	if ((DMaskIdx == -1 \|\| TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray	0
3541	return true;	0
3542		----
3543	unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);	0
3544	unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;	0
3545	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0
3546	if (DMask == 0)	0
3547	DMask = 1;	0
3548		----
3549	bool IsPackedD16 = false;	0
3550	unsigned DataSize =	----
3551	(Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask);	0
3552	if (hasPackedD16()) {	0
3553	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	0
3554	IsPackedD16 = D16Idx >= 0;	0
3555	if (IsPackedD16 && Inst.getOperand(D16Idx).getImm())	0
3556	DataSize = (DataSize + 1) / 2;	0
3557	}	----
3558		----
3559	if ((VDataSize / 4) == DataSize + TFESize)	0
3560	return true;	0
3561		----
3562	StringRef Modifiers;	0
3563	if (isGFX90A())	0
3564	Modifiers = IsPackedD16 ? "dmask and d16" : "dmask";	0
3565	else	----
3566	Modifiers = IsPackedD16 ? "dmask, d16 and tfe" : "dmask and tfe";	0
3567		----
3568	Error(IDLoc, Twine("image data size does not match ") + Modifiers);	0
3569	return false;	0
3570	}	----
3571		----
3572	bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,	0
3573	const SMLoc &IDLoc) {	----
3574	const unsigned Opc = Inst.getOpcode();	0
3575	const MCInstrDesc &Desc = MII.get(Opc);	0
3576		----
3577	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 \|\| !isGFX10Plus())	0
3578	return true;	0
3579		----
3580	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	0
3581		----
3582	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	----
3583	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	0
3584	int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);	0
3585	int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);	0
3586	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	0
3587	int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);	0
3588		----
3589	assert(VAddr0Idx != -1);	0
3590	assert(SrsrcIdx != -1);	0
3591	assert(SrsrcIdx > VAddr0Idx);	0
3592		----
3593	bool IsA16 = Inst.getOperand(A16Idx).getImm();	0
3594	if (BaseOpcode->BVH) {	0
3595	if (IsA16 == BaseOpcode->A16)	0
3596	return true;	0
3597	Error(IDLoc, "image address size does not match a16");	0
3598	return false;	0
3599	}	----
3600		----
3601	unsigned Dim = Inst.getOperand(DimIdx).getImm();	0
3602	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	0
3603	bool IsNSA = SrsrcIdx - VAddr0Idx > 1;	0
3604	unsigned ActualAddrSize =	----
3605	IsNSA ? SrsrcIdx - VAddr0Idx	0
3606	: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;	0
3607		----
3608	unsigned ExpectedAddrSize =	----
3609	AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());	0
3610		----
3611	if (IsNSA) {	0
3612	if (hasPartialNSAEncoding() && ExpectedAddrSize > getNSAMaxSize()) {	0
3613	int VAddrLastIdx = SrsrcIdx - 1;	0
3614	unsigned VAddrLastSize =	----
3615	AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;	0
3616		----
3617	ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;	0
3618	}	----
3619	} else {	----
3620	if (ExpectedAddrSize > 12)	0
3621	ExpectedAddrSize = 16;	0
3622		----
3623	// Allow oversized 8 VGPR vaddr when only 5/6/7 VGPRs are required.	----
3624	// This provides backward compatibility for assembly created	----
3625	// before 160b/192b/224b types were directly supported.	----
3626	if (ActualAddrSize == 8 && (ExpectedAddrSize >= 5 && ExpectedAddrSize <= 7))	0
3627	return true;	0
3628	}	----
3629		----
3630	if (ActualAddrSize == ExpectedAddrSize)	0
3631	return true;	0
3632		----
3633	Error(IDLoc, "image address size does not match dim and a16");	0
3634	return false;	0
3635	}	----
3636		----
3637	bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {	0
3638		----
3639	const unsigned Opc = Inst.getOpcode();	0
3640	const MCInstrDesc &Desc = MII.get(Opc);	0
3641		----
3642	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3643	return true;	0
3644	if (!Desc.mayLoad() \|\| !Desc.mayStore())	0
3645	return true; // Not atomic	0
3646		----
3647	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0
3648	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0
3649		----
3650	// This is an incomplete check because image_atomic_cmpswap	----
3651	// may only use 0x3 and 0xf while other atomic operations	----
3652	// may use 0x1 and 0x3. However these limitations are	----
3653	// verified when we check that dmask matches dst size.	----
3654	return DMask == 0x1 \|\| DMask == 0x3 \|\| DMask == 0xf;	0
3655	}	----
3656		----
3657	bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {	0
3658		----
3659	const unsigned Opc = Inst.getOpcode();	0
3660	const MCInstrDesc &Desc = MII.get(Opc);	0
3661		----
3662	if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0)	0
3663	return true;	0
3664		----
3665	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0
3666	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0
3667		----
3668	// GATHER4 instructions use dmask in a different fashion compared to	----
3669	// other MIMG instructions. The only useful DMASK values are	----
3670	// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns	----
3671	// (red,red,red,red) etc.) The ISA document doesn't mention	----
3672	// this.	----
3673	return DMask == 0x1 \|\| DMask == 0x2 \|\| DMask == 0x4 \|\| DMask == 0x8;	0
3674	}	----
3675		----
3676	bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {	0
3677	const unsigned Opc = Inst.getOpcode();	0
3678	const MCInstrDesc &Desc = MII.get(Opc);	0
3679		----
3680	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3681	return true;	0
3682		----
3683	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	0
3684	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	----
3685	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	0
3686		----
3687	if (!BaseOpcode->MSAA)	0
3688	return true;	0
3689		----
3690	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	0
3691	assert(DimIdx != -1);	0
3692		----
3693	unsigned Dim = Inst.getOperand(DimIdx).getImm();	0
3694	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	0
3695		----
3696	return DimInfo->MSAA;	0
3697	}	----
3698		----
3699	static bool IsMovrelsSDWAOpcode(const unsigned Opcode)	0
3700	{	----
3701	switch (Opcode) {	0
3702	case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:	0
3703	case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:	----
3704	case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:	----
3705	return true;	0
3706	default:	0
3707	return false;	0
3708	}	----
3709	}	----
3710		----
3711	// movrels* opcodes should only allow VGPRS as src0.	----
3712	// This is specified in .td description for vop1/vop3,	----
3713	// but sdwa is handled differently. See isSDWAOperand.	----
3714	bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,	0
3715	const OperandVector &Operands) {	----
3716		----
3717	const unsigned Opc = Inst.getOpcode();	0
3718	const MCInstrDesc &Desc = MII.get(Opc);	0
3719		----
3720	if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 \|\| !IsMovrelsSDWAOpcode(Opc))	0
3721	return true;	0
3722		----
3723	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0
3724	assert(Src0Idx != -1);	0
3725		----
3726	SMLoc ErrLoc;	0
3727	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	0
3728	if (Src0.isReg()) {	0
3729	auto Reg = mc2PseudoReg(Src0.getReg());	0
3730	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3731	if (!isSGPR(Reg, TRI))	0
3732	return true;	0
3733	ErrLoc = getRegLoc(Reg, Operands);	0
3734	} else {	----
3735	ErrLoc = getConstLoc(Operands);	0
3736	}	----
3737		----
3738	Error(ErrLoc, "source operand must be a VGPR");	0
3739	return false;	0
3740	}	----
3741		----
3742	bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,	0
3743	const OperandVector &Operands) {	----
3744		----
3745	const unsigned Opc = Inst.getOpcode();	0
3746		----
3747	if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)	0
3748	return true;	0
3749		----
3750	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0
3751	assert(Src0Idx != -1);	0
3752		----
3753	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	0
3754	if (!Src0.isReg())	0
3755	return true;	0
3756		----
3757	auto Reg = mc2PseudoReg(Src0.getReg());	0
3758	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3759	if (!isGFX90A() && isSGPR(Reg, TRI)) {	0
3760	Error(getRegLoc(Reg, Operands),	0
3761	"source operand must be either a VGPR or an inline constant");	----
3762	return false;	0
3763	}	----
3764		----
3765	return true;	0
3766	}	----
3767		----
3768	bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,	0
3769	const OperandVector &Operands) {	----
3770	unsigned Opcode = Inst.getOpcode();	0
3771	const MCInstrDesc &Desc = MII.get(Opcode);	0
3772		----
3773	if (!(Desc.TSFlags & SIInstrFlags::IsMAI) \|\|	0
3774	!getFeatureBits()[FeatureMFMAInlineLiteralBug])	0
3775	return true;	0
3776		----
3777	const int Src2Idx = getNamedOperandIdx(Opcode, OpName::src2);	0
3778	if (Src2Idx == -1)	0
3779	return true;	0
3780		----
3781	if (Inst.getOperand(Src2Idx).isImm() && isInlineConstant(Inst, Src2Idx)) {	0
3782	Error(getConstLoc(Operands),	0
3783	"inline constants are not allowed for this operand");	----
3784	return false;	0
3785	}	----
3786		----
3787	return true;	0
3788	}	----
3789		----
3790	bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,	0
3791	const OperandVector &Operands) {	----
3792	const unsigned Opc = Inst.getOpcode();	0
3793	const MCInstrDesc &Desc = MII.get(Opc);	0
3794		----
3795	if ((Desc.TSFlags & SIInstrFlags::IsMAI) == 0)	0
3796	return true;	0
3797		----
3798	const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);	0
3799	if (Src2Idx == -1)	0
3800	return true;	0
3801		----
3802	const MCOperand &Src2 = Inst.getOperand(Src2Idx);	0
3803	if (!Src2.isReg())	0
3804	return true;	0
3805		----
3806	MCRegister Src2Reg = Src2.getReg();	0
3807	MCRegister DstReg = Inst.getOperand(0).getReg();	0
3808	if (Src2Reg == DstReg)	0
3809	return true;	0
3810		----
3811	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3812	if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)	0
3813	return true;	0
3814		----
3815	if (TRI->regsOverlap(Src2Reg, DstReg)) {	0
3816	Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),	0
3817	"source 2 operand must not partially overlap with dst");	----
3818	return false;	0
3819	}	----
3820		----
3821	return true;	0
3822	}	----
3823		----
3824	bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {	0
3825	switch (Inst.getOpcode()) {	0
3826	default:	0
3827	return true;	0
3828	case V_DIV_SCALE_F32_gfx6_gfx7:	0
3829	case V_DIV_SCALE_F32_vi:	----
3830	case V_DIV_SCALE_F32_gfx10:	----
3831	case V_DIV_SCALE_F64_gfx6_gfx7:	----
3832	case V_DIV_SCALE_F64_vi:	----
3833	case V_DIV_SCALE_F64_gfx10:	----
3834	break;	0
3835	}	----
3836		----
3837	// TODO: Check that src0 = src1 or src2.	----
3838		----
3839	for (auto Name : {AMDGPU::OpName::src0_modifiers,	0
3840	AMDGPU::OpName::src2_modifiers,	----
3841	AMDGPU::OpName::src2_modifiers}) {	0
3842	if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))	0
3843	.getImm() &	0
3844	SISrcMods::ABS) {	----
3845	return false;	0
3846	}	----
3847	}	----
3848		----
3849	return true;	0
3850	}	----
3851		----
3852	bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {	0
3853		----
3854	const unsigned Opc = Inst.getOpcode();	0
3855	const MCInstrDesc &Desc = MII.get(Opc);	0
3856		----
3857	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3858	return true;	0
3859		----
3860	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	0
3861	if (D16Idx >= 0 && Inst.getOperand(D16Idx).getImm()) {	0
3862	if (isCI() \|\| isSI())	0
3863	return false;	0
3864	}	----
3865		----
3866	return true;	0
3867	}	----
3868		----
3869	static bool IsRevOpcode(const unsigned Opcode)	0
3870	{	----
3871	switch (Opcode) {	0
3872	case AMDGPU::V_SUBREV_F32_e32:	0
3873	case AMDGPU::V_SUBREV_F32_e64:	----
3874	case AMDGPU::V_SUBREV_F32_e32_gfx10:	----
3875	case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:	----
3876	case AMDGPU::V_SUBREV_F32_e32_vi:	----
3877	case AMDGPU::V_SUBREV_F32_e64_gfx10:	----
3878	case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:	----
3879	case AMDGPU::V_SUBREV_F32_e64_vi:	----
3880		----
3881	case AMDGPU::V_SUBREV_CO_U32_e32:	----
3882	case AMDGPU::V_SUBREV_CO_U32_e64:	----
3883	case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:	----
3884	case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:	----
3885		----
3886	case AMDGPU::V_SUBBREV_U32_e32:	----
3887	case AMDGPU::V_SUBBREV_U32_e64:	----
3888	case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:	----
3889	case AMDGPU::V_SUBBREV_U32_e32_vi:	----
3890	case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:	----
3891	case AMDGPU::V_SUBBREV_U32_e64_vi:	----
3892		----
3893	case AMDGPU::V_SUBREV_U32_e32:	----
3894	case AMDGPU::V_SUBREV_U32_e64:	----
3895	case AMDGPU::V_SUBREV_U32_e32_gfx9:	----
3896	case AMDGPU::V_SUBREV_U32_e32_vi:	----
3897	case AMDGPU::V_SUBREV_U32_e64_gfx9:	----
3898	case AMDGPU::V_SUBREV_U32_e64_vi:	----
3899		----
3900	case AMDGPU::V_SUBREV_F16_e32:	----
3901	case AMDGPU::V_SUBREV_F16_e64:	----
3902	case AMDGPU::V_SUBREV_F16_e32_gfx10:	----
3903	case AMDGPU::V_SUBREV_F16_e32_vi:	----
3904	case AMDGPU::V_SUBREV_F16_e64_gfx10:	----
3905	case AMDGPU::V_SUBREV_F16_e64_vi:	----
3906		----
3907	case AMDGPU::V_SUBREV_U16_e32:	----
3908	case AMDGPU::V_SUBREV_U16_e64:	----
3909	case AMDGPU::V_SUBREV_U16_e32_vi:	----
3910	case AMDGPU::V_SUBREV_U16_e64_vi:	----
3911		----
3912	case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:	----
3913	case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:	----
3914	case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:	----
3915		----
3916	case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:	----
3917	case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:	----
3918		----
3919	case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:	----
3920	case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:	----
3921		----
3922	case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:	----
3923	case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:	----
3924		----
3925	case AMDGPU::V_LSHRREV_B32_e32:	----
3926	case AMDGPU::V_LSHRREV_B32_e64:	----
3927	case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:	----
3928	case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:	----
3929	case AMDGPU::V_LSHRREV_B32_e32_vi:	----
3930	case AMDGPU::V_LSHRREV_B32_e64_vi:	----
3931	case AMDGPU::V_LSHRREV_B32_e32_gfx10:	----
3932	case AMDGPU::V_LSHRREV_B32_e64_gfx10:	----
3933		----
3934	case AMDGPU::V_ASHRREV_I32_e32:	----
3935	case AMDGPU::V_ASHRREV_I32_e64:	----
3936	case AMDGPU::V_ASHRREV_I32_e32_gfx10:	----
3937	case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:	----
3938	case AMDGPU::V_ASHRREV_I32_e32_vi:	----
3939	case AMDGPU::V_ASHRREV_I32_e64_gfx10:	----
3940	case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:	----
3941	case AMDGPU::V_ASHRREV_I32_e64_vi:	----
3942		----
3943	case AMDGPU::V_LSHLREV_B32_e32:	----
3944	case AMDGPU::V_LSHLREV_B32_e64:	----
3945	case AMDGPU::V_LSHLREV_B32_e32_gfx10:	----
3946	case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:	----
3947	case AMDGPU::V_LSHLREV_B32_e32_vi:	----
3948	case AMDGPU::V_LSHLREV_B32_e64_gfx10:	----
3949	case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:	----
3950	case AMDGPU::V_LSHLREV_B32_e64_vi:	----
3951		----
3952	case AMDGPU::V_LSHLREV_B16_e32:	----
3953	case AMDGPU::V_LSHLREV_B16_e64:	----
3954	case AMDGPU::V_LSHLREV_B16_e32_vi:	----
3955	case AMDGPU::V_LSHLREV_B16_e64_vi:	----
3956	case AMDGPU::V_LSHLREV_B16_gfx10:	----
3957		----
3958	case AMDGPU::V_LSHRREV_B16_e32:	----
3959	case AMDGPU::V_LSHRREV_B16_e64:	----
3960	case AMDGPU::V_LSHRREV_B16_e32_vi:	----
3961	case AMDGPU::V_LSHRREV_B16_e64_vi:	----
3962	case AMDGPU::V_LSHRREV_B16_gfx10:	----
3963		----
3964	case AMDGPU::V_ASHRREV_I16_e32:	----
3965	case AMDGPU::V_ASHRREV_I16_e64:	----
3966	case AMDGPU::V_ASHRREV_I16_e32_vi:	----
3967	case AMDGPU::V_ASHRREV_I16_e64_vi:	----
3968	case AMDGPU::V_ASHRREV_I16_gfx10:	----
3969		----
3970	case AMDGPU::V_LSHLREV_B64_e64:	----
3971	case AMDGPU::V_LSHLREV_B64_gfx10:	----
3972	case AMDGPU::V_LSHLREV_B64_vi:	----
3973		----
3974	case AMDGPU::V_LSHRREV_B64_e64:	----
3975	case AMDGPU::V_LSHRREV_B64_gfx10:	----
3976	case AMDGPU::V_LSHRREV_B64_vi:	----
3977		----
3978	case AMDGPU::V_ASHRREV_I64_e64:	----
3979	case AMDGPU::V_ASHRREV_I64_gfx10:	----
3980	case AMDGPU::V_ASHRREV_I64_vi:	----
3981		----
3982	case AMDGPU::V_PK_LSHLREV_B16:	----
3983	case AMDGPU::V_PK_LSHLREV_B16_gfx10:	----
3984	case AMDGPU::V_PK_LSHLREV_B16_vi:	----
3985		----
3986	case AMDGPU::V_PK_LSHRREV_B16:	----
3987	case AMDGPU::V_PK_LSHRREV_B16_gfx10:	----
3988	case AMDGPU::V_PK_LSHRREV_B16_vi:	----
3989	case AMDGPU::V_PK_ASHRREV_I16:	----
3990	case AMDGPU::V_PK_ASHRREV_I16_gfx10:	----
3991	case AMDGPU::V_PK_ASHRREV_I16_vi:	----
3992	return true;	0
3993	default:	0
3994	return false;	0
3995	}	----
3996	}	----
3997		----
3998	std::optional	----
3999	AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {	0
4000		----
4001	using namespace SIInstrFlags;	----
4002	const unsigned Opcode = Inst.getOpcode();	0
4003	const MCInstrDesc &Desc = MII.get(Opcode);	0
4004		----
4005	// lds_direct register is defined so that it can be used	----
4006	// with 9-bit operands only. Ignore encodings which do not accept these.	----
4007	const auto Enc = VOP1 \| VOP2 \| VOP3 \| VOPC \| VOP3P \| SIInstrFlags::SDWA;	0
4008	if ((Desc.TSFlags & Enc) == 0)	0
4009	return std::nullopt;	0
4010		----
4011	for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {	0
4012	auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);	0
4013	if (SrcIdx == -1)	0
4014	break;	0
4015	const auto &Src = Inst.getOperand(SrcIdx);	0
4016	if (Src.isReg() && Src.getReg() == LDS_DIRECT) {	0
4017		----
4018	if (isGFX90A() \|\| isGFX11Plus())	0
4019	return StringRef("lds_direct is not supported on this GPU");	0
4020		----
4021	if (IsRevOpcode(Opcode) \|\| (Desc.TSFlags & SIInstrFlags::SDWA))	0
4022	return StringRef("lds_direct cannot be used with this instruction");	0
4023		----
4024	if (SrcName != OpName::src0)	0
4025	return StringRef("lds_direct may be used as src0 only");	0
4026	}	----
4027	}	----
4028		----
4029	return std::nullopt;	0
4030	}	----
4031		----
4032	SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {	0
4033	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
4034	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
4035	if (Op.isFlatOffset())	0
4036	return Op.getStartLoc();	0
4037	}	----
4038	return getLoc();	0
4039	}	----
4040		----
4041	bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,	0
4042	const OperandVector &Operands) {	----
4043	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4044	if ((TSFlags & SIInstrFlags::FLAT) == 0)	0
4045	return true;	0
4046		----
4047	auto Opcode = Inst.getOpcode();	0
4048	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	0
4049	assert(OpNum != -1);	0
4050		----
4051	const auto &Op = Inst.getOperand(OpNum);	0
4052	if (!hasFlatOffsets() && Op.getImm() != 0) {	0
4053	Error(getFlatOffsetLoc(Operands),	0
4054	"flat offset modifier is not supported on this GPU");	----
4055	return false;	0
4056	}	----
4057		----
4058	// For FLAT segment the offset must be positive;	----
4059	// MSB is ignored and forced to zero.	----
4060	unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI());	0
4061	bool AllowNegative =	0
4062	TSFlags & (SIInstrFlags::FlatGlobal \| SIInstrFlags::FlatScratch);	0
4063	if (!isIntN(OffsetSize, Op.getImm()) \|\| (!AllowNegative && Op.getImm() < 0)) {	0
4064	Error(getFlatOffsetLoc(Operands),	0
4065	Twine("expected a ") +	0
4066	(AllowNegative ? Twine(OffsetSize) + "-bit signed offset"	0
4067	: Twine(OffsetSize - 1) + "-bit unsigned offset"));	0
4068	return false;	0
4069	}	----
4070		----
4071	return true;	0
4072	}	----
4073		----
4074	SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {	0
4075	// Start with second operand because SMEM Offset cannot be dst or src0.	----
4076	for (unsigned i = 2, e = Operands.size(); i != e; ++i) {	0
4077	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
4078	if (Op.isSMEMOffset() \|\| Op.isSMEMOffsetMod())	0
4079	return Op.getStartLoc();	0
4080	}	----
4081	return getLoc();	0
4082	}	----
4083		----
4084	bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,	0
4085	const OperandVector &Operands) {	----
4086	if (isCI() \|\| isSI())	0
4087	return true;	0
4088		----
4089	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4090	if ((TSFlags & SIInstrFlags::SMRD) == 0)	0
4091	return true;	0
4092		----
4093	auto Opcode = Inst.getOpcode();	0
4094	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	0
4095	if (OpNum == -1)	0
4096	return true;	0
4097		----
4098	const auto &Op = Inst.getOperand(OpNum);	0
4099	if (!Op.isImm())	0
4100	return true;	0
4101		----
4102	uint64_t Offset = Op.getImm();	0
4103	bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode);	0
4104	if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) \|\|	0
4105	AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer))	0
4106	return true;	0
4107		----
4108	Error(getSMEMOffsetLoc(Operands),	0
4109	(isVI() \|\| IsBuffer) ? "expected a 20-bit unsigned offset" :	0
4110	"expected a 21-bit signed offset");	----
4111		----
4112	return false;	0
4113	}	----
4114		----
4115	bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {	0
4116	unsigned Opcode = Inst.getOpcode();	0
4117	const MCInstrDesc &Desc = MII.get(Opcode);	0
4118	if (!(Desc.TSFlags & (SIInstrFlags::SOP2 \| SIInstrFlags::SOPC)))	0
4119	return true;	0
4120		----
4121	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);	0
4122	const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);	0
4123		----
4124	const int OpIndices[] = { Src0Idx, Src1Idx };	0
4125		----
4126	unsigned NumExprs = 0;	0
4127	unsigned NumLiterals = 0;	0
4128	uint32_t LiteralValue;	----
4129		----
4130	for (int OpIdx : OpIndices) {	0
4131	if (OpIdx == -1) break;	0
4132		----
4133	const MCOperand &MO = Inst.getOperand(OpIdx);	0
4134	// Exclude special imm operands (like that used by s_set_gpr_idx_on)	----
4135	if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {	0
4136	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	0
4137	uint32_t Value = static_cast(MO.getImm());	0
4138	if (NumLiterals == 0 \|\| LiteralValue != Value) {	0
4139	LiteralValue = Value;	0
4140	++NumLiterals;	0
4141	}	----
4142	} else if (MO.isExpr()) {	0
4143	++NumExprs;	0
4144	}	----
4145	}	----
4146	}	----
4147		----
4148	return NumLiterals + NumExprs <= 1;	0
4149	}	----
4150		----
4151	bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {	0
4152	const unsigned Opc = Inst.getOpcode();	0
4153	if (isPermlane16(Opc)) {	0
4154	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
4155	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
4156		----
4157	if (OpSel & ~3)	0
4158	return false;	0
4159	}	----
4160		----
4161	uint64_t TSFlags = MII.get(Opc).TSFlags;	0
4162		----
4163	if (isGFX940() && (TSFlags & SIInstrFlags::IsDOT)) {	0
4164	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
4165	if (OpSelIdx != -1) {	0
4166	if (Inst.getOperand(OpSelIdx).getImm() != 0)	0
4167	return false;	0
4168	}	----
4169	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	0
4170	if (OpSelHiIdx != -1) {	0
4171	if (Inst.getOperand(OpSelHiIdx).getImm() != -1)	0
4172	return false;	0
4173	}	----
4174	}	----
4175		----
4176	// op_sel[0:1] must be 0 for v_dot2_bf16_bf16 and v_dot2_f16_f16 (VOP3 Dot).	----
4177	if (isGFX11Plus() && (TSFlags & SIInstrFlags::IsDOT) &&	0
4178	(TSFlags & SIInstrFlags::VOP3) && !(TSFlags & SIInstrFlags::VOP3P)) {	0
4179	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
4180	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
4181	if (OpSel & 3)	0
4182	return false;	0
4183	}	----
4184		----
4185	return true;	0
4186	}	----
4187		----
4188	bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,	0
4189	const OperandVector &Operands) {	----
4190	const unsigned Opc = Inst.getOpcode();	0
4191	int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl);	0
4192	if (DppCtrlIdx < 0)	0
4193	return true;	0
4194	unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();	0
4195		----
4196	if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {	0
4197	// DPP64 is supported for row_newbcast only.	----
4198	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0
4199	if (Src0Idx >= 0 &&	0
4200	getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) {	0
4201	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);	0
4202	Error(S, "64 bit dpp only supports row_newbcast");	0
4203	return false;	0
4204	}	----
4205	}	----
4206		----
4207	return true;	0
4208	}	----
4209		----
4210	// Check if VCC register matches wavefront size	----
4211	bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {	0
4212	auto FB = getFeatureBits();	0
4213	return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) \|\|	0
4214	(FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);	0
4215	}	----
4216		----
4217	// One unique literal can be used. VOP3 literal is only allowed in GFX10+	----
4218	bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,	0
4219	const OperandVector &Operands) {	----
4220	unsigned Opcode = Inst.getOpcode();	0
4221	const MCInstrDesc &Desc = MII.get(Opcode);	0
4222	bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1;	0
4223	if (!(Desc.TSFlags & (SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P)) &&	0
4224	!HasMandatoryLiteral && !isVOPD(Opcode))	0
4225	return true;	0
4226		----
4227	OperandIndices OpIndices = getSrcOperandIndices(Opcode, HasMandatoryLiteral);	0
4228		----
4229	unsigned NumExprs = 0;	0
4230	unsigned NumLiterals = 0;	0
4231	uint32_t LiteralValue;	----
4232		----
4233	for (int OpIdx : OpIndices) {	0
4234	if (OpIdx == -1)	0
4235	continue;	0
4236		----
4237	const MCOperand &MO = Inst.getOperand(OpIdx);	0
4238	if (!MO.isImm() && !MO.isExpr())	0
4239	continue;	0
4240	if (!isSISrcOperand(Desc, OpIdx))	0
4241	continue;	0
4242		----
4243	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	0
4244	uint32_t Value = static_cast(MO.getImm());	0
4245	if (NumLiterals == 0 \|\| LiteralValue != Value) {	0
4246	LiteralValue = Value;	0
4247	++NumLiterals;	0
4248	}	----
4249	} else if (MO.isExpr()) {	0
4250	++NumExprs;	0
4251	}	----
4252	}	----
4253	NumLiterals += NumExprs;	0
4254		----
4255	if (!NumLiterals)	0
4256	return true;	0
4257		----
4258	if (!HasMandatoryLiteral && !getFeatureBits()[FeatureVOP3Literal]) {	0
4259	Error(getLitLoc(Operands), "literal operands are not supported");	0
4260	return false;	0
4261	}	----
4262		----
4263	if (NumLiterals > 1) {	0
4264	Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");	0
4265	return false;	0
4266	}	----
4267		----
4268	return true;	0
4269	}	0
4270		----
4271	// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.	----
4272	static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,	0
4273	const MCRegisterInfo *MRI) {	----
4274	int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);	0
4275	if (OpIdx < 0)	0
4276	return -1;	0
4277		----
4278	const MCOperand &Op = Inst.getOperand(OpIdx);	0
4279	if (!Op.isReg())	0
4280	return -1;	0
4281		----
4282	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	0
4283	auto Reg = Sub ? Sub : Op.getReg();	0
4284	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	0
4285	return AGPR32.contains(Reg) ? 1 : 0;	0
4286	}	----
4287		----
4288	bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {	0
4289	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4290	if ((TSFlags & (SIInstrFlags::FLAT \| SIInstrFlags::MUBUF \|	0
4291	SIInstrFlags::MTBUF \| SIInstrFlags::MIMG \|	----
4292	SIInstrFlags::DS)) == 0)	----
4293	return true;	0
4294		----
4295	uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0	0
4296	: AMDGPU::OpName::vdata;	----
4297		----
4298	const MCRegisterInfo *MRI = getMRI();	0
4299	int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);	0
4300	int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);	0
4301		----
4302	if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {	0
4303	int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);	0
4304	if (Data2Areg >= 0 && Data2Areg != DataAreg)	0
4305	return false;	0
4306	}	----
4307		----
4308	auto FB = getFeatureBits();	0
4309	if (FB[AMDGPU::FeatureGFX90AInsts]) {	0
4310	if (DataAreg < 0 \|\| DstAreg < 0)	0
4311	return true;	0
4312	return DstAreg == DataAreg;	0
4313	}	----
4314		----
4315	return DstAreg < 1 && DataAreg < 1;	0
4316	}	----
4317		----
4318	bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {	0
4319	auto FB = getFeatureBits();	0
4320	if (!FB[AMDGPU::FeatureGFX90AInsts])	0
4321	return true;	0
4322		----
4323	const MCRegisterInfo *MRI = getMRI();	0
4324	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	0
4325	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	0
4326	for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {	0
4327	const MCOperand &Op = Inst.getOperand(I);	0
4328	if (!Op.isReg())	0
4329	continue;	0
4330		----
4331	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	0
4332	if (!Sub)	0
4333	continue;	0
4334		----
4335	if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))	0
4336	return false;	0
4337	if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))	0
4338	return false;	0
4339	}	----
4340		----
4341	return true;	0
4342	}	----
4343		----
4344	SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {	0
4345	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
4346	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
4347	if (Op.isBLGP())	0
4348	return Op.getStartLoc();	0
4349	}	----
4350	return SMLoc();	0
4351	}	----
4352		----
4353	bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,	0
4354	const OperandVector &Operands) {	----
4355	unsigned Opc = Inst.getOpcode();	0
4356	int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp);	0
4357	if (BlgpIdx == -1)	0
4358	return true;	0
4359	SMLoc BLGPLoc = getBLGPLoc(Operands);	0
4360	if (!BLGPLoc.isValid())	0
4361	return true;	0
4362	bool IsNeg = StringRef(BLGPLoc.getPointer()).startswith("neg:");	0
4363	auto FB = getFeatureBits();	0
4364	bool UsesNeg = false;	0
4365	if (FB[AMDGPU::FeatureGFX940Insts]) {	0
4366	switch (Opc) {	0
4367	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:	0
4368	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:	----
4369	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:	----
4370	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:	----
4371	UsesNeg = true;	0
4372	}	----
4373	}	----
4374		----
4375	if (IsNeg == UsesNeg)	0
4376	return true;	0
4377		----
4378	Error(BLGPLoc,	0
4379	UsesNeg ? "invalid modifier: blgp is not supported"	----
4380	: "invalid modifier: neg is not supported");	----
4381		----
4382	return false;	0
4383	}	----
4384		----
4385	bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,	0
4386	const OperandVector &Operands) {	----
4387	if (!isGFX11Plus())	0
4388	return true;	0
4389		----
4390	unsigned Opc = Inst.getOpcode();	0
4391	if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 &&	0
4392	Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 &&	0
4393	Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 &&	0
4394	Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11)	----
4395	return true;	0
4396		----
4397	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);	0
4398	assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());	0
4399	auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());	0
4400	if (Reg == AMDGPU::SGPR_NULL)	0
4401	return true;	0
4402		----
4403	SMLoc RegLoc = getRegLoc(Reg, Operands);	0
4404	Error(RegLoc, "src0 must be null");	0
4405	return false;	0
4406	}	----
4407		----
4408	// gfx90a has an undocumented limitation:	----
4409	// DS_GWS opcodes must use even aligned registers.	----
4410	bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,	0
4411	const OperandVector &Operands) {	----
4412	if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])	0
4413	return true;	0
4414		----
4415	int Opc = Inst.getOpcode();	0
4416	if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&	0
4417	Opc != AMDGPU::DS_GWS_SEMA_BR_vi)	----
4418	return true;	0
4419		----
4420	const MCRegisterInfo *MRI = getMRI();	0
4421	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	0
4422	int Data0Pos =	----
4423	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);	0
4424	assert(Data0Pos != -1);	0
4425	auto Reg = Inst.getOperand(Data0Pos).getReg();	0
4426	auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);	0
4427	if (RegIdx & 1) {	0
4428	SMLoc RegLoc = getRegLoc(Reg, Operands);	0
4429	Error(RegLoc, "vgpr must be even aligned");	0
4430	return false;	0
4431	}	----
4432		----
4433	return true;	0
4434	}	----
4435		----
4436	bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,	0
4437	const OperandVector &Operands,	----
4438	const SMLoc &IDLoc) {	----
4439	int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),	0
4440	AMDGPU::OpName::cpol);	0
4441	if (CPolPos == -1)	0
4442	return true;	0
4443		----
4444	unsigned CPol = Inst.getOperand(CPolPos).getImm();	0
4445		----
4446	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4447	if (TSFlags & SIInstrFlags::SMRD) {	0
4448	if (CPol && (isSI() \|\| isCI())) {	0
4449	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0
4450	Error(S, "cache policy is not supported for SMRD instructions");	0
4451	return false;	0
4452	}	----
4453	if (CPol & ~(AMDGPU::CPol::GLC \| AMDGPU::CPol::DLC)) {	0
4454	Error(IDLoc, "invalid cache policy for SMEM instruction");	0
4455	return false;	0
4456	}	----
4457	}	----
4458		----
4459	if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {	0
4460	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0
4461	StringRef CStr(S.getPointer());	0
4462	S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);	0
4463	Error(S, "scc is not supported on this GPU");	0
4464	return false;	0
4465	}	----
4466		----
4467	if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet \| SIInstrFlags::IsAtomicRet)))	0
4468	return true;	0
4469		----
4470	if (TSFlags & SIInstrFlags::IsAtomicRet) {	0
4471	if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {	0
4472	Error(IDLoc, isGFX940() ? "instruction must use sc0"	0
4473	: "instruction must use glc");	----
4474	return false;	0
4475	}	----
4476	} else {	----
4477	if (CPol & CPol::GLC) {	0
4478	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0
4479	StringRef CStr(S.getPointer());	0
4480	S = SMLoc::getFromPointer(	0
4481	&CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]);	0
4482	Error(S, isGFX940() ? "instruction must not use sc0"	0
4483	: "instruction must not use glc");	----
4484	return false;	0
4485	}	----
4486	}	----
4487		----
4488	return true;	0
4489	}	----
4490		----
4491	bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {	0
4492	if (!isGFX11Plus())	0
4493	return true;	0
4494	for (auto &Operand : Operands) {	0
4495	if (!Operand->isReg())	0
4496	continue;	0
4497	unsigned Reg = Operand->getReg();	0
4498	if (Reg == SRC_EXECZ \|\| Reg == SRC_VCCZ) {	0
4499	Error(getRegLoc(Reg, Operands),	0
4500	"execz and vccz are not supported on this GPU");	----
4501	return false;	0
4502	}	----
4503	}	----
4504	return true;	0
4505	}	----
4506		----
4507	bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,	0
4508	const OperandVector &Operands) {	----
4509	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
4510	if (Desc.mayStore() &&	0
4511	(Desc.TSFlags & (SIInstrFlags::MUBUF \| SIInstrFlags::MTBUF))) {	0
4512	SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);	0
4513	if (Loc != getInstLoc(Operands)) {	0
4514	Error(Loc, "TFE modifier has no meaning for store instructions");	0
4515	return false;	0
4516	}	----
4517	}	----
4518		----
4519	return true;	0
4520	}	----
4521		----
4522	bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,	0
4523	const SMLoc &IDLoc,	----
4524	const OperandVector &Operands) {	----
4525	if (auto ErrMsg = validateLdsDirect(Inst)) {	0
4526	Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);	0
4527	return false;	0
4528	}	----
4529	if (!validateSOPLiteral(Inst)) {	0
4530	Error(getLitLoc(Operands),	0
4531	"only one unique literal operand is allowed");	----
4532	return false;	0
4533	}	----
4534	if (!validateVOPLiteral(Inst, Operands)) {	0
4535	return false;	0
4536	}	----
4537	if (!validateConstantBusLimitations(Inst, Operands)) {	0
4538	return false;	0
4539	}	----
4540	if (!validateVOPDRegBankConstraints(Inst, Operands)) {	0
4541	return false;	0
4542	}	----
4543	if (!validateIntClampSupported(Inst)) {	0
4544	Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),	0
4545	"integer clamping is not supported on this GPU");	----
4546	return false;	0
4547	}	----
4548	if (!validateOpSel(Inst)) {	0
4549	Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),	0
4550	"invalid op_sel operand");	----
4551	return false;	0
4552	}	----
4553	if (!validateDPP(Inst, Operands)) {	0
4554	return false;	0
4555	}	----
4556	// For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.	----
4557	if (!validateMIMGD16(Inst)) {	0
4558	Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),	0
4559	"d16 modifier is not supported on this GPU");	----
4560	return false;	0
4561	}	----
4562	if (!validateMIMGMSAA(Inst)) {	0
4563	Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),	0
4564	"invalid dim; must be MSAA type");	----
4565	return false;	0
4566	}	----
4567	if (!validateMIMGDataSize(Inst, IDLoc)) {	0
4568	return false;	0
4569	}	----
4570	if (!validateMIMGAddrSize(Inst, IDLoc))	0
4571	return false;	0
4572	if (!validateMIMGAtomicDMask(Inst)) {	0
4573	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	0
4574	"invalid atomic image dmask");	----
4575	return false;	0
4576	}	----
4577	if (!validateMIMGGatherDMask(Inst)) {	0
4578	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	0
4579	"invalid image_gather dmask: only one bit must be set");	----
4580	return false;	0
4581	}	----
4582	if (!validateMovrels(Inst, Operands)) {	0
4583	return false;	0
4584	}	----
4585	if (!validateFlatOffset(Inst, Operands)) {	0
4586	return false;	0
4587	}	----
4588	if (!validateSMEMOffset(Inst, Operands)) {	0
4589	return false;	0
4590	}	----
4591	if (!validateMAIAccWrite(Inst, Operands)) {	0
4592	return false;	0
4593	}	----
4594	if (!validateMAISrc2(Inst, Operands)) {	0
4595	return false;	0
4596	}	----
4597	if (!validateMFMA(Inst, Operands)) {	0
4598	return false;	0
4599	}	----
4600	if (!validateCoherencyBits(Inst, Operands, IDLoc)) {	0
4601	return false;	0
4602	}	----
4603		----
4604	if (!validateAGPRLdSt(Inst)) {	0
4605	Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]	0
4606	? "invalid register class: data and dst should be all VGPR or AGPR"	----
4607	: "invalid register class: agpr loads and stores not supported on this GPU"	----
4608	);	----
4609	return false;	0
4610	}	----
4611	if (!validateVGPRAlign(Inst)) {	0
4612	Error(IDLoc,	0
4613	"invalid register class: vgpr tuples must be 64 bit aligned");	----
4614	return false;	0
4615	}	----
4616	if (!validateGWS(Inst, Operands)) {	0
4617	return false;	0
4618	}	----
4619		----
4620	if (!validateBLGP(Inst, Operands)) {	0
4621	return false;	0
4622	}	----
4623		----
4624	if (!validateDivScale(Inst)) {	0
4625	Error(IDLoc, "ABS not allowed in VOP3B instructions");	0
4626	return false;	0
4627	}	----
4628	if (!validateWaitCnt(Inst, Operands)) {	0
4629	return false;	0
4630	}	----
4631	if (!validateExeczVcczOperands(Operands)) {	0
4632	return false;	0
4633	}	----
4634	if (!validateTFE(Inst, Operands)) {	0
4635	return false;	0
4636	}	----
4637		----
4638	return true;	0
4639	}	----
4640		----
4641	static std::string AMDGPUMnemonicSpellCheck(StringRef S,	----
4642	const FeatureBitset &FBS,	----
4643	unsigned VariantID = 0);	----
4644		----
4645	static bool AMDGPUCheckMnemonic(StringRef Mnemonic,	----
4646	const FeatureBitset &AvailableFeatures,	----
4647	unsigned VariantID);	----
4648		----
4649	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	0
4650	const FeatureBitset &FBS) {	----
4651	return isSupportedMnemo(Mnemo, FBS, getAllVariants());	0
4652	}	----
4653		----
4654	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	0
4655	const FeatureBitset &FBS,	----
4656	ArrayRef Variants) {	----
4657	for (auto Variant : Variants) {	0
4658	if (AMDGPUCheckMnemonic(Mnemo, FBS, Variant))	0
4659	return true;	0
4660	}	----
4661		----
4662	return false;	0
4663	}	----
4664		----
4665	bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,	0
4666	const SMLoc &IDLoc) {	----
4667	FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());	0
4668		----
4669	// Check if requested instruction variant is supported.	----
4670	if (isSupportedMnemo(Mnemo, FBS, getMatchedVariants()))	0
4671	return false;	0
4672		----
4673	// This instruction is not supported.	----
4674	// Clear any other pending errors because they are no longer relevant.	----
4675	getParser().clearPendingErrors();	0
4676		----
4677	// Requested instruction variant is not supported.	----
4678	// Check if any other variants are supported.	----
4679	StringRef VariantName = getMatchedVariantName();	0
4680	if (!VariantName.empty() && isSupportedMnemo(Mnemo, FBS)) {	0
4681	return Error(IDLoc,	0
4682	Twine(VariantName,	0
4683	" variant of this instruction is not supported"));	0
4684	}	----
4685		----
4686	// Check if this instruction may be used with a different wavesize.	----
4687	if (isGFX10Plus() && getFeatureBits()[AMDGPU::FeatureWavefrontSize64] &&	0
4688	!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) {	0
4689		----
4690	FeatureBitset FeaturesWS32 = getFeatureBits();	0
4691	FeaturesWS32.flip(AMDGPU::FeatureWavefrontSize64)	0
4692	.flip(AMDGPU::FeatureWavefrontSize32);	0
4693	FeatureBitset AvailableFeaturesWS32 =	----
4694	ComputeAvailableFeatures(FeaturesWS32);	0
4695		----
4696	if (isSupportedMnemo(Mnemo, AvailableFeaturesWS32, getMatchedVariants()))	0
4697	return Error(IDLoc, "instruction requires wavesize=32");	0
4698	}	----
4699		----
4700	// Finally check if this instruction is supported on any other GPU.	----
4701	if (isSupportedMnemo(Mnemo, FeatureBitset().set())) {	0
4702	return Error(IDLoc, "instruction not supported on this GPU");	0
4703	}	----
4704		----
4705	// Instruction not supported on any GPU. Probably a typo.	----
4706	std::string Suggestion = AMDGPUMnemonicSpellCheck(Mnemo, FBS);	0
4707	return Error(IDLoc, "invalid instruction" + Suggestion);	0
4708	}	0
4709		----
4710	static bool isInvalidVOPDY(const OperandVector &Operands,	0
4711	uint64_t InvalidOprIdx) {	----
4712	assert(InvalidOprIdx < Operands.size());	0
4713	const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);	0
4714	if (Op.isToken() && InvalidOprIdx > 1) {	0
4715	const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);	0
4716	return PrevOp.isToken() && PrevOp.getToken() == "::";	0
4717	}	----
4718	return false;	0
4719	}	----
4720		----
4721	bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	0
4722	OperandVector &Operands,	----
4723	MCStreamer &Out,	----
4724	uint64_t &ErrorInfo,	----
4725	bool MatchingInlineAsm) {	----
4726	MCInst Inst;	0
4727	unsigned Result = Match_Success;	0
4728	for (auto Variant : getMatchedVariants()) {	0
4729	uint64_t EI;	----
4730	auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,	0
4731	Variant);	----
4732	// We order match statuses from least to most specific. We use most specific	----
4733	// status as resulting	----
4734	// Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32	----
4735	if ((R == Match_Success) \|\|	0
4736	(R == Match_PreferE32) \|\|	0
4737	(R == Match_MissingFeature && Result != Match_PreferE32) \|\|	0
4738	(R == Match_InvalidOperand && Result != Match_MissingFeature	0
4739	&& Result != Match_PreferE32) \|\|	0
4740	(R == Match_MnemonicFail && Result != Match_InvalidOperand	0
4741	&& Result != Match_MissingFeature	0
4742	&& Result != Match_PreferE32)) {	0
4743	Result = R;	0
4744	ErrorInfo = EI;	0
4745	}	----
4746	if (R == Match_Success)	0
4747	break;	0
4748	}	----
4749		----
4750	if (Result == Match_Success) {	0
4751	if (!validateInstruction(Inst, IDLoc, Operands)) {	0
4752	return true;	0
4753	}	----
4754	Inst.setLoc(IDLoc);	0
4755	Out.emitInstruction(Inst, getSTI());	0
4756	return false;	0
4757	}	----
4758		----
4759	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	0
4760	if (checkUnsupportedInstruction(Mnemo, IDLoc)) {	0
4761	return true;	0
4762	}	----
4763		----
4764	switch (Result) {	0
4765	default: break;	0
4766	case Match_MissingFeature:	0
4767	// It has been verified that the specified instruction	----
4768	// mnemonic is valid. A match was found but it requires	----
4769	// features which are not supported on this GPU.	----
4770	return Error(IDLoc, "operands are not valid for this GPU or mode");	0
4771		----
4772	case Match_InvalidOperand: {	0
4773	SMLoc ErrorLoc = IDLoc;	0
4774	if (ErrorInfo != ~0ULL) {	0
4775	if (ErrorInfo >= Operands.size()) {	0
4776	return Error(IDLoc, "too few operands for instruction");	0
4777	}	----
4778	ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();	0
4779	if (ErrorLoc == SMLoc())	0
4780	ErrorLoc = IDLoc;	0
4781		----
4782	if (isInvalidVOPDY(Operands, ErrorInfo))	0
4783	return Error(ErrorLoc, "invalid VOPDY instruction");	0
4784	}	----
4785	return Error(ErrorLoc, "invalid operand for instruction");	0
4786	}	----
4787		----
4788	case Match_PreferE32:	0
4789	return Error(IDLoc, "internal error: instruction without _e64 suffix "	0
4790	"should be encoded as e32");	0
4791	case Match_MnemonicFail:	0
4792	llvm_unreachable("Invalid instructions should have been handled already");	0
4793	}	----
4794	llvm_unreachable("Implement any new match types added!");	0
4795	}	0
4796		----
4797	bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {	0
4798	int64_t Tmp = -1;	0
4799	if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {	0
4800	return true;	0
4801	}	----
4802	if (getParser().parseAbsoluteExpression(Tmp)) {	0
4803	return true;	0
4804	}	----
4805	Ret = static_cast(Tmp);	0
4806	return false;	0
4807	}	----
4808		----
4809	bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,	0
4810	uint32_t &Minor) {	----
4811	if (ParseAsAbsoluteExpression(Major))	0
4812	return TokError("invalid major version");	0
4813		----
4814	if (!trySkipToken(AsmToken::Comma))	0
4815	return TokError("minor version number required, comma expected");	0
4816		----
4817	if (ParseAsAbsoluteExpression(Minor))	0
4818	return TokError("invalid minor version");	0
4819		----
4820	return false;	0
4821	}	----
4822		----
4823	bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {	0
4824	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	0
4825	return TokError("directive only supported for amdgcn architecture");	0
4826		----
4827	std::string TargetIDDirective;	0
4828	SMLoc TargetStart = getTok().getLoc();	0
4829	if (getParser().parseEscapedString(TargetIDDirective))	0
4830	return true;	0
4831		----
4832	SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());	0
4833	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	0
4834	return getParser().Error(TargetRange.Start,	0
4835	(Twine(".amdgcn_target directive's target id ") +	0
4836	Twine(TargetIDDirective) +	0
4837	Twine(" does not match the specified target id ") +	0
4838	Twine(getTargetStreamer().getTargetID()->toString())).str());	0
4839		----
4840	return false;	0
4841	}	0
4842		----
4843	bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {	0
4844	return Error(Range.Start, "value out of range", Range);	0
4845	}	----
4846		----
4847	bool AMDGPUAsmParser::calculateGPRBlocks(	0
4848	const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,	----
4849	bool XNACKUsed, std::optional EnableWavefrontSize32,	----
4850	unsigned NextFreeVGPR, SMRange VGPRRange, unsigned NextFreeSGPR,	----
4851	SMRange SGPRRange, unsigned &VGPRBlocks, unsigned &SGPRBlocks) {	----
4852	// TODO(scott.linder): These calculations are duplicated from	----
4853	// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.	----
4854	IsaVersion Version = getIsaVersion(getSTI().getCPU());	0
4855		----
4856	unsigned NumVGPRs = NextFreeVGPR;	0
4857	unsigned NumSGPRs = NextFreeSGPR;	0
4858		----
4859	if (Version.Major >= 10)	0
4860	NumSGPRs = 0;	0
4861	else {	----
4862	unsigned MaxAddressableNumSGPRs =	----
4863	IsaInfo::getAddressableNumSGPRs(&getSTI());	0
4864		----
4865	if (Version.Major >= 8 && !Features.test(FeatureSGPRInitBug) &&	0
4866	NumSGPRs > MaxAddressableNumSGPRs)	----
4867	return OutOfRangeError(SGPRRange);	0
4868		----
4869	NumSGPRs +=	0
4870	IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);	0
4871		----
4872	if ((Version.Major <= 7 \|\| Features.test(FeatureSGPRInitBug)) &&	0
4873	NumSGPRs > MaxAddressableNumSGPRs)	----
4874	return OutOfRangeError(SGPRRange);	0
4875		----
4876	if (Features.test(FeatureSGPRInitBug))	0
4877	NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;	0
4878	}	----
4879		----
4880	VGPRBlocks =	0
4881	IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);	0
4882	SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);	0
4883		----
4884	return false;	0
4885	}	----
4886		----
4887	bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {	0
4888	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	0
4889	return TokError("directive only supported for amdgcn architecture");	0
4890		----
4891	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)	0
4892	return TokError("directive only supported for amdhsa OS");	0
4893		----
4894	StringRef KernelName;	0
4895	if (getParser().parseIdentifier(KernelName))	0
4896	return true;	0
4897		----
4898	kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());	0
4899		----
4900	StringSet<> Seen;	0
4901		----
4902	IsaVersion IVersion = getIsaVersion(getSTI().getCPU());	0
4903		----
4904	SMRange VGPRRange;	0
4905	uint64_t NextFreeVGPR = 0;	0
4906	uint64_t AccumOffset = 0;	0
4907	uint64_t SharedVGPRCount = 0;	0
4908	SMRange SGPRRange;	0
4909	uint64_t NextFreeSGPR = 0;	0
4910		----
4911	// Count the number of user SGPRs implied from the enabled feature bits.	----
4912	unsigned ImpliedUserSGPRCount = 0;	0
4913		----
4914	// Track if the asm explicitly contains the directive for the user SGPR	----
4915	// count.	----
4916	std::optional ExplicitUserSGPRCount;	0
4917	bool ReserveVCC = true;	0
4918	bool ReserveFlatScr = true;	0
4919	std::optional EnableWavefrontSize32;	0
4920		----
4921	while (true) {	----
4922	while (trySkipToken(AsmToken::EndOfStatement));	0
4923		----
4924	StringRef ID;	0
4925	SMRange IDRange = getTok().getLocRange();	0
4926	if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))	0
4927	return true;	0
4928		----
4929	if (ID == ".end_amdhsa_kernel")	0
4930	break;	0
4931		----
4932	if (!Seen.insert(ID).second)	0
4933	return TokError(".amdhsa_ directives cannot be repeated");	0
4934		----
4935	SMLoc ValStart = getLoc();	0
4936	int64_t IVal;	----
4937	if (getParser().parseAbsoluteExpression(IVal))	0
4938	return true;	0
4939	SMLoc ValEnd = getLoc();	0
4940	SMRange ValRange = SMRange(ValStart, ValEnd);	0
4941		----
4942	if (IVal < 0)	0
4943	return OutOfRangeError(ValRange);	0
4944		----
4945	uint64_t Val = IVal;	0
4946		----
4947	#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE) \	----
4948	if (!isUInt(VALUE)) \	----
4949	return OutOfRangeError(RANGE); \	----
4950	AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);	----
4951		----
4952	if (ID == ".amdhsa_group_segment_fixed_size") {	0
4953	if (!isUInt(Val))	0
4954	return OutOfRangeError(ValRange);	0
4955	KD.group_segment_fixed_size = Val;	0
4956	} else if (ID == ".amdhsa_private_segment_fixed_size") {	0
4957	if (!isUInt(Val))	0
4958	return OutOfRangeError(ValRange);	0
4959	KD.private_segment_fixed_size = Val;	0
4960	} else if (ID == ".amdhsa_kernarg_size") {	0
4961	if (!isUInt(Val))	0
4962	return OutOfRangeError(ValRange);	0
4963	KD.kernarg_size = Val;	0
4964	} else if (ID == ".amdhsa_user_sgpr_count") {	0
4965	ExplicitUserSGPRCount = Val;	0
4966	} else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {	0
4967	if (hasArchitectedFlatScratch())	0
4968	return Error(IDRange.Start,	0
4969	"directive is not supported with architected flat scratch",	----
4970	IDRange);	0
4971	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4972	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,	----
4973	Val, ValRange);	----
4974	if (Val)	0
4975	ImpliedUserSGPRCount += 4;	0
4976	} else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {	0
4977	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4978	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,	----
4979	ValRange);	----
4980	if (Val)	0
4981	ImpliedUserSGPRCount += 2;	0
4982	} else if (ID == ".amdhsa_user_sgpr_queue_ptr") {	0
4983	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4984	KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,	----
4985	ValRange);	----
4986	if (Val)	0
4987	ImpliedUserSGPRCount += 2;	0
4988	} else if (ID == ".amdhsa_user_sgpr_kernarg_segment_ptr") {	0
4989	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4990	KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,	----
4991	Val, ValRange);	----
4992	if (Val)	0
4993	ImpliedUserSGPRCount += 2;	0
4994	} else if (ID == ".amdhsa_user_sgpr_dispatch_id") {	0
4995	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4996	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,	----
4997	ValRange);	----
4998	if (Val)	0
4999	ImpliedUserSGPRCount += 2;	0
5000	} else if (ID == ".amdhsa_user_sgpr_flat_scratch_init") {	0
5001	if (hasArchitectedFlatScratch())	0
5002	return Error(IDRange.Start,	0
5003	"directive is not supported with architected flat scratch",	----
5004	IDRange);	0
5005	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5006	KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,	----
5007	ValRange);	----
5008	if (Val)	0
5009	ImpliedUserSGPRCount += 2;	0
5010	} else if (ID == ".amdhsa_user_sgpr_private_segment_size") {	0
5011	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5012	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,	----
5013	Val, ValRange);	----
5014	if (Val)	0
5015	ImpliedUserSGPRCount += 1;	0
5016	} else if (ID == ".amdhsa_wavefront_size32") {	0
5017	if (IVersion.Major < 10)	0
5018	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5019	EnableWavefrontSize32 = Val;	0
5020	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5021	KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,	----
5022	Val, ValRange);	----
5023	} else if (ID == ".amdhsa_uses_dynamic_stack") {	0
5024	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5025	KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, Val, ValRange);	----
5026	} else if (ID == ".amdhsa_system_sgpr_private_segment_wavefront_offset") {	0
5027	if (hasArchitectedFlatScratch())	0
5028	return Error(IDRange.Start,	0
5029	"directive is not supported with architected flat scratch",	----
5030	IDRange);	0
5031	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5032	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	----
5033	} else if (ID == ".amdhsa_enable_private_segment") {	0
5034	if (!hasArchitectedFlatScratch())	0
5035	return Error(	0
5036	IDRange.Start,	----
5037	"directive is not supported without architected flat scratch",	----
5038	IDRange);	0
5039	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5040	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	----
5041	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_x") {	0
5042	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5043	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,	----
5044	ValRange);	----
5045	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_y") {	0
5046	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5047	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,	----
5048	ValRange);	----
5049	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_z") {	0
5050	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5051	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,	----
5052	ValRange);	----
5053	} else if (ID == ".amdhsa_system_sgpr_workgroup_info") {	0
5054	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5055	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,	----
5056	ValRange);	----
5057	} else if (ID == ".amdhsa_system_vgpr_workitem_id") {	0
5058	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5059	COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,	----
5060	ValRange);	----
5061	} else if (ID == ".amdhsa_next_free_vgpr") {	0
5062	VGPRRange = ValRange;	0
5063	NextFreeVGPR = Val;	0
5064	} else if (ID == ".amdhsa_next_free_sgpr") {	0
5065	SGPRRange = ValRange;	0
5066	NextFreeSGPR = Val;	0
5067	} else if (ID == ".amdhsa_accum_offset") {	0
5068	if (!isGFX90A())	0
5069	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	0
5070	AccumOffset = Val;	0
5071	} else if (ID == ".amdhsa_reserve_vcc") {	0
5072	if (!isUInt<1>(Val))	0
5073	return OutOfRangeError(ValRange);	0
5074	ReserveVCC = Val;	0
5075	} else if (ID == ".amdhsa_reserve_flat_scratch") {	0
5076	if (IVersion.Major < 7)	0
5077	return Error(IDRange.Start, "directive requires gfx7+", IDRange);	0
5078	if (hasArchitectedFlatScratch())	0
5079	return Error(IDRange.Start,	0
5080	"directive is not supported with architected flat scratch",	----
5081	IDRange);	0
5082	if (!isUInt<1>(Val))	0
5083	return OutOfRangeError(ValRange);	0
5084	ReserveFlatScr = Val;	0
5085	} else if (ID == ".amdhsa_reserve_xnack_mask") {	0
5086	if (IVersion.Major < 8)	0
5087	return Error(IDRange.Start, "directive requires gfx8+", IDRange);	0
5088	if (!isUInt<1>(Val))	0
5089	return OutOfRangeError(ValRange);	0
5090	if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())	0
5091	return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",	0
5092	IDRange);	0
5093	} else if (ID == ".amdhsa_float_round_mode_32") {	0
5094	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5095	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);	----
5096	} else if (ID == ".amdhsa_float_round_mode_16_64") {	0
5097	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5098	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);	----
5099	} else if (ID == ".amdhsa_float_denorm_mode_32") {	0
5100	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5101	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);	----
5102	} else if (ID == ".amdhsa_float_denorm_mode_16_64") {	0
5103	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5104	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,	----
5105	ValRange);	----
5106	} else if (ID == ".amdhsa_dx10_clamp") {	0
5107	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5108	COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);	----
5109	} else if (ID == ".amdhsa_ieee_mode") {	0
5110	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,	0
5111	Val, ValRange);	----
5112	} else if (ID == ".amdhsa_fp16_overflow") {	0
5113	if (IVersion.Major < 9)	0
5114	return Error(IDRange.Start, "directive requires gfx9+", IDRange);	0
5115	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,	0
5116	ValRange);	----
5117	} else if (ID == ".amdhsa_tg_split") {	0
5118	if (!isGFX90A())	0
5119	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	0
5120	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Val,	0
5121	ValRange);	----
5122	} else if (ID == ".amdhsa_workgroup_processor_mode") {	0
5123	if (IVersion.Major < 10)	0
5124	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5125	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,	0
5126	ValRange);	----
5127	} else if (ID == ".amdhsa_memory_ordered") {	0
5128	if (IVersion.Major < 10)	0
5129	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5130	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,	0
5131	ValRange);	----
5132	} else if (ID == ".amdhsa_forward_progress") {	0
5133	if (IVersion.Major < 10)	0
5134	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5135	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,	0
5136	ValRange);	----
5137	} else if (ID == ".amdhsa_shared_vgpr_count") {	0
5138	if (IVersion.Major < 10)	0
5139	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5140	SharedVGPRCount = Val;	0
5141	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3,	0
5142	COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, Val,	----
5143	ValRange);	----
5144	} else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {	0
5145	PARSE_BITS_ENTRY(	0
5146	KD.compute_pgm_rsrc2,	----
5147	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,	----
5148	ValRange);	----
5149	} else if (ID == ".amdhsa_exception_fp_denorm_src") {	0
5150	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5151	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,	----
5152	Val, ValRange);	----
5153	} else if (ID == ".amdhsa_exception_fp_ieee_div_zero") {	0
5154	PARSE_BITS_ENTRY(	0
5155	KD.compute_pgm_rsrc2,	----
5156	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,	----
5157	ValRange);	----
5158	} else if (ID == ".amdhsa_exception_fp_ieee_overflow") {	0
5159	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5160	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,	----
5161	Val, ValRange);	----
5162	} else if (ID == ".amdhsa_exception_fp_ieee_underflow") {	0
5163	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5164	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,	----
5165	Val, ValRange);	----
5166	} else if (ID == ".amdhsa_exception_fp_ieee_inexact") {	0
5167	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5168	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,	----
5169	Val, ValRange);	----
5170	} else if (ID == ".amdhsa_exception_int_div_zero") {	0
5171	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5172	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,	----
5173	Val, ValRange);	----
5174	} else {	----
5175	return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange);	0
5176	}	----
5177		----
5178	#undef PARSE_BITS_ENTRY	----
5179	}	0
5180		----
5181	if (!Seen.contains(".amdhsa_next_free_vgpr"))	0
5182	return TokError(".amdhsa_next_free_vgpr directive is required");	0
5183		----
5184	if (!Seen.contains(".amdhsa_next_free_sgpr"))	0
5185	return TokError(".amdhsa_next_free_sgpr directive is required");	0
5186		----
5187	unsigned VGPRBlocks;	----
5188	unsigned SGPRBlocks;	----
5189	if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,	0
5190	getTargetStreamer().getTargetID()->isXnackOnOrAny(),	0
5191	EnableWavefrontSize32, NextFreeVGPR,	----
5192	VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,	----
5193	SGPRBlocks))	----
5194	return true;	0
5195		----
5196	if (!isUInt(	0
5197	VGPRBlocks))	----
5198	return OutOfRangeError(VGPRRange);	0
5199	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	0
5200	COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, VGPRBlocks);	----
5201		----
5202	if (!isUInt(	0
5203	SGPRBlocks))	----
5204	return OutOfRangeError(SGPRRange);	0
5205	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	0
5206	COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT,	----
5207	SGPRBlocks);	----
5208		----
5209	if (ExplicitUserSGPRCount && ImpliedUserSGPRCount > *ExplicitUserSGPRCount)	0
5210	return TokError("amdgpu_user_sgpr_count smaller than than implied by "	0
5211	"enabled user SGPRs");	0
5212		----
5213	unsigned UserSGPRCount =	----
5214	ExplicitUserSGPRCount ? *ExplicitUserSGPRCount : ImpliedUserSGPRCount;	0
5215		----
5216	if (!isUInt(UserSGPRCount))	0
5217	return TokError("too many user SGPRs enabled");	0
5218	AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,	0
5219	UserSGPRCount);	----
5220		----
5221	if (isGFX90A()) {	0
5222	if (!Seen.contains(".amdhsa_accum_offset"))	0
5223	return TokError(".amdhsa_accum_offset directive is required");	0
5224	if (AccumOffset < 4 \|\| AccumOffset > 256 \|\| (AccumOffset & 3))	0
5225	return TokError("accum_offset should be in range [4..256] in "	0
5226	"increments of 4");	0
5227	if (AccumOffset > alignTo(std::max((uint64_t)1, NextFreeVGPR), 4))	0
5228	return TokError("accum_offset exceeds total VGPR allocation");	0
5229	AMDHSA_BITS_SET(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,	0
5230	(AccumOffset / 4 - 1));	----
5231	}	----
5232		----
5233	if (IVersion.Major >= 10) {	0
5234	// SharedVGPRCount < 16 checked by PARSE_ENTRY_BITS	----
5235	if (SharedVGPRCount && EnableWavefrontSize32 && *EnableWavefrontSize32) {	0
5236	return TokError("shared_vgpr_count directive not valid on "	0
5237	"wavefront size 32");	0
5238	}	----
5239	if (SharedVGPRCount * 2 + VGPRBlocks > 63) {	0
5240	return TokError("shared_vgpr_count*2 + "	0
5241	"compute_pgm_rsrc1.GRANULATED_WORKITEM_VGPR_COUNT cannot "	----
5242	"exceed 63\n");	0
5243	}	----
5244	}	----
5245		----
5246	getTargetStreamer().EmitAmdhsaKernelDescriptor(	0
5247	getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,	----
5248	ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion());	----
5249	return false;	0
5250	}	0
5251		----
5252	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {	0
5253	uint32_t Major;	----
5254	uint32_t Minor;	----
5255		----
5256	if (ParseDirectiveMajorMinor(Major, Minor))	0
5257	return true;	0
5258		----
5259	getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);	0
5260	return false;	0
5261	}	----
5262		----
5263	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {	0
5264	uint32_t Major;	----
5265	uint32_t Minor;	----
5266	uint32_t Stepping;	----
5267	StringRef VendorName;	0
5268	StringRef ArchName;	0
5269		----
5270	// If this directive has no arguments, then use the ISA version for the	----
5271	// targeted GPU.	----
5272	if (isToken(AsmToken::EndOfStatement)) {	0
5273	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
5274	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,	0
5275	ISA.Stepping,	----
5276	"AMD", "AMDGPU");	----
5277	return false;	0
5278	}	----
5279		----
5280	if (ParseDirectiveMajorMinor(Major, Minor))	0
5281	return true;	0
5282		----
5283	if (!trySkipToken(AsmToken::Comma))	0
5284	return TokError("stepping version number required, comma expected");	0
5285		----
5286	if (ParseAsAbsoluteExpression(Stepping))	0
5287	return TokError("invalid stepping version");	0
5288		----
5289	if (!trySkipToken(AsmToken::Comma))	0
5290	return TokError("vendor name required, comma expected");	0
5291		----
5292	if (!parseString(VendorName, "invalid vendor name"))	0
5293	return true;	0
5294		----
5295	if (!trySkipToken(AsmToken::Comma))	0
5296	return TokError("arch name required, comma expected");	0
5297		----
5298	if (!parseString(ArchName, "invalid arch name"))	0
5299	return true;	0
5300		----
5301	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,	0
5302	VendorName, ArchName);	----
5303	return false;	0
5304	}	----
5305		----
5306	bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,	0
5307	amd_kernel_code_t &Header) {	----
5308	// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing	----
5309	// assembly for backwards compatibility.	----
5310	if (ID == "max_scratch_backing_memory_byte_size") {	0
5311	Parser.eatToEndOfStatement();	0
5312	return false;	0
5313	}	----
5314		----
5315	SmallString<40> ErrStr;	0
5316	raw_svector_ostream Err(ErrStr);	0
5317	if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {	0
5318	return TokError(Err.str());	0
5319	}	----
5320	Lex();	0
5321		----
5322	if (ID == "enable_wavefront_size32") {	0
5323	if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) {	0
5324	if (!isGFX10Plus())	0
5325	return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");	0
5326	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	0
5327	return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");	0
5328	} else {	----
5329	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	0
5330	return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");	0
5331	}	----
5332	}	----
5333		----
5334	if (ID == "wavefront_size") {	0
5335	if (Header.wavefront_size == 5) {	0
5336	if (!isGFX10Plus())	0
5337	return TokError("wavefront_size=5 is only allowed on GFX10+");	0
5338	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	0
5339	return TokError("wavefront_size=5 requires +WavefrontSize32");	0
5340	} else if (Header.wavefront_size == 6) {	0
5341	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	0
5342	return TokError("wavefront_size=6 requires +WavefrontSize64");	0
5343	}	----
5344	}	----
5345		----
5346	if (ID == "enable_wgp_mode") {	0
5347	if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) &&	0
5348	!isGFX10Plus())	0
5349	return TokError("enable_wgp_mode=1 is only allowed on GFX10+");	0
5350	}	----
5351		----
5352	if (ID == "enable_mem_ordered") {	0
5353	if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) &&	0
5354	!isGFX10Plus())	0
5355	return TokError("enable_mem_ordered=1 is only allowed on GFX10+");	0
5356	}	----
5357		----
5358	if (ID == "enable_fwd_progress") {	0
5359	if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) &&	0
5360	!isGFX10Plus())	0
5361	return TokError("enable_fwd_progress=1 is only allowed on GFX10+");	0
5362	}	----
5363		----
5364	return false;	0
5365	}	0
5366		----
5367	bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {	0
5368	amd_kernel_code_t Header;	----
5369	AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());	0
5370		----
5371	while (true) {	----
5372	// Lex EndOfStatement. This is in a while loop, because lexing a comment	----
5373	// will set the current token to EndOfStatement.	----
5374	while(trySkipToken(AsmToken::EndOfStatement));	0
5375		----
5376	StringRef ID;	0
5377	if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))	0
5378	return true;	0
5379		----
5380	if (ID == ".end_amd_kernel_code_t")	0
5381	break;	0
5382		----
5383	if (ParseAMDKernelCodeTValue(ID, Header))	0
5384	return true;	0
5385	}	0
5386		----
5387	getTargetStreamer().EmitAMDKernelCodeT(Header);	0
5388		----
5389	return false;	0
5390	}	----
5391		----
5392	bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {	0
5393	StringRef KernelName;	0
5394	if (!parseId(KernelName, "expected symbol name"))	0
5395	return true;	0
5396		----
5397	getTargetStreamer().EmitAMDGPUSymbolType(KernelName,	0
5398	ELF::STT_AMDGPU_HSA_KERNEL);	----
5399		----
5400	KernelScope.initialize(getContext());	0
5401	return false;	0
5402	}	----
5403		----
5404	bool AMDGPUAsmParser::ParseDirectiveISAVersion() {	0
5405	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {	0
5406	return Error(getLoc(),	0
5407	".amd_amdgpu_isa directive is not available on non-amdgcn "	----
5408	"architectures");	0
5409	}	----
5410		----
5411	auto TargetIDDirective = getLexer().getTok().getStringContents();	0
5412	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	0
5413	return Error(getParser().getTok().getLoc(), "target id must match options");	0
5414		----
5415	getTargetStreamer().EmitISAVersion();	0
5416	Lex();	0
5417		----
5418	return false;	0
5419	}	----
5420		----
5421	bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {	0
5422	const char *AssemblerDirectiveBegin;	----
5423	const char *AssemblerDirectiveEnd;	----
5424	std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =	0
5425	isHsaAbiVersion3AndAbove(&getSTI())	0
5426	? std::pair(HSAMD::V3::AssemblerDirectiveBegin,	0
5427	HSAMD::V3::AssemblerDirectiveEnd)	0
5428	: std::pair(HSAMD::AssemblerDirectiveBegin,	0
5429	HSAMD::AssemblerDirectiveEnd);	0
5430		----
5431	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {	0
5432	return Error(getLoc(),	0
5433	(Twine(AssemblerDirectiveBegin) + Twine(" directive is "	0
5434	"not available on non-amdhsa OSes")).str());	0
5435	}	----
5436		----
5437	std::string HSAMetadataString;	0
5438	if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,	0
5439	HSAMetadataString))	----
5440	return true;	0
5441		----
5442	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0
5443	if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))	0
5444	return Error(getLoc(), "invalid HSA metadata");	0
5445	} else {	----
5446	if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))	0
5447	return Error(getLoc(), "invalid HSA metadata");	0
5448	}	----
5449		----
5450	return false;	0
5451	}	0
5452		----
5453	/// Common code to parse out a block of text (typically YAML) between start and	----
5454	/// end directives.	----
5455	bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,	0
5456	const char *AssemblerDirectiveEnd,	----
5457	std::string &CollectString) {	----
5458		----
5459	raw_string_ostream CollectStream(CollectString);	0
5460		----
5461	getLexer().setSkipSpace(false);	0
5462		----
5463	bool FoundEnd = false;	0
5464	while (!isToken(AsmToken::Eof)) {	0
5465	while (isToken(AsmToken::Space)) {	0
5466	CollectStream << getTokenStr();	0
5467	Lex();	0
5468	}	----
5469		----
5470	if (trySkipId(AssemblerDirectiveEnd)) {	0
5471	FoundEnd = true;	0
5472	break;	0
5473	}	----
5474		----
5475	CollectStream << Parser.parseStringToEndOfStatement()	0
5476	<< getContext().getAsmInfo()->getSeparatorString();	0
5477		----
5478	Parser.eatToEndOfStatement();	0
5479	}	----
5480		----
5481	getLexer().setSkipSpace(true);	0
5482		----
5483	if (isToken(AsmToken::Eof) && !FoundEnd) {	0
5484	return TokError(Twine("expected directive ") +	0
5485	Twine(AssemblerDirectiveEnd) + Twine(" not found"));	0
5486	}	----
5487		----
5488	CollectStream.flush();	0
5489	return false;	0
5490	}	0
5491		----
5492	/// Parse the assembler directive for new MsgPack-format PAL metadata.	----
5493	bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {	0
5494	std::string String;	0
5495	if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin,	0
5496	AMDGPU::PALMD::AssemblerDirectiveEnd, String))	----
5497	return true;	0
5498		----
5499	auto PALMetadata = getTargetStreamer().getPALMetadata();	0
5500	if (!PALMetadata->setFromString(String))	0
5501	return Error(getLoc(), "invalid PAL metadata");	0
5502	return false;	0
5503	}	0
5504		----
5505	/// Parse the assembler directive for old linear-format PAL metadata.	----
5506	bool AMDGPUAsmParser::ParseDirectivePALMetadata() {	0
5507	if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {	0
5508	return Error(getLoc(),	0
5509	(Twine(PALMD::AssemblerDirective) + Twine(" directive is "	0
5510	"not available on non-amdpal OSes")).str());	0
5511	}	----
5512		----
5513	auto PALMetadata = getTargetStreamer().getPALMetadata();	0
5514	PALMetadata->setLegacy();	0
5515	for (;;) {	----
5516	uint32_t Key, Value;	----
5517	if (ParseAsAbsoluteExpression(Key)) {	0
5518	return TokError(Twine("invalid value in ") +	0
5519	Twine(PALMD::AssemblerDirective));	0
5520	}	----
5521	if (!trySkipToken(AsmToken::Comma)) {	0
5522	return TokError(Twine("expected an even number of values in ") +	0
5523	Twine(PALMD::AssemblerDirective));	0
5524	}	----
5525	if (ParseAsAbsoluteExpression(Value)) {	0
5526	return TokError(Twine("invalid value in ") +	0
5527	Twine(PALMD::AssemblerDirective));	0
5528	}	----
5529	PALMetadata->setRegister(Key, Value);	0
5530	if (!trySkipToken(AsmToken::Comma))	0
5531	break;	0
5532	}	0
5533	return false;	0
5534	}	----
5535		----
5536	/// ParseDirectiveAMDGPULDS	----
5537	/// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression]	----
5538	bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {	0
5539	if (getParser().checkForValidSection())	0
5540	return true;	0
5541		----
5542	StringRef Name;	0
5543	SMLoc NameLoc = getLoc();	0
5544	if (getParser().parseIdentifier(Name))	0
5545	return TokError("expected identifier in directive");	0
5546		----
5547	MCSymbol *Symbol = getContext().getOrCreateSymbol(Name);	0
5548	if (getParser().parseComma())	0
5549	return true;	0
5550		----
5551	unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());	0
5552		----
5553	int64_t Size;	----
5554	SMLoc SizeLoc = getLoc();	0
5555	if (getParser().parseAbsoluteExpression(Size))	0
5556	return true;	0
5557	if (Size < 0)	0
5558	return Error(SizeLoc, "size must be non-negative");	0
5559	if (Size > LocalMemorySize)	0
5560	return Error(SizeLoc, "size is too large");	0
5561		----
5562	int64_t Alignment = 4;	0
5563	if (trySkipToken(AsmToken::Comma)) {	0
5564	SMLoc AlignLoc = getLoc();	0
5565	if (getParser().parseAbsoluteExpression(Alignment))	0
5566	return true;	0
5567	if (Alignment < 0 \|\| !isPowerOf2_64(Alignment))	0
5568	return Error(AlignLoc, "alignment must be a power of two");	0
5569		----
5570	// Alignment larger than the size of LDS is possible in theory, as long	----
5571	// as the linker manages to place to symbol at address 0, but we do want	----
5572	// to make sure the alignment fits nicely into a 32-bit integer.	----
5573	if (Alignment >= 1u << 31)	0
5574	return Error(AlignLoc, "alignment is too large");	0
5575	}	----
5576		----
5577	if (parseEOL())	0
5578	return true;	0
5579		----
5580	Symbol->redefineIfPossible();	0
5581	if (!Symbol->isUndefined())	0
5582	return Error(NameLoc, "invalid symbol redefinition");	0
5583		----
5584	getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));	0
5585	return false;	0
5586	}	----
5587		----
5588	bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {	0
5589	StringRef IDVal = DirectiveID.getString();	0
5590		----
5591	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0
5592	if (IDVal == ".amdhsa_kernel")	0
5593	return ParseDirectiveAMDHSAKernel();	0
5594		----
5595	// TODO: Restructure/combine with PAL metadata directive.	----
5596	if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)	0
5597	return ParseDirectiveHSAMetadata();	0
5598	} else {	----
5599	if (IDVal == ".hsa_code_object_version")	0
5600	return ParseDirectiveHSACodeObjectVersion();	0
5601		----
5602	if (IDVal == ".hsa_code_object_isa")	0
5603	return ParseDirectiveHSACodeObjectISA();	0
5604		----
5605	if (IDVal == ".amd_kernel_code_t")	0
5606	return ParseDirectiveAMDKernelCodeT();	0
5607		----
5608	if (IDVal == ".amdgpu_hsa_kernel")	0
5609	return ParseDirectiveAMDGPUHsaKernel();	0
5610		----
5611	if (IDVal == ".amd_amdgpu_isa")	0
5612	return ParseDirectiveISAVersion();	0
5613		----
5614	if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)	0
5615	return ParseDirectiveHSAMetadata();	0
5616	}	----
5617		----
5618	if (IDVal == ".amdgcn_target")	0
5619	return ParseDirectiveAMDGCNTarget();	0
5620		----
5621	if (IDVal == ".amdgpu_lds")	0
5622	return ParseDirectiveAMDGPULDS();	0
5623		----
5624	if (IDVal == PALMD::AssemblerDirectiveBegin)	0
5625	return ParseDirectivePALMetadataBegin();	0
5626		----
5627	if (IDVal == PALMD::AssemblerDirective)	0
5628	return ParseDirectivePALMetadata();	0
5629		----
5630	return true;	0
5631	}	----
5632		----
5633	bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,	0
5634	unsigned RegNo) {	----
5635		----
5636	if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))	0
5637	return isGFX9Plus();	0
5638		----
5639	// GFX10+ has 2 more SGPRs 104 and 105.	----
5640	if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))	0
5641	return hasSGPR104_SGPR105();	0
5642		----
5643	switch (RegNo) {	0
5644	case AMDGPU::SRC_SHARED_BASE_LO:	0
5645	case AMDGPU::SRC_SHARED_BASE:	----
5646	case AMDGPU::SRC_SHARED_LIMIT_LO:	----
5647	case AMDGPU::SRC_SHARED_LIMIT:	----
5648	case AMDGPU::SRC_PRIVATE_BASE_LO:	----
5649	case AMDGPU::SRC_PRIVATE_BASE:	----
5650	case AMDGPU::SRC_PRIVATE_LIMIT_LO:	----
5651	case AMDGPU::SRC_PRIVATE_LIMIT:	----
5652	return isGFX9Plus();	0
5653	case AMDGPU::SRC_POPS_EXITING_WAVE_ID:	0
5654	return isGFX9Plus() && !isGFX11Plus();	0
5655	case AMDGPU::TBA:	0
5656	case AMDGPU::TBA_LO:	----
5657	case AMDGPU::TBA_HI:	----
5658	case AMDGPU::TMA:	----
5659	case AMDGPU::TMA_LO:	----
5660	case AMDGPU::TMA_HI:	----
5661	return !isGFX9Plus();	0
5662	case AMDGPU::XNACK_MASK:	0
5663	case AMDGPU::XNACK_MASK_LO:	----
5664	case AMDGPU::XNACK_MASK_HI:	----
5665	return (isVI() \|\| isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();	0
5666	case AMDGPU::SGPR_NULL:	0
5667	return isGFX10Plus();	0
5668	default:	0
5669	break;	0
5670	}	----
5671		----
5672	if (isCI())	0
5673	return true;	0
5674		----
5675	if (isSI() \|\| isGFX10Plus()) {	0
5676	// No flat_scr on SI.	----
5677	// On GFX10Plus flat scratch is not a valid register operand and can only be	----
5678	// accessed with s_setreg/s_getreg.	----
5679	switch (RegNo) {	0
5680	case AMDGPU::FLAT_SCR:	0
5681	case AMDGPU::FLAT_SCR_LO:	----
5682	case AMDGPU::FLAT_SCR_HI:	----
5683	return false;	0
5684	default:	0
5685	return true;	0
5686	}	----
5687	}	----
5688		----
5689	// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that	----
5690	// SI/CI have.	----
5691	if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))	0
5692	return hasSGPR102_SGPR103();	0
5693		----
5694	return true;	0
5695	}	----
5696		----
5697	ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,	0
5698	StringRef Mnemonic,	----
5699	OperandMode Mode) {	----
5700	ParseStatus Res = parseVOPD(Operands);	0
5701	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	0
5702	return Res;	0
5703		----
5704	// Try to parse with a custom parser	----
5705	Res = MatchOperandParserImpl(Operands, Mnemonic);	0
5706		----
5707	// If we successfully parsed the operand or if there as an error parsing,	----
5708	// we are done.	----
5709	//	----
5710	// If we are parsing after we reach EndOfStatement then this means we	----
5711	// are appending default values to the Operands list. This is only done	----
5712	// by custom parser, so we shouldn't continue on to the generic parsing.	----
5713	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	0
5714	return Res;	0
5715		----
5716	SMLoc RBraceLoc;	0
5717	SMLoc LBraceLoc = getLoc();	0
5718	if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {	0
5719	unsigned Prefix = Operands.size();	0
5720		----
5721	for (;;) {	----
5722	auto Loc = getLoc();	0
5723	Res = parseReg(Operands);	0
5724	if (Res.isNoMatch())	0
5725	Error(Loc, "expected a register");	0
5726	if (!Res.isSuccess())	0
5727	return ParseStatus::Failure;	0
5728		----
5729	RBraceLoc = getLoc();	0
5730	if (trySkipToken(AsmToken::RBrac))	0
5731	break;	0
5732		----
5733	if (!skipToken(AsmToken::Comma,	0
5734	"expected a comma or a closing square bracket"))	----
5735	return ParseStatus::Failure;	0
5736	}	0
5737		----
5738	if (Operands.size() - Prefix > 1) {	0
5739	Operands.insert(Operands.begin() + Prefix,	0
5740	AMDGPUOperand::CreateToken(this, "[", LBraceLoc));	0
5741	Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));	0
5742	}	----
5743		----
5744	return ParseStatus::Success;	0
5745	}	----
5746		----
5747	return parseRegOrImm(Operands);	0
5748	}	----
5749		----
5750	StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {	0
5751	// Clear any forced encodings from the previous instruction.	----
5752	setForcedEncodingSize(0);	0
5753	setForcedDPP(false);	0
5754	setForcedSDWA(false);	0
5755		----
5756	if (Name.endswith("_e64_dpp")) {	0
5757	setForcedDPP(true);	0
5758	setForcedEncodingSize(64);	0
5759	return Name.substr(0, Name.size() - 8);	0
5760	} else if (Name.endswith("_e64")) {	0
5761	setForcedEncodingSize(64);	0
5762	return Name.substr(0, Name.size() - 4);	0
5763	} else if (Name.endswith("_e32")) {	0
5764	setForcedEncodingSize(32);	0
5765	return Name.substr(0, Name.size() - 4);	0
5766	} else if (Name.endswith("_dpp")) {	0
5767	setForcedDPP(true);	0
5768	return Name.substr(0, Name.size() - 4);	0
5769	} else if (Name.endswith("_sdwa")) {	0
5770	setForcedSDWA(true);	0
5771	return Name.substr(0, Name.size() - 5);	0
5772	}	----
5773	return Name;	0
5774	}	----
5775		----
5776	static void applyMnemonicAliases(StringRef &Mnemonic,	----
5777	const FeatureBitset &Features,	----
5778	unsigned VariantID);	----
5779		----
5780	bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,	0
5781	StringRef Name,	----
5782	SMLoc NameLoc, OperandVector &Operands) {	----
5783	// Add the instruction mnemonic	----
5784	Name = parseMnemonicSuffix(Name);	0
5785		----
5786	// If the target architecture uses MnemonicAlias, call it here to parse	----
5787	// operands correctly.	----
5788	applyMnemonicAliases(Name, getAvailableFeatures(), 0);	0
5789		----
5790	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));	0
5791		----
5792	bool IsMIMG = Name.startswith("image_");	0
5793		----
5794	while (!trySkipToken(AsmToken::EndOfStatement)) {	0
5795	OperandMode Mode = OperandMode_Default;	0
5796	if (IsMIMG && isGFX10Plus() && Operands.size() == 2)	0
5797	Mode = OperandMode_NSA;	0
5798	ParseStatus Res = parseOperand(Operands, Name, Mode);	0
5799		----
5800	if (!Res.isSuccess()) {	0
5801	checkUnsupportedInstruction(Name, NameLoc);	0
5802	if (!Parser.hasPendingError()) {	0
5803	// FIXME: use real operand location rather than the current location.	----
5804	StringRef Msg = Res.isFailure() ? "failed parsing operand."	0
5805	: "not a valid operand.";	0
5806	Error(getLoc(), Msg);	0
5807	}	----
5808	while (!trySkipToken(AsmToken::EndOfStatement)) {	0
5809	lex();	0
5810	}	----
5811	return true;	0
5812	}	----
5813		----
5814	// Eat the comma or space if there is one.	----
5815	trySkipToken(AsmToken::Comma);	0
5816	}	----
5817		----
5818	return false;	0
5819	}	----
5820		----
5821	//===----------------------------------------------------------------------===//	----
5822	// Utility functions	----
5823	//===----------------------------------------------------------------------===//	----
5824		----
5825	ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,	0
5826	OperandVector &Operands) {	----
5827	SMLoc S = getLoc();	0
5828	if (!trySkipId(Name))	0
5829	return ParseStatus::NoMatch;	0
5830		----
5831	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));	0
5832	return ParseStatus::Success;	0
5833	}	----
5834		----
5835	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,	0
5836	int64_t &IntVal) {	----
5837		----
5838	if (!trySkipId(Prefix, AsmToken::Colon))	0
5839	return ParseStatus::NoMatch;	0
5840		----
5841	return parseExpr(IntVal) ? ParseStatus::Success : ParseStatus::Failure;	0
5842	}	----
5843		----
5844	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(	0
5845	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	----
5846	std::function ConvertResult) {	----
5847	SMLoc S = getLoc();	0
5848	int64_t Value = 0;	0
5849		----
5850	ParseStatus Res = parseIntWithPrefix(Prefix, Value);	0
5851	if (!Res.isSuccess())	0
5852	return Res;	0
5853		----
5854	if (ConvertResult && !ConvertResult(Value)) {	0
5855	Error(S, "invalid " + StringRef(Prefix) + " value.");	0
5856	}	----
5857		----
5858	Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));	0
5859	return ParseStatus::Success;	0
5860	}	----
5861		----
5862	ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(	0
5863	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	----
5864	bool (*ConvertResult)(int64_t &)) {	----
5865	SMLoc S = getLoc();	0
5866	if (!trySkipId(Prefix, AsmToken::Colon))	0
5867	return ParseStatus::NoMatch;	0
5868		----
5869	if (!skipToken(AsmToken::LBrac, "expected a left square bracket"))	0
5870	return ParseStatus::Failure;	0
5871		----
5872	unsigned Val = 0;	0
5873	const unsigned MaxSize = 4;	0
5874		----
5875	// FIXME: How to verify the number of elements matches the number of src	----
5876	// operands?	----
5877	for (int I = 0; ; ++I) {	0
5878	int64_t Op;	----
5879	SMLoc Loc = getLoc();	0
5880	if (!parseExpr(Op))	0
5881	return ParseStatus::Failure;	0
5882		----
5883	if (Op != 0 && Op != 1)	0
5884	return Error(Loc, "invalid " + StringRef(Prefix) + " value.");	0
5885		----
5886	Val \|= (Op << I);	0
5887		----
5888	if (trySkipToken(AsmToken::RBrac))	0
5889	break;	0
5890		----
5891	if (I + 1 == MaxSize)	0
5892	return Error(getLoc(), "expected a closing square bracket");	0
5893		----
5894	if (!skipToken(AsmToken::Comma, "expected a comma"))	0
5895	return ParseStatus::Failure;	0
5896	}	0
5897		----
5898	Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));	0
5899	return ParseStatus::Success;	0
5900	}	----
5901		----
5902	ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,	0
5903	OperandVector &Operands,	----
5904	AMDGPUOperand::ImmTy ImmTy) {	----
5905	int64_t Bit;	----
5906	SMLoc S = getLoc();	0
5907		----
5908	if (trySkipId(Name)) {	0
5909	Bit = 1;	0
5910	} else if (trySkipId("no", Name)) {	0
5911	Bit = 0;	0
5912	} else {	----
5913	return ParseStatus::NoMatch;	0
5914	}	----
5915		----
5916	if (Name == "r128" && !hasMIMG_R128())	0
5917	return Error(S, "r128 modifier is not supported on this GPU");	0
5918	if (Name == "a16" && !hasA16())	0
5919	return Error(S, "a16 modifier is not supported on this GPU");	0
5920		----
5921	if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)	0
5922	ImmTy = AMDGPUOperand::ImmTyR128A16;	0
5923		----
5924	Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));	0
5925	return ParseStatus::Success;	0
5926	}	----
5927		----
5928	unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,	0
5929	bool &Disabling) const {	----
5930	Disabling = Id.consume_front("no");	0
5931		----
5932	if (isGFX940() && !Mnemo.startswith("s_")) {	0
5933	return StringSwitch(Id)	0
5934	.Case("nt", AMDGPU::CPol::NT)	0
5935	.Case("sc0", AMDGPU::CPol::SC0)	0
5936	.Case("sc1", AMDGPU::CPol::SC1)	0
5937	.Default(0);	0
5938	}	----
5939		----
5940	return StringSwitch(Id)	0
5941	.Case("dlc", AMDGPU::CPol::DLC)	0
5942	.Case("glc", AMDGPU::CPol::GLC)	0
5943	.Case("scc", AMDGPU::CPol::SCC)	0
5944	.Case("slc", AMDGPU::CPol::SLC)	0
5945	.Default(0);	0
5946	}	----
5947		----
5948	ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {	0
5949	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	0
5950	SMLoc OpLoc = getLoc();	0
5951	unsigned Enabled = 0, Seen = 0;	0
5952	for (;;) {	----
5953	SMLoc S = getLoc();	0
5954	bool Disabling;	----
5955	unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);	0
5956	if (!CPol)	0
5957	break;	0
5958		----
5959	lex();	0
5960		----
5961	if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)	0
5962	return Error(S, "dlc modifier is not supported on this GPU");	0
5963		----
5964	if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)	0
5965	return Error(S, "scc modifier is not supported on this GPU");	0
5966		----
5967	if (Seen & CPol)	0
5968	return Error(S, "duplicate cache policy modifier");	0
5969		----
5970	if (!Disabling)	0
5971	Enabled \|= CPol;	0
5972		----
5973	Seen \|= CPol;	0
5974	}	0
5975		----
5976	if (!Seen)	0
5977	return ParseStatus::NoMatch;	0
5978		----
5979	Operands.push_back(	0
5980	AMDGPUOperand::CreateImm(this, Enabled, OpLoc, AMDGPUOperand::ImmTyCPol));	0
5981	return ParseStatus::Success;	0
5982	}	----
5983		----
5984	static void addOptionalImmOperand(	0
5985	MCInst& Inst, const OperandVector& Operands,	----
5986	AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,	----
5987	AMDGPUOperand::ImmTy ImmT,	----
5988	int64_t Default = 0) {	----
5989	auto i = OptionalIdx.find(ImmT);	0
5990	if (i != OptionalIdx.end()) {	0
5991	unsigned Idx = i->second;	0
5992	((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);	0
5993	} else {	----
5994	Inst.addOperand(MCOperand::createImm(Default));	0
5995	}	----
5996	}	0
5997		----
5998	ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,	0
5999	StringRef &Value,	----
6000	SMLoc &StringLoc) {	----
6001	if (!trySkipId(Prefix, AsmToken::Colon))	0
6002	return ParseStatus::NoMatch;	0
6003		----
6004	StringLoc = getLoc();	0
6005	return parseId(Value, "expected an identifier") ? ParseStatus::Success	0
6006	: ParseStatus::Failure;	0
6007	}	----
6008		----
6009	//===----------------------------------------------------------------------===//	----
6010	// MTBUF format	----
6011	//===----------------------------------------------------------------------===//	----
6012		----
6013	bool AMDGPUAsmParser::tryParseFmt(const char *Pref,	0
6014	int64_t MaxVal,	----
6015	int64_t &Fmt) {	----
6016	int64_t Val;	----
6017	SMLoc Loc = getLoc();	0
6018		----
6019	auto Res = parseIntWithPrefix(Pref, Val);	0
6020	if (Res.isFailure())	0
6021	return false;	0
6022	if (Res.isNoMatch())	0
6023	return true;	0
6024		----
6025	if (Val < 0 \|\| Val > MaxVal) {	0
6026	Error(Loc, Twine("out of range ", StringRef(Pref)));	0
6027	return false;	0
6028	}	----
6029		----
6030	Fmt = Val;	0
6031	return true;	0
6032	}	----
6033		----
6034	// dfmt and nfmt (in a tbuffer instruction) are parsed as one to allow their	----
6035	// values to live in a joint format operand in the MCInst encoding.	----
6036	ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {	0
6037	using namespace llvm::AMDGPU::MTBUFFormat;	----
6038		----
6039	int64_t Dfmt = DFMT_UNDEF;	0
6040	int64_t Nfmt = NFMT_UNDEF;	0
6041		----
6042	// dfmt and nfmt can appear in either order, and each is optional.	----
6043	for (int I = 0; I < 2; ++I) {	0
6044	if (Dfmt == DFMT_UNDEF && !tryParseFmt("dfmt", DFMT_MAX, Dfmt))	0
6045	return ParseStatus::Failure;	0
6046		----
6047	if (Nfmt == NFMT_UNDEF && !tryParseFmt("nfmt", NFMT_MAX, Nfmt))	0
6048	return ParseStatus::Failure;	0
6049		----
6050	// Skip optional comma between dfmt/nfmt	----
6051	// but guard against 2 commas following each other.	----
6052	if ((Dfmt == DFMT_UNDEF) != (Nfmt == NFMT_UNDEF) &&	0
6053	!peekToken().is(AsmToken::Comma)) {	0
6054	trySkipToken(AsmToken::Comma);	0
6055	}	----
6056	}	----
6057		----
6058	if (Dfmt == DFMT_UNDEF && Nfmt == NFMT_UNDEF)	0
6059	return ParseStatus::NoMatch;	0
6060		----
6061	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	0
6062	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	0
6063		----
6064	Format = encodeDfmtNfmt(Dfmt, Nfmt);	0
6065	return ParseStatus::Success;	0
6066	}	----
6067		----
6068	ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {	0
6069	using namespace llvm::AMDGPU::MTBUFFormat;	----
6070		----
6071	int64_t Fmt = UFMT_UNDEF;	0
6072		----
6073	if (!tryParseFmt("format", UFMT_MAX, Fmt))	0
6074	return ParseStatus::Failure;	0
6075		----
6076	if (Fmt == UFMT_UNDEF)	0
6077	return ParseStatus::NoMatch;	0
6078		----
6079	Format = Fmt;	0
6080	return ParseStatus::Success;	0
6081	}	----
6082		----
6083	bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,	0
6084	int64_t &Nfmt,	----
6085	StringRef FormatStr,	----
6086	SMLoc Loc) {	----
6087	using namespace llvm::AMDGPU::MTBUFFormat;	----
6088	int64_t Format;	----
6089		----
6090	Format = getDfmt(FormatStr);	0
6091	if (Format != DFMT_UNDEF) {	0
6092	Dfmt = Format;	0
6093	return true;	0
6094	}	----
6095		----
6096	Format = getNfmt(FormatStr, getSTI());	0
6097	if (Format != NFMT_UNDEF) {	0
6098	Nfmt = Format;	0
6099	return true;	0
6100	}	----
6101		----
6102	Error(Loc, "unsupported format");	0
6103	return false;	0
6104	}	----
6105		----
6106	ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,	0
6107	SMLoc FormatLoc,	----
6108	int64_t &Format) {	----
6109	using namespace llvm::AMDGPU::MTBUFFormat;	----
6110		----
6111	int64_t Dfmt = DFMT_UNDEF;	0
6112	int64_t Nfmt = NFMT_UNDEF;	0
6113	if (!matchDfmtNfmt(Dfmt, Nfmt, FormatStr, FormatLoc))	0
6114	return ParseStatus::Failure;	0
6115		----
6116	if (trySkipToken(AsmToken::Comma)) {	0
6117	StringRef Str;	0
6118	SMLoc Loc = getLoc();	0
6119	if (!parseId(Str, "expected a format string") \|\|	0
6120	!matchDfmtNfmt(Dfmt, Nfmt, Str, Loc))	0
6121	return ParseStatus::Failure;	0
6122	if (Dfmt == DFMT_UNDEF)	0
6123	return Error(Loc, "duplicate numeric format");	0
6124	if (Nfmt == NFMT_UNDEF)	0
6125	return Error(Loc, "duplicate data format");	0
6126	}	----
6127		----
6128	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	0
6129	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	0
6130		----
6131	if (isGFX10Plus()) {	0
6132	auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt, getSTI());	0
6133	if (Ufmt == UFMT_UNDEF)	0
6134	return Error(FormatLoc, "unsupported format");	0
6135	Format = Ufmt;	0
6136	} else {	----
6137	Format = encodeDfmtNfmt(Dfmt, Nfmt);	0
6138	}	----
6139		----
6140	return ParseStatus::Success;	0
6141	}	----
6142		----
6143	ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,	0
6144	SMLoc Loc,	----
6145	int64_t &Format) {	----
6146	using namespace llvm::AMDGPU::MTBUFFormat;	----
6147		----
6148	auto Id = getUnifiedFormat(FormatStr, getSTI());	0
6149	if (Id == UFMT_UNDEF)	0
6150	return ParseStatus::NoMatch;	0
6151		----
6152	if (!isGFX10Plus())	0
6153	return Error(Loc, "unified format is not supported on this GPU");	0
6154		----
6155	Format = Id;	0
6156	return ParseStatus::Success;	0
6157	}	----
6158		----
6159	ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {	0
6160	using namespace llvm::AMDGPU::MTBUFFormat;	----
6161	SMLoc Loc = getLoc();	0
6162		----
6163	if (!parseExpr(Format))	0
6164	return ParseStatus::Failure;	0
6165	if (!isValidFormatEncoding(Format, getSTI()))	0
6166	return Error(Loc, "out of range format");	0
6167		----
6168	return ParseStatus::Success;	0
6169	}	----
6170		----
6171	ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {	0
6172	using namespace llvm::AMDGPU::MTBUFFormat;	----
6173		----
6174	if (!trySkipId("format", AsmToken::Colon))	0
6175	return ParseStatus::NoMatch;	0
6176		----
6177	if (trySkipToken(AsmToken::LBrac)) {	0
6178	StringRef FormatStr;	0
6179	SMLoc Loc = getLoc();	0
6180	if (!parseId(FormatStr, "expected a format string"))	0
6181	return ParseStatus::Failure;	0
6182		----
6183	auto Res = parseSymbolicUnifiedFormat(FormatStr, Loc, Format);	0
6184	if (Res.isNoMatch())	0
6185	Res = parseSymbolicSplitFormat(FormatStr, Loc, Format);	0
6186	if (!Res.isSuccess())	0
6187	return Res;	0
6188		----
6189	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
6190	return ParseStatus::Failure;	0
6191		----
6192	return ParseStatus::Success;	0
6193	}	----
6194		----
6195	return parseNumericFormat(Format);	0
6196	}	----
6197		----
6198	ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {	0
6199	using namespace llvm::AMDGPU::MTBUFFormat;	----
6200		----
6201	int64_t Format = getDefaultFormatEncoding(getSTI());	0
6202	ParseStatus Res;	0
6203	SMLoc Loc = getLoc();	0
6204		----
6205	// Parse legacy format syntax.	----
6206	Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format);	0
6207	if (Res.isFailure())	0
6208	return Res;	0
6209		----
6210	bool FormatFound = Res.isSuccess();	0
6211		----
6212	Operands.push_back(	0
6213	AMDGPUOperand::CreateImm(this, Format, Loc, AMDGPUOperand::ImmTyFORMAT));	0
6214		----
6215	if (FormatFound)	0
6216	trySkipToken(AsmToken::Comma);	0
6217		----
6218	if (isToken(AsmToken::EndOfStatement)) {	0
6219	// We are expecting an soffset operand,	----
6220	// but let matcher handle the error.	----
6221	return ParseStatus::Success;	0
6222	}	----
6223		----
6224	// Parse soffset.	----
6225	Res = parseRegOrImm(Operands);	0
6226	if (!Res.isSuccess())	0
6227	return Res;	0
6228		----
6229	trySkipToken(AsmToken::Comma);	0
6230		----
6231	if (!FormatFound) {	0
6232	Res = parseSymbolicOrNumericFormat(Format);	0
6233	if (Res.isFailure())	0
6234	return Res;	0
6235	if (Res.isSuccess()) {	0
6236	auto Size = Operands.size();	0
6237	AMDGPUOperand &Op = static_cast(*Operands[Size - 2]);	0
6238	assert(Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyFORMAT);	0
6239	Op.setImm(Format);	0
6240	}	----
6241	return ParseStatus::Success;	0
6242	}	----
6243		----
6244	if (isId("format") && peekToken().is(AsmToken::Colon))	0
6245	return Error(getLoc(), "duplicate format");	0
6246	return ParseStatus::Success;	0
6247	}	----
6248		----
6249	ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {	0
6250	ParseStatus Res =	----
6251	parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);	0
6252	if (Res.isNoMatch()) {	0
6253	Res = parseIntWithPrefix("inst_offset", Operands,	0
6254	AMDGPUOperand::ImmTyInstOffset);	----
6255	}	----
6256	return Res;	0
6257	}	----
6258		----
6259	ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {	0
6260	ParseStatus Res =	----
6261	parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);	0
6262	if (Res.isNoMatch())	0
6263	Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);	0
6264	return Res;	0
6265	}	----
6266		----
6267	ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {	0
6268	ParseStatus Res =	----
6269	parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);	0
6270	if (Res.isNoMatch()) {	0
6271	Res =	----
6272	parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);	0
6273	}	----
6274	return Res;	0
6275	}	----
6276		----
6277	//===----------------------------------------------------------------------===//	----
6278	// Exp	----
6279	//===----------------------------------------------------------------------===//	----
6280		----
6281	void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {	0
6282	OptionalImmIndexMap OptionalIdx;	0
6283		----
6284	unsigned OperandIdx[4];	----
6285	unsigned EnMask = 0;	0
6286	int SrcIdx = 0;	0
6287		----
6288	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
6289	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
6290		----
6291	// Add the register arguments	----
6292	if (Op.isReg()) {	0
6293	assert(SrcIdx < 4);	0
6294	OperandIdx[SrcIdx] = Inst.size();	0
6295	Op.addRegOperands(Inst, 1);	0
6296	++SrcIdx;	0
6297	continue;	0
6298	}	----
6299		----
6300	if (Op.isOff()) {	0
6301	assert(SrcIdx < 4);	0
6302	OperandIdx[SrcIdx] = Inst.size();	0
6303	Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));	0
6304	++SrcIdx;	0
6305	continue;	0
6306	}	----
6307		----
6308	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {	0
6309	Op.addImmOperands(Inst, 1);	0
6310	continue;	0
6311	}	----
6312		----
6313	if (Op.isToken() && (Op.getToken() == "done" \|\| Op.getToken() == "row_en"))	0
6314	continue;	0
6315		----
6316	// Handle optional arguments	----
6317	OptionalIdx[Op.getImmTy()] = i;	0
6318	}	----
6319		----
6320	assert(SrcIdx == 4);	0
6321		----
6322	bool Compr = false;	0
6323	if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {	0
6324	Compr = true;	0
6325	Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);	0
6326	Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);	0
6327	Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);	0
6328	}	----
6329		----
6330	for (auto i = 0; i < SrcIdx; ++i) {	0
6331	if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {	0
6332	EnMask \|= Compr? (0x3 << i * 2) : (0x1 << i);	0
6333	}	----
6334	}	----
6335		----
6336	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);	0
6337	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);	0
6338		----
6339	Inst.addOperand(MCOperand::createImm(EnMask));	0
6340	}	0
6341		----
6342	//===----------------------------------------------------------------------===//	----
6343	// s_waitcnt	----
6344	//===----------------------------------------------------------------------===//	----
6345		----
6346	static bool	----
6347	encodeCnt(	0
6348	const AMDGPU::IsaVersion ISA,	----
6349	int64_t &IntVal,	----
6350	int64_t CntVal,	----
6351	bool Saturate,	----
6352	unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned),	----
6353	unsigned (*decode)(const IsaVersion &Version, unsigned))	----
6354	{	----
6355	bool Failed = false;	0
6356		----
6357	IntVal = encode(ISA, IntVal, CntVal);	0
6358	if (CntVal != decode(ISA, IntVal)) {	0
6359	if (Saturate) {	0
6360	IntVal = encode(ISA, IntVal, -1);	0
6361	} else {	----
6362	Failed = true;	0
6363	}	----
6364	}	----
6365	return Failed;	0
6366	}	----
6367		----
6368	bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {	0
6369		----
6370	SMLoc CntLoc = getLoc();	0
6371	StringRef CntName = getTokenStr();	0
6372		----
6373	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	0
6374	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0
6375	return false;	0
6376		----
6377	int64_t CntVal;	----
6378	SMLoc ValLoc = getLoc();	0
6379	if (!parseExpr(CntVal))	0
6380	return false;	0
6381		----
6382	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
6383		----
6384	bool Failed = true;	0
6385	bool Sat = CntName.endswith("_sat");	0
6386		----
6387	if (CntName == "vmcnt" \|\| CntName == "vmcnt_sat") {	0
6388	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeVmcnt, decodeVmcnt);	0
6389	} else if (CntName == "expcnt" \|\| CntName == "expcnt_sat") {	0
6390	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeExpcnt, decodeExpcnt);	0
6391	} else if (CntName == "lgkmcnt" \|\| CntName == "lgkmcnt_sat") {	0
6392	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeLgkmcnt, decodeLgkmcnt);	0
6393	} else {	----
6394	Error(CntLoc, "invalid counter name " + CntName);	0
6395	return false;	0
6396	}	----
6397		----
6398	if (Failed) {	0
6399	Error(ValLoc, "too large value for " + CntName);	0
6400	return false;	0
6401	}	----
6402		----
6403	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	0
6404	return false;	0
6405		----
6406	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	0
6407	if (isToken(AsmToken::EndOfStatement)) {	0
6408	Error(getLoc(), "expected a counter name");	0
6409	return false;	0
6410	}	----
6411	}	----
6412		----
6413	return true;	0
6414	}	----
6415		----
6416	ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {	0
6417	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
6418	int64_t Waitcnt = getWaitcntBitMask(ISA);	0
6419	SMLoc S = getLoc();	0
6420		----
6421	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0
6422	while (!isToken(AsmToken::EndOfStatement)) {	0
6423	if (!parseCnt(Waitcnt))	0
6424	return ParseStatus::Failure;	0
6425	}	----
6426	} else {	----
6427	if (!parseExpr(Waitcnt))	0
6428	return ParseStatus::Failure;	0
6429	}	----
6430		----
6431	Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));	0
6432	return ParseStatus::Success;	0
6433	}	----
6434		----
6435	bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {	0
6436	SMLoc FieldLoc = getLoc();	0
6437	StringRef FieldName = getTokenStr();	0
6438	if (!skipToken(AsmToken::Identifier, "expected a field name") \|\|	0
6439	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0
6440	return false;	0
6441		----
6442	SMLoc ValueLoc = getLoc();	0
6443	StringRef ValueName = getTokenStr();	0
6444	if (!skipToken(AsmToken::Identifier, "expected a value name") \|\|	0
6445	!skipToken(AsmToken::RParen, "expected a right parenthesis"))	0
6446	return false;	0
6447		----
6448	unsigned Shift;	----
6449	if (FieldName == "instid0") {	0
6450	Shift = 0;	0
6451	} else if (FieldName == "instskip") {	0
6452	Shift = 4;	0
6453	} else if (FieldName == "instid1") {	0
6454	Shift = 7;	0
6455	} else {	----
6456	Error(FieldLoc, "invalid field name " + FieldName);	0
6457	return false;	0
6458	}	----
6459		----
6460	int Value;	----
6461	if (Shift == 4) {	0
6462	// Parse values for instskip.	----
6463	Value = StringSwitch(ValueName)	0
6464	.Case("SAME", 0)	0
6465	.Case("NEXT", 1)	0
6466	.Case("SKIP_1", 2)	0
6467	.Case("SKIP_2", 3)	0
6468	.Case("SKIP_3", 4)	0
6469	.Case("SKIP_4", 5)	0
6470	.Default(-1);	0
6471	} else {	----
6472	// Parse values for instid0 and instid1.	----
6473	Value = StringSwitch(ValueName)	0
6474	.Case("NO_DEP", 0)	0
6475	.Case("VALU_DEP_1", 1)	0
6476	.Case("VALU_DEP_2", 2)	0
6477	.Case("VALU_DEP_3", 3)	0
6478	.Case("VALU_DEP_4", 4)	0
6479	.Case("TRANS32_DEP_1", 5)	0
6480	.Case("TRANS32_DEP_2", 6)	0
6481	.Case("TRANS32_DEP_3", 7)	0
6482	.Case("FMA_ACCUM_CYCLE_1", 8)	0
6483	.Case("SALU_CYCLE_1", 9)	0
6484	.Case("SALU_CYCLE_2", 10)	0
6485	.Case("SALU_CYCLE_3", 11)	0
6486	.Default(-1);	0
6487	}	----
6488	if (Value < 0) {	0
6489	Error(ValueLoc, "invalid value name " + ValueName);	0
6490	return false;	0
6491	}	----
6492		----
6493	Delay \|= Value << Shift;	0
6494	return true;	0
6495	}	----
6496		----
6497	ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {	0
6498	int64_t Delay = 0;	0
6499	SMLoc S = getLoc();	0
6500		----
6501	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0
6502	do {	----
6503	if (!parseDelay(Delay))	0
6504	return ParseStatus::Failure;	0
6505	} while (trySkipToken(AsmToken::Pipe));	0
6506	} else {	----
6507	if (!parseExpr(Delay))	0
6508	return ParseStatus::Failure;	0
6509	}	----
6510		----
6511	Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));	0
6512	return ParseStatus::Success;	0
6513	}	----
6514		----
6515	bool	----
6516	AMDGPUOperand::isSWaitCnt() const {	0
6517	return isImm();	0
6518	}	----
6519		----
6520	bool AMDGPUOperand::isSDelayALU() const { return isImm(); }	0
6521		----
6522	//===----------------------------------------------------------------------===//	----
6523	// DepCtr	----
6524	//===----------------------------------------------------------------------===//	----
6525		----
6526	void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,	0
6527	StringRef DepCtrName) {	----
6528	switch (ErrorId) {	0
6529	case OPR_ID_UNKNOWN:	0
6530	Error(Loc, Twine("invalid counter name ", DepCtrName));	0
6531	return;	0
6532	case OPR_ID_UNSUPPORTED:	0
6533	Error(Loc, Twine(DepCtrName, " is not supported on this GPU"));	0
6534	return;	0
6535	case OPR_ID_DUPLICATE:	0
6536	Error(Loc, Twine("duplicate counter name ", DepCtrName));	0
6537	return;	0
6538	case OPR_VAL_INVALID:	0
6539	Error(Loc, Twine("invalid value for ", DepCtrName));	0
6540	return;	0
6541	default:	0
6542	assert(false);	0
6543	}	----
6544	}	----
6545		----
6546	bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {	0
6547		----
6548	using namespace llvm::AMDGPU::DepCtr;	----
6549		----
6550	SMLoc DepCtrLoc = getLoc();	0
6551	StringRef DepCtrName = getTokenStr();	0
6552		----
6553	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	0
6554	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0
6555	return false;	0
6556		----
6557	int64_t ExprVal;	----
6558	if (!parseExpr(ExprVal))	0
6559	return false;	0
6560		----
6561	unsigned PrevOprMask = UsedOprMask;	0
6562	int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());	0
6563		----
6564	if (CntVal < 0) {	0
6565	depCtrError(DepCtrLoc, CntVal, DepCtrName);	0
6566	return false;	0
6567	}	----
6568		----
6569	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	0
6570	return false;	0
6571		----
6572	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	0
6573	if (isToken(AsmToken::EndOfStatement)) {	0
6574	Error(getLoc(), "expected a counter name");	0
6575	return false;	0
6576	}	----
6577	}	----
6578		----
6579	unsigned CntValMask = PrevOprMask ^ UsedOprMask;	0
6580	DepCtr = (DepCtr & ~CntValMask) \| CntVal;	0
6581	return true;	0
6582	}	----
6583		----
6584	ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {	0
6585	using namespace llvm::AMDGPU::DepCtr;	----
6586		----
6587	int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());	0
6588	SMLoc Loc = getLoc();	0
6589		----
6590	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0
6591	unsigned UsedOprMask = 0;	0
6592	while (!isToken(AsmToken::EndOfStatement)) {	0
6593	if (!parseDepCtr(DepCtr, UsedOprMask))	0
6594	return ParseStatus::Failure;	0
6595	}	----
6596	} else {	----
6597	if (!parseExpr(DepCtr))	0
6598	return ParseStatus::Failure;	0
6599	}	----
6600		----
6601	Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));	0
6602	return ParseStatus::Success;	0
6603	}	----
6604		----
6605	bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }	0
6606		----
6607	//===----------------------------------------------------------------------===//	----
6608	// hwreg	----
6609	//===----------------------------------------------------------------------===//	----
6610		----
6611	bool	----
6612	AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,	0
6613	OperandInfoTy &Offset,	----
6614	OperandInfoTy &Width) {	----
6615	using namespace llvm::AMDGPU::Hwreg;	----
6616		----
6617	// The register may be specified by name or using a numeric code	----
6618	HwReg.Loc = getLoc();	0
6619	if (isToken(AsmToken::Identifier) &&	0
6620	(HwReg.Id = getHwregId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	0
6621	HwReg.IsSymbolic = true;	0
6622	lex(); // skip register name	0
6623	} else if (!parseExpr(HwReg.Id, "a register name")) {	0
6624	return false;	0
6625	}	----
6626		----
6627	if (trySkipToken(AsmToken::RParen))	0
6628	return true;	0
6629		----
6630	// parse optional params	----
6631	if (!skipToken(AsmToken::Comma, "expected a comma or a closing parenthesis"))	0
6632	return false;	0
6633		----
6634	Offset.Loc = getLoc();	0
6635	if (!parseExpr(Offset.Id))	0
6636	return false;	0
6637		----
6638	if (!skipToken(AsmToken::Comma, "expected a comma"))	0
6639	return false;	0
6640		----
6641	Width.Loc = getLoc();	0
6642	return parseExpr(Width.Id) &&	0
6643	skipToken(AsmToken::RParen, "expected a closing parenthesis");	0
6644	}	----
6645		----
6646	bool	----
6647	AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,	0
6648	const OperandInfoTy &Offset,	----
6649	const OperandInfoTy &Width) {	----
6650		----
6651	using namespace llvm::AMDGPU::Hwreg;	----
6652		----
6653	if (HwReg.IsSymbolic) {	0
6654	if (HwReg.Id == OPR_ID_UNSUPPORTED) {	0
6655	Error(HwReg.Loc,	0
6656	"specified hardware register is not supported on this GPU");	----
6657	return false;	0
6658	}	----
6659	} else {	----
6660	if (!isValidHwreg(HwReg.Id)) {	0
6661	Error(HwReg.Loc,	0
6662	"invalid code of hardware register: only 6-bit values are legal");	----
6663	return false;	0
6664	}	----
6665	}	----
6666	if (!isValidHwregOffset(Offset.Id)) {	0
6667	Error(Offset.Loc, "invalid bit offset: only 5-bit values are legal");	0
6668	return false;	0
6669	}	----
6670	if (!isValidHwregWidth(Width.Id)) {	0
6671	Error(Width.Loc,	0
6672	"invalid bitfield width: only values from 1 to 32 are legal");	----
6673	return false;	0
6674	}	----
6675	return true;	0
6676	}	----
6677		----
6678	ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {	0
6679	using namespace llvm::AMDGPU::Hwreg;	----
6680		----
6681	int64_t ImmVal = 0;	0
6682	SMLoc Loc = getLoc();	0
6683		----
6684	if (trySkipId("hwreg", AsmToken::LParen)) {	0
6685	OperandInfoTy HwReg(OPR_ID_UNKNOWN);	0
6686	OperandInfoTy Offset(OFFSET_DEFAULT_);	0
6687	OperandInfoTy Width(WIDTH_DEFAULT_);	0
6688	if (parseHwregBody(HwReg, Offset, Width) &&	0
6689	validateHwreg(HwReg, Offset, Width)) {	0
6690	ImmVal = encodeHwreg(HwReg.Id, Offset.Id, Width.Id);	0
6691	} else {	----
6692	return ParseStatus::Failure;	0
6693	}	----
6694	} else if (parseExpr(ImmVal, "a hwreg macro")) {	0
6695	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	0
6696	return Error(Loc, "invalid immediate: only 16-bit values are legal");	0
6697	} else {	----
6698	return ParseStatus::Failure;	0
6699	}	----
6700		----
6701	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg));	0
6702	return ParseStatus::Success;	0
6703	}	----
6704		----
6705	bool AMDGPUOperand::isHwreg() const {	0
6706	return isImmTy(ImmTyHwreg);	0
6707	}	----
6708		----
6709	//===----------------------------------------------------------------------===//	----
6710	// sendmsg	----
6711	//===----------------------------------------------------------------------===//	----
6712		----
6713	bool	----
6714	AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,	0
6715	OperandInfoTy &Op,	----
6716	OperandInfoTy &Stream) {	----
6717	using namespace llvm::AMDGPU::SendMsg;	----
6718		----
6719	Msg.Loc = getLoc();	0
6720	if (isToken(AsmToken::Identifier) &&	0
6721	(Msg.Id = getMsgId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	0
6722	Msg.IsSymbolic = true;	0
6723	lex(); // skip message name	0
6724	} else if (!parseExpr(Msg.Id, "a message name")) {	0
6725	return false;	0
6726	}	----
6727		----
6728	if (trySkipToken(AsmToken::Comma)) {	0
6729	Op.IsDefined = true;	0
6730	Op.Loc = getLoc();	0
6731	if (isToken(AsmToken::Identifier) &&	0
6732	(Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {	0
6733	lex(); // skip operation name	0
6734	} else if (!parseExpr(Op.Id, "an operation name")) {	0
6735	return false;	0
6736	}	----
6737		----
6738	if (trySkipToken(AsmToken::Comma)) {	0
6739	Stream.IsDefined = true;	0
6740	Stream.Loc = getLoc();	0
6741	if (!parseExpr(Stream.Id))	0
6742	return false;	0
6743	}	----
6744	}	----
6745		----
6746	return skipToken(AsmToken::RParen, "expected a closing parenthesis");	0
6747	}	----
6748		----
6749	bool	----
6750	AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,	0
6751	const OperandInfoTy &Op,	----
6752	const OperandInfoTy &Stream) {	----
6753	using namespace llvm::AMDGPU::SendMsg;	----
6754		----
6755	// Validation strictness depends on whether message is specified	----
6756	// in a symbolic or in a numeric form. In the latter case	----
6757	// only encoding possibility is checked.	----
6758	bool Strict = Msg.IsSymbolic;	0
6759		----
6760	if (Strict) {	0
6761	if (Msg.Id == OPR_ID_UNSUPPORTED) {	0
6762	Error(Msg.Loc, "specified message id is not supported on this GPU");	0
6763	return false;	0
6764	}	----
6765	} else {	----
6766	if (!isValidMsgId(Msg.Id, getSTI())) {	0
6767	Error(Msg.Loc, "invalid message id");	0
6768	return false;	0
6769	}	----
6770	}	----
6771	if (Strict && (msgRequiresOp(Msg.Id, getSTI()) != Op.IsDefined)) {	0
6772	if (Op.IsDefined) {	0
6773	Error(Op.Loc, "message does not support operations");	0
6774	} else {	----
6775	Error(Msg.Loc, "missing message operation");	0
6776	}	----
6777	return false;	0
6778	}	----
6779	if (!isValidMsgOp(Msg.Id, Op.Id, getSTI(), Strict)) {	0
6780	Error(Op.Loc, "invalid operation id");	0
6781	return false;	0
6782	}	----
6783	if (Strict && !msgSupportsStream(Msg.Id, Op.Id, getSTI()) &&	0
6784	Stream.IsDefined) {	0
6785	Error(Stream.Loc, "message operation does not support streams");	0
6786	return false;	0
6787	}	----
6788	if (!isValidMsgStream(Msg.Id, Op.Id, Stream.Id, getSTI(), Strict)) {	0
6789	Error(Stream.Loc, "invalid message stream id");	0
6790	return false;	0
6791	}	----
6792	return true;	0
6793	}	----
6794		----
6795	ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {	0
6796	using namespace llvm::AMDGPU::SendMsg;	----
6797		----
6798	int64_t ImmVal = 0;	0
6799	SMLoc Loc = getLoc();	0
6800		----
6801	if (trySkipId("sendmsg", AsmToken::LParen)) {	0
6802	OperandInfoTy Msg(OPR_ID_UNKNOWN);	0
6803	OperandInfoTy Op(OP_NONE_);	0
6804	OperandInfoTy Stream(STREAM_ID_NONE_);	0
6805	if (parseSendMsgBody(Msg, Op, Stream) &&	0
6806	validateSendMsg(Msg, Op, Stream)) {	0
6807	ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id);	0
6808	} else {	----
6809	return ParseStatus::Failure;	0
6810	}	----
6811	} else if (parseExpr(ImmVal, "a sendmsg macro")) {	0
6812	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	0
6813	return Error(Loc, "invalid immediate: only 16-bit values are legal");	0
6814	} else {	----
6815	return ParseStatus::Failure;	0
6816	}	----
6817		----
6818	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));	0
6819	return ParseStatus::Success;	0
6820	}	----
6821		----
6822	bool AMDGPUOperand::isSendMsg() const {	0
6823	return isImmTy(ImmTySendMsg);	0
6824	}	----
6825		----
6826	//===----------------------------------------------------------------------===//	----
6827	// v_interp	----
6828	//===----------------------------------------------------------------------===//	----
6829		----
6830	ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {	0
6831	StringRef Str;	0
6832	SMLoc S = getLoc();	0
6833		----
6834	if (!parseId(Str))	0
6835	return ParseStatus::NoMatch;	0
6836		----
6837	int Slot = StringSwitch(Str)	0
6838	.Case("p10", 0)	0
6839	.Case("p20", 1)	0
6840	.Case("p0", 2)	0
6841	.Default(-1);	0
6842		----
6843	if (Slot == -1)	0
6844	return Error(S, "invalid interpolation slot");	0
6845		----
6846	Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,	0
6847	AMDGPUOperand::ImmTyInterpSlot));	----
6848	return ParseStatus::Success;	0
6849	}	----
6850		----
6851	ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {	0
6852	StringRef Str;	0
6853	SMLoc S = getLoc();	0
6854		----
6855	if (!parseId(Str))	0
6856	return ParseStatus::NoMatch;	0
6857		----
6858	if (!Str.startswith("attr"))	0
6859	return Error(S, "invalid interpolation attribute");	0
6860		----
6861	StringRef Chan = Str.take_back(2);	0
6862	int AttrChan = StringSwitch(Chan)	0
6863	.Case(".x", 0)	0
6864	.Case(".y", 1)	0
6865	.Case(".z", 2)	0
6866	.Case(".w", 3)	0
6867	.Default(-1);	0
6868	if (AttrChan == -1)	0
6869	return Error(S, "invalid or missing interpolation attribute channel");	0
6870		----
6871	Str = Str.drop_back(2).drop_front(4);	0
6872		----
6873	uint8_t Attr;	----
6874	if (Str.getAsInteger(10, Attr))	0
6875	return Error(S, "invalid or missing interpolation attribute number");	0
6876		----
6877	if (Attr > 32)	0
6878	return Error(S, "out of bounds interpolation attribute number");	0
6879		----
6880	SMLoc SChan = SMLoc::getFromPointer(Chan.data());	0
6881		----
6882	Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,	0
6883	AMDGPUOperand::ImmTyInterpAttr));	----
6884	Operands.push_back(AMDGPUOperand::CreateImm(	0
6885	this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));	----
6886	return ParseStatus::Success;	0
6887	}	----
6888		----
6889	//===----------------------------------------------------------------------===//	----
6890	// exp	----
6891	//===----------------------------------------------------------------------===//	----
6892		----
6893	ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {	0
6894	using namespace llvm::AMDGPU::Exp;	----
6895		----
6896	StringRef Str;	0
6897	SMLoc S = getLoc();	0
6898		----
6899	if (!parseId(Str))	0
6900	return ParseStatus::NoMatch;	0
6901		----
6902	unsigned Id = getTgtId(Str);	0
6903	if (Id == ET_INVALID \|\| !isSupportedTgtId(Id, getSTI()))	0
6904	return Error(S, (Id == ET_INVALID)	0
6905	? "invalid exp target"	----
6906	: "exp target is not supported on this GPU");	0
6907		----
6908	Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,	0
6909	AMDGPUOperand::ImmTyExpTgt));	----
6910	return ParseStatus::Success;	0
6911	}	----
6912		----
6913	//===----------------------------------------------------------------------===//	----
6914	// parser helpers	----
6915	//===----------------------------------------------------------------------===//	----
6916		----
6917	bool	----
6918	AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {	0
6919	return Token.is(AsmToken::Identifier) && Token.getString() == Id;	0
6920	}	----
6921		----
6922	bool	----
6923	AMDGPUAsmParser::isId(const StringRef Id) const {	0
6924	return isId(getToken(), Id);	0
6925	}	----
6926		----
6927	bool	----
6928	AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {	0
6929	return getTokenKind() == Kind;	0
6930	}	----
6931		----
6932	StringRef AMDGPUAsmParser::getId() const {	0
6933	return isToken(AsmToken::Identifier) ? getTokenStr() : StringRef();	0
6934	}	----
6935		----
6936	bool	----
6937	AMDGPUAsmParser::trySkipId(const StringRef Id) {	0
6938	if (isId(Id)) {	0
6939	lex();	0
6940	return true;	0
6941	}	----
6942	return false;	0
6943	}	----
6944		----
6945	bool	----
6946	AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {	0
6947	if (isToken(AsmToken::Identifier)) {	0
6948	StringRef Tok = getTokenStr();	0
6949	if (Tok.startswith(Pref) && Tok.drop_front(Pref.size()) == Id) {	0
6950	lex();	0
6951	return true;	0
6952	}	----
6953	}	----
6954	return false;	0
6955	}	----
6956		----
6957	bool	----
6958	AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {	0
6959	if (isId(Id) && peekToken().is(Kind)) {	0
6960	lex();	0
6961	lex();	0
6962	return true;	0
6963	}	----
6964	return false;	0
6965	}	----
6966		----
6967	bool	----
6968	AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {	0
6969	if (isToken(Kind)) {	0
6970	lex();	0
6971	return true;	0
6972	}	----
6973	return false;	0
6974	}	----
6975		----
6976	bool	----
6977	AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,	0
6978	const StringRef ErrMsg) {	----
6979	if (!trySkipToken(Kind)) {	0
6980	Error(getLoc(), ErrMsg);	0
6981	return false;	0
6982	}	----
6983	return true;	0
6984	}	----
6985		----
6986	bool	----
6987	AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {	0
6988	SMLoc S = getLoc();	0
6989		----
6990	const MCExpr *Expr;	----
6991	if (Parser.parseExpression(Expr))	0
6992	return false;	0
6993		----
6994	if (Expr->evaluateAsAbsolute(Imm))	0
6995	return true;	0
6996		----
6997	if (Expected.empty()) {	0
6998	Error(S, "expected absolute expression");	0
6999	} else {	----
7000	Error(S, Twine("expected ", Expected) +	0
7001	Twine(" or an absolute expression"));	0
7002	}	----
7003	return false;	0
7004	}	----
7005		----
7006	bool	----
7007	AMDGPUAsmParser::parseExpr(OperandVector &Operands) {	0
7008	SMLoc S = getLoc();	0
7009		----
7010	const MCExpr *Expr;	----
7011	if (Parser.parseExpression(Expr))	0
7012	return false;	0
7013		----
7014	int64_t IntVal;	----
7015	if (Expr->evaluateAsAbsolute(IntVal)) {	0
7016	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	0
7017	} else {	----
7018	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	0
7019	}	----
7020	return true;	0
7021	}	----
7022		----
7023	bool	----
7024	AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {	0
7025	if (isToken(AsmToken::String)) {	0
7026	Val = getToken().getStringContents();	0
7027	lex();	0
7028	return true;	0
7029	} else {	----
7030	Error(getLoc(), ErrMsg);	0
7031	return false;	0
7032	}	----
7033	}	----
7034		----
7035	bool	----
7036	AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {	0
7037	if (isToken(AsmToken::Identifier)) {	0
7038	Val = getTokenStr();	0
7039	lex();	0
7040	return true;	0
7041	} else {	----
7042	if (!ErrMsg.empty())	0
7043	Error(getLoc(), ErrMsg);	0
7044	return false;	0
7045	}	----
7046	}	----
7047		----
7048	AsmToken	----
7049	AMDGPUAsmParser::getToken() const {	0
7050	return Parser.getTok();	0
7051	}	----
7052		----
7053	AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {	0
7054	return isToken(AsmToken::EndOfStatement)	0
7055	? getToken()	----
7056	: getLexer().peekTok(ShouldSkipSpace);	0
7057	}	----
7058		----
7059	void	----
7060	AMDGPUAsmParser::peekTokens(MutableArrayRef Tokens) {	0
7061	auto TokCount = getLexer().peekTokens(Tokens);	0
7062		----
7063	for (auto Idx = TokCount; Idx < Tokens.size(); ++Idx)	0
7064	Tokens[Idx] = AsmToken(AsmToken::Error, "");	0
7065	}	0
7066		----
7067	AsmToken::TokenKind	----
7068	AMDGPUAsmParser::getTokenKind() const {	0
7069	return getLexer().getKind();	0
7070	}	----
7071		----
7072	SMLoc	----
7073	AMDGPUAsmParser::getLoc() const {	0
7074	return getToken().getLoc();	0
7075	}	----
7076		----
7077	StringRef	----
7078	AMDGPUAsmParser::getTokenStr() const {	0
7079	return getToken().getString();	0
7080	}	----
7081		----
7082	void	----
7083	AMDGPUAsmParser::lex() {	0
7084	Parser.Lex();	0
7085	}	0
7086		----
7087	SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {	0
7088	return ((AMDGPUOperand &)*Operands[0]).getStartLoc();	0
7089	}	----
7090		----
7091	SMLoc	----
7092	AMDGPUAsmParser::getOperandLoc(std::function Test,	0
7093	const OperandVector &Operands) const {	----
7094	for (unsigned i = Operands.size() - 1; i > 0; --i) {	0
7095	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7096	if (Test(Op))	0
7097	return Op.getStartLoc();	0
7098	}	----
7099	return getInstLoc(Operands);	0
7100	}	----
7101		----
7102	SMLoc	----
7103	AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,	0
7104	const OperandVector &Operands) const {	----
7105	auto Test = [=](const AMDGPUOperand& Op) { return Op.isImmTy(Type); };	0
7106	return getOperandLoc(Test, Operands);	0
7107	}	----
7108		----
7109	SMLoc	----
7110	AMDGPUAsmParser::getRegLoc(unsigned Reg,	0
7111	const OperandVector &Operands) const {	----
7112	auto Test = [=](const AMDGPUOperand& Op) {	0
7113	return Op.isRegKind() && Op.getReg() == Reg;	0
7114	};	0
7115	return getOperandLoc(Test, Operands);	0
7116	}	----
7117		----
7118	SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,	0
7119	bool SearchMandatoryLiterals) const {	----
7120	auto Test = [](const AMDGPUOperand& Op) {	0
7121	return Op.IsImmKindLiteral() \|\| Op.isExpr();	0
7122	};	----
7123	SMLoc Loc = getOperandLoc(Test, Operands);	0
7124	if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))	0
7125	Loc = getMandatoryLitLoc(Operands);	0
7126	return Loc;	0
7127	}	----
7128		----
7129	SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {	0
7130	auto Test = [](const AMDGPUOperand &Op) {	0
7131	return Op.IsImmKindMandatoryLiteral();	0
7132	};	----
7133	return getOperandLoc(Test, Operands);	0
7134	}	----
7135		----
7136	SMLoc	----
7137	AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {	0
7138	auto Test = [](const AMDGPUOperand& Op) {	0
7139	return Op.isImmKindConst();	0
7140	};	----
7141	return getOperandLoc(Test, Operands);	0
7142	}	----
7143		----
7144	//===----------------------------------------------------------------------===//	----
7145	// swizzle	----
7146	//===----------------------------------------------------------------------===//	----
7147		----
7148	LLVM_READNONE	----
7149	static unsigned	----
7150	encodeBitmaskPerm(const unsigned AndMask,	0
7151	const unsigned OrMask,	----
7152	const unsigned XorMask) {	----
7153	using namespace llvm::AMDGPU::Swizzle;	----
7154		----
7155	return BITMASK_PERM_ENC \|	----
7156	(AndMask << BITMASK_AND_SHIFT) \|	0
7157	(OrMask << BITMASK_OR_SHIFT) \|	0
7158	(XorMask << BITMASK_XOR_SHIFT);	0
7159	}	----
7160		----
7161	bool	----
7162	AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,	0
7163	const unsigned MinVal,	----
7164	const unsigned MaxVal,	----
7165	const StringRef ErrMsg,	----
7166	SMLoc &Loc) {	----
7167	if (!skipToken(AsmToken::Comma, "expected a comma")) {	0
7168	return false;	0
7169	}	----
7170	Loc = getLoc();	0
7171	if (!parseExpr(Op)) {	0
7172	return false;	0
7173	}	----
7174	if (Op < MinVal \|\| Op > MaxVal) {	0
7175	Error(Loc, ErrMsg);	0
7176	return false;	0
7177	}	----
7178		----
7179	return true;	0
7180	}	----
7181		----
7182	bool	----
7183	AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	0
7184	const unsigned MinVal,	----
7185	const unsigned MaxVal,	----
7186	const StringRef ErrMsg) {	----
7187	SMLoc Loc;	0
7188	for (unsigned i = 0; i < OpNum; ++i) {	0
7189	if (!parseSwizzleOperand(Op[i], MinVal, MaxVal, ErrMsg, Loc))	0
7190	return false;	0
7191	}	----
7192		----
7193	return true;	0
7194	}	----
7195		----
7196	bool	----
7197	AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {	0
7198	using namespace llvm::AMDGPU::Swizzle;	----
7199		----
7200	int64_t Lane[LANE_NUM];	----
7201	if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,	0
7202	"expected a 2-bit lane id")) {	----
7203	Imm = QUAD_PERM_ENC;	0
7204	for (unsigned I = 0; I < LANE_NUM; ++I) {	0
7205	Imm \|= Lane[I] << (LANE_SHIFT * I);	0
7206	}	----
7207	return true;	0
7208	}	----
7209	return false;	0
7210	}	----
7211		----
7212	bool	----
7213	AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {	0
7214	using namespace llvm::AMDGPU::Swizzle;	----
7215		----
7216	SMLoc Loc;	0
7217	int64_t GroupSize;	----
7218	int64_t LaneIdx;	----
7219		----
7220	if (!parseSwizzleOperand(GroupSize,	0
7221	2, 32,	----
7222	"group size must be in the interval [2,32]",	----
7223	Loc)) {	----
7224	return false;	0
7225	}	----
7226	if (!isPowerOf2_64(GroupSize)) {	0
7227	Error(Loc, "group size must be a power of two");	0
7228	return false;	0
7229	}	----
7230	if (parseSwizzleOperand(LaneIdx,	0
7231	0, GroupSize - 1,	----
7232	"lane id must be in the interval [0,group size - 1]",	----
7233	Loc)) {	----
7234	Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);	0
7235	return true;	0
7236	}	----
7237	return false;	0
7238	}	----
7239		----
7240	bool	----
7241	AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {	0
7242	using namespace llvm::AMDGPU::Swizzle;	----
7243		----
7244	SMLoc Loc;	0
7245	int64_t GroupSize;	----
7246		----
7247	if (!parseSwizzleOperand(GroupSize,	0
7248	2, 32,	----
7249	"group size must be in the interval [2,32]",	----
7250	Loc)) {	----
7251	return false;	0
7252	}	----
7253	if (!isPowerOf2_64(GroupSize)) {	0
7254	Error(Loc, "group size must be a power of two");	0
7255	return false;	0
7256	}	----
7257		----
7258	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);	0
7259	return true;	0
7260	}	----
7261		----
7262	bool	----
7263	AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {	0
7264	using namespace llvm::AMDGPU::Swizzle;	----
7265		----
7266	SMLoc Loc;	0
7267	int64_t GroupSize;	----
7268		----
7269	if (!parseSwizzleOperand(GroupSize,	0
7270	1, 16,	----
7271	"group size must be in the interval [1,16]",	----
7272	Loc)) {	----
7273	return false;	0
7274	}	----
7275	if (!isPowerOf2_64(GroupSize)) {	0
7276	Error(Loc, "group size must be a power of two");	0
7277	return false;	0
7278	}	----
7279		----
7280	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize);	0
7281	return true;	0
7282	}	----
7283		----
7284	bool	----
7285	AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {	0
7286	using namespace llvm::AMDGPU::Swizzle;	----
7287		----
7288	if (!skipToken(AsmToken::Comma, "expected a comma")) {	0
7289	return false;	0
7290	}	----
7291		----
7292	StringRef Ctl;	0
7293	SMLoc StrLoc = getLoc();	0
7294	if (!parseString(Ctl)) {	0
7295	return false;	0
7296	}	----
7297	if (Ctl.size() != BITMASK_WIDTH) {	0
7298	Error(StrLoc, "expected a 5-character mask");	0
7299	return false;	0
7300	}	----
7301		----
7302	unsigned AndMask = 0;	0
7303	unsigned OrMask = 0;	0
7304	unsigned XorMask = 0;	0
7305		----
7306	for (size_t i = 0; i < Ctl.size(); ++i) {	0
7307	unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);	0
7308	switch(Ctl[i]) {	0
7309	default:	0
7310	Error(StrLoc, "invalid mask");	0
7311	return false;	0
7312	case '0':	0
7313	break;	0
7314	case '1':	0
7315	OrMask \|= Mask;	0
7316	break;	0
7317	case 'p':	0
7318	AndMask \|= Mask;	0
7319	break;	0
7320	case 'i':	0
7321	AndMask \|= Mask;	0
7322	XorMask \|= Mask;	0
7323	break;	0
7324	}	----
7325	}	----
7326		----
7327	Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask);	0
7328	return true;	0
7329	}	----
7330		----
7331	bool	----
7332	AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {	0
7333		----
7334	SMLoc OffsetLoc = getLoc();	0
7335		----
7336	if (!parseExpr(Imm, "a swizzle macro")) {	0
7337	return false;	0
7338	}	----
7339	if (!isUInt<16>(Imm)) {	0
7340	Error(OffsetLoc, "expected a 16-bit offset");	0
7341	return false;	0
7342	}	----
7343	return true;	0
7344	}	----
7345		----
7346	bool	----
7347	AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {	0
7348	using namespace llvm::AMDGPU::Swizzle;	----
7349		----
7350	if (skipToken(AsmToken::LParen, "expected a left parentheses")) {	0
7351		----
7352	SMLoc ModeLoc = getLoc();	0
7353	bool Ok = false;	0
7354		----
7355	if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {	0
7356	Ok = parseSwizzleQuadPerm(Imm);	0
7357	} else if (trySkipId(IdSymbolic[ID_BITMASK_PERM])) {	0
7358	Ok = parseSwizzleBitmaskPerm(Imm);	0
7359	} else if (trySkipId(IdSymbolic[ID_BROADCAST])) {	0
7360	Ok = parseSwizzleBroadcast(Imm);	0
7361	} else if (trySkipId(IdSymbolic[ID_SWAP])) {	0
7362	Ok = parseSwizzleSwap(Imm);	0
7363	} else if (trySkipId(IdSymbolic[ID_REVERSE])) {	0
7364	Ok = parseSwizzleReverse(Imm);	0
7365	} else {	----
7366	Error(ModeLoc, "expected a swizzle mode");	0
7367	}	----
7368		----
7369	return Ok && skipToken(AsmToken::RParen, "expected a closing parentheses");	0
7370	}	----
7371		----
7372	return false;	0
7373	}	----
7374		----
7375	ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {	0
7376	SMLoc S = getLoc();	0
7377	int64_t Imm = 0;	0
7378		----
7379	if (trySkipId("offset")) {	0
7380		----
7381	bool Ok = false;	0
7382	if (skipToken(AsmToken::Colon, "expected a colon")) {	0
7383	if (trySkipId("swizzle")) {	0
7384	Ok = parseSwizzleMacro(Imm);	0
7385	} else {	----
7386	Ok = parseSwizzleOffset(Imm);	0
7387	}	----
7388	}	----
7389		----
7390	Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));	0
7391		----
7392	return Ok ? ParseStatus::Success : ParseStatus::Failure;	0
7393	}	----
7394	return ParseStatus::NoMatch;	0
7395	}	----
7396		----
7397	bool	----
7398	AMDGPUOperand::isSwizzle() const {	0
7399	return isImmTy(ImmTySwizzle);	0
7400	}	----
7401		----
7402	//===----------------------------------------------------------------------===//	----
7403	// VGPR Index Mode	----
7404	//===----------------------------------------------------------------------===//	----
7405		----
7406	int64_t AMDGPUAsmParser::parseGPRIdxMacro() {	0
7407		----
7408	using namespace llvm::AMDGPU::VGPRIndexMode;	----
7409		----
7410	if (trySkipToken(AsmToken::RParen)) {	0
7411	return OFF;	0
7412	}	----
7413		----
7414	int64_t Imm = 0;	0
7415		----
7416	while (true) {	----
7417	unsigned Mode = 0;	0
7418	SMLoc S = getLoc();	0
7419		----
7420	for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {	0
7421	if (trySkipId(IdSymbolic[ModeId])) {	0
7422	Mode = 1 << ModeId;	0
7423	break;	0
7424	}	----
7425	}	----
7426		----
7427	if (Mode == 0) {	0
7428	Error(S, (Imm == 0)?	0
7429	"expected a VGPR index mode or a closing parenthesis" :	----
7430	"expected a VGPR index mode");	----
7431	return UNDEF;	0
7432	}	----
7433		----
7434	if (Imm & Mode) {	0
7435	Error(S, "duplicate VGPR index mode");	0
7436	return UNDEF;	0
7437	}	----
7438	Imm \|= Mode;	0
7439		----
7440	if (trySkipToken(AsmToken::RParen))	0
7441	break;	0
7442	if (!skipToken(AsmToken::Comma,	0
7443	"expected a comma or a closing parenthesis"))	----
7444	return UNDEF;	0
7445	}	0
7446		----
7447	return Imm;	0
7448	}	----
7449		----
7450	ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {	0
7451		----
7452	using namespace llvm::AMDGPU::VGPRIndexMode;	----
7453		----
7454	int64_t Imm = 0;	0
7455	SMLoc S = getLoc();	0
7456		----
7457	if (trySkipId("gpr_idx", AsmToken::LParen)) {	0
7458	Imm = parseGPRIdxMacro();	0
7459	if (Imm == UNDEF)	0
7460	return ParseStatus::Failure;	0
7461	} else {	----
7462	if (getParser().parseAbsoluteExpression(Imm))	0
7463	return ParseStatus::Failure;	0
7464	if (Imm < 0 \|\| !isUInt<4>(Imm))	0
7465	return Error(S, "invalid immediate: only 4-bit values are legal");	0
7466	}	----
7467		----
7468	Operands.push_back(	0
7469	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode));	0
7470	return ParseStatus::Success;	0
7471	}	----
7472		----
7473	bool AMDGPUOperand::isGPRIdxMode() const {	0
7474	return isImmTy(ImmTyGprIdxMode);	0
7475	}	----
7476		----
7477	//===----------------------------------------------------------------------===//	----
7478	// sopp branch targets	----
7479	//===----------------------------------------------------------------------===//	----
7480		----
7481	ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {	0
7482		----
7483	// Make sure we are not parsing something	----
7484	// that looks like a label or an expression but is not.	----
7485	// This will improve error messages.	----
7486	if (isRegister() \|\| isModifier())	0
7487	return ParseStatus::NoMatch;	0
7488		----
7489	if (!parseExpr(Operands))	0
7490	return ParseStatus::Failure;	0
7491		----
7492	AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);	0
7493	assert(Opr.isImm() \|\| Opr.isExpr());	0
7494	SMLoc Loc = Opr.getStartLoc();	0
7495		----
7496	// Currently we do not support arbitrary expressions as branch targets.	----
7497	// Only labels and absolute expressions are accepted.	----
7498	if (Opr.isExpr() && !Opr.isSymbolRefExpr()) {	0
7499	Error(Loc, "expected an absolute expression or a label");	0
7500	} else if (Opr.isImm() && !Opr.isS16Imm()) {	0
7501	Error(Loc, "expected a 16-bit signed jump offset");	0
7502	}	----
7503		----
7504	return ParseStatus::Success;	0
7505	}	----
7506		----
7507	//===----------------------------------------------------------------------===//	----
7508	// Boolean holding registers	----
7509	//===----------------------------------------------------------------------===//	----
7510		----
7511	ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {	0
7512	return parseReg(Operands);	0
7513	}	----
7514		----
7515	//===----------------------------------------------------------------------===//	----
7516	// mubuf	----
7517	//===----------------------------------------------------------------------===//	----
7518		----
7519	void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,	0
7520	const OperandVector &Operands,	----
7521	bool IsAtomic) {	----
7522	OptionalImmIndexMap OptionalIdx;	0
7523	unsigned FirstOperandIdx = 1;	0
7524	bool IsAtomicReturn = false;	0
7525		----
7526	if (IsAtomic) {	0
7527	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	0
7528	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7529	if (!Op.isCPol())	0
7530	continue;	0
7531	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	0
7532	break;	0
7533	}	----
7534		----
7535	if (!IsAtomicReturn) {	0
7536	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	0
7537	if (NewOpc != -1)	0
7538	Inst.setOpcode(NewOpc);	0
7539	}	----
7540		----
7541	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	0
7542	SIInstrFlags::IsAtomicRet;	----
7543	}	----
7544		----
7545	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	0
7546	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7547		----
7548	// Add the register arguments	----
7549	if (Op.isReg()) {	0
7550	Op.addRegOperands(Inst, 1);	0
7551	// Insert a tied src for atomic return dst.	----
7552	// This cannot be postponed as subsequent calls to	----
7553	// addImmOperands rely on correct number of MC operands.	----
7554	if (IsAtomicReturn && i == FirstOperandIdx)	0
7555	Op.addRegOperands(Inst, 1);	0
7556	continue;	0
7557	}	----
7558		----
7559	// Handle the case where soffset is an immediate	----
7560	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	0
7561	Op.addImmOperands(Inst, 1);	0
7562	continue;	0
7563	}	----
7564		----
7565	// Handle tokens like 'offen' which are sometimes hard-coded into the	----
7566	// asm string. There are no MCInst operands for these.	----
7567	if (Op.isToken()) {	0
7568	continue;	0
7569	}	----
7570	assert(Op.isImm());	0
7571		----
7572	// Handle optional arguments	----
7573	OptionalIdx[Op.getImmTy()] = i;	0
7574	}	----
7575		----
7576	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);	0
7577	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	0
7578	}	0
7579		----
7580	//===----------------------------------------------------------------------===//	----
7581	// SMEM	----
7582	//===----------------------------------------------------------------------===//	----
7583		----
7584	void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {	0
7585	OptionalImmIndexMap OptionalIdx;	0
7586	bool IsAtomicReturn = false;	0
7587		----
7588	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
7589	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7590	if (!Op.isCPol())	0
7591	continue;	0
7592	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	0
7593	break;	0
7594	}	----
7595		----
7596	if (!IsAtomicReturn) {	0
7597	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	0
7598	if (NewOpc != -1)	0
7599	Inst.setOpcode(NewOpc);	0
7600	}	----
7601		----
7602	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	0
7603	SIInstrFlags::IsAtomicRet;	----
7604		----
7605	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
7606	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7607		----
7608	// Add the register arguments	----
7609	if (Op.isReg()) {	0
7610	Op.addRegOperands(Inst, 1);	0
7611	if (IsAtomicReturn && i == 1)	0
7612	Op.addRegOperands(Inst, 1);	0
7613	continue;	0
7614	}	----
7615		----
7616	// Handle the case where soffset is an immediate	----
7617	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	0
7618	Op.addImmOperands(Inst, 1);	0
7619	continue;	0
7620	}	----
7621		----
7622	// Handle tokens like 'offen' which are sometimes hard-coded into the	----
7623	// asm string. There are no MCInst operands for these.	----
7624	if (Op.isToken()) {	0
7625	continue;	0
7626	}	----
7627	assert(Op.isImm());	0
7628		----
7629	// Handle optional arguments	----
7630	OptionalIdx[Op.getImmTy()] = i;	0
7631	}	----
7632		----
7633	if ((int)Inst.getNumOperands() <=	0
7634	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset))	0
7635	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7636	AMDGPUOperand::ImmTySMEMOffsetMod);	----
7637	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	0
7638	}	0
7639		----
7640	//===----------------------------------------------------------------------===//	----
7641	// smrd	----
7642	//===----------------------------------------------------------------------===//	----
7643		----
7644	bool AMDGPUOperand::isSMRDOffset8() const {	0
7645	return isImmLiteral() && isUInt<8>(getImm());	0
7646	}	----
7647		----
7648	bool AMDGPUOperand::isSMEMOffset() const {	0
7649	// Offset range is checked later by validator.	----
7650	return isImmLiteral();	0
7651	}	----
7652		----
7653	bool AMDGPUOperand::isSMRDLiteralOffset() const {	0
7654	// 32-bit literals are only supported on CI and we only want to use them	----
7655	// when the offset is > 8-bits.	----
7656	return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());	0
7657	}	----
7658		----
7659	//===----------------------------------------------------------------------===//	----
7660	// vop3	----
7661	//===----------------------------------------------------------------------===//	----
7662		----
7663	static bool ConvertOmodMul(int64_t &Mul) {	0
7664	if (Mul != 1 && Mul != 2 && Mul != 4)	0
7665	return false;	0
7666		----
7667	Mul >>= 1;	0
7668	return true;	0
7669	}	----
7670		----
7671	static bool ConvertOmodDiv(int64_t &Div) {	0
7672	if (Div == 1) {	0
7673	Div = 0;	0
7674	return true;	0
7675	}	----
7676		----
7677	if (Div == 2) {	0
7678	Div = 3;	0
7679	return true;	0
7680	}	----
7681		----
7682	return false;	0
7683	}	----
7684		----
7685	// For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.	----
7686	// This is intentional and ensures compatibility with sp3.	----
7687	// See bug 35397 for details.	----
7688	bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {	0
7689	if (BoundCtrl == 0 \|\| BoundCtrl == 1) {	0
7690	if (!isGFX11Plus())	0
7691	BoundCtrl = 1;	0
7692	return true;	0
7693	}	----
7694	return false;	0
7695	}	----
7696		----
7697	void AMDGPUAsmParser::onBeginOfFile() {	0
7698	if (!getParser().getStreamer().getTargetStreamer() \|\|	0
7699	getSTI().getTargetTriple().getArch() == Triple::r600)	0
7700	return;	0
7701		----
7702	if (!getTargetStreamer().getTargetID())	0
7703	getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(),	0
7704	// TODO: Should try to check code object version from directive???	----
7705	AMDGPU::getAmdhsaCodeObjectVersion());	----
7706		----
7707	if (isHsaAbiVersion3AndAbove(&getSTI()))	0
7708	getTargetStreamer().EmitDirectiveAMDGCNTarget();	0
7709	}	----
7710		----
7711	ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {	0
7712	StringRef Name = getTokenStr();	0
7713	if (Name == "mul") {	0
7714	return parseIntWithPrefix("mul", Operands,	0
7715	AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);	0
7716	}	----
7717		----
7718	if (Name == "div") {	0
7719	return parseIntWithPrefix("div", Operands,	0
7720	AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);	0
7721	}	----
7722		----
7723	return ParseStatus::NoMatch;	0
7724	}	----
7725		----
7726	// Determines which bit DST_OP_SEL occupies in the op_sel operand according to	----
7727	// the number of src operands present, then copies that bit into src0_modifiers.	----
7728	void cvtVOP3DstOpSelOnly(MCInst &Inst) {	0
7729	int Opc = Inst.getOpcode();	0
7730	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
7731	if (OpSelIdx == -1)	0
7732	return;	0
7733		----
7734	int SrcNum;	----
7735	const int Ops[] = { AMDGPU::OpName::src0,	0
7736	AMDGPU::OpName::src1,	----
7737	AMDGPU::OpName::src2 };	----
7738	for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);	0
7739	++SrcNum)	----
7740	;	----
7741	assert(SrcNum > 0);	0
7742		----
7743	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
7744		----
7745	if ((OpSel & (1 << SrcNum)) != 0) {	0
7746	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);	0
7747	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	0
7748	Inst.getOperand(ModIdx).setImm(ModVal \| SISrcMods::DST_OP_SEL);	0
7749	}	----
7750	}	----
7751		----
7752	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,	0
7753	const OperandVector &Operands) {	----
7754	cvtVOP3P(Inst, Operands);	0
7755	cvtVOP3DstOpSelOnly(Inst);	0
7756	}	0
7757		----
7758	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	0
7759	OptionalImmIndexMap &OptionalIdx) {	----
7760	cvtVOP3P(Inst, Operands, OptionalIdx);	0
7761	cvtVOP3DstOpSelOnly(Inst);	0
7762	}	0
7763		----
7764	static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {	0
7765	return	----
7766	// 1. This operand is input modifiers	----
7767	Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS	0
7768	// 2. This is not last operand	----
7769	&& Desc.NumOperands > (OpNum + 1)	0
7770	// 3. Next operand is register class	----
7771	&& Desc.operands()[OpNum + 1].RegClass != -1	0
7772	// 4. Next register is not tied to any other operand	----
7773	&& Desc.getOperandConstraint(OpNum + 1,	0
7774	MCOI::OperandConstraint::TIED_TO) == -1;	0
7775	}	----
7776		----
7777	void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)	0
7778	{	----
7779	OptionalImmIndexMap OptionalIdx;	0
7780	unsigned Opc = Inst.getOpcode();	0
7781		----
7782	unsigned I = 1;	0
7783	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
7784	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
7785	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
7786	}	----
7787		----
7788	for (unsigned E = Operands.size(); I != E; ++I) {	0
7789	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
7790	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
7791	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
7792	} else if (Op.isInterpSlot() \|\| Op.isInterpAttr() \|\|	0
7793	Op.isInterpAttrChan()) {	0
7794	Inst.addOperand(MCOperand::createImm(Op.getImm()));	0
7795	} else if (Op.isImmModifier()) {	0
7796	OptionalIdx[Op.getImmTy()] = I;	0
7797	} else {	----
7798	llvm_unreachable("unhandled operand type");	0
7799	}	----
7800	}	----
7801		----
7802	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))	0
7803	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7804	AMDGPUOperand::ImmTyHigh);	----
7805		----
7806	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
7807	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7808	AMDGPUOperand::ImmTyClampSI);	----
7809		----
7810	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
7811	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7812	AMDGPUOperand::ImmTyOModSI);	----
7813	}	0
7814		----
7815	void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)	0
7816	{	----
7817	OptionalImmIndexMap OptionalIdx;	0
7818	unsigned Opc = Inst.getOpcode();	0
7819		----
7820	unsigned I = 1;	0
7821	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
7822	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
7823	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
7824	}	----
7825		----
7826	for (unsigned E = Operands.size(); I != E; ++I) {	0
7827	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
7828	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
7829	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
7830	} else if (Op.isImmModifier()) {	0
7831	OptionalIdx[Op.getImmTy()] = I;	0
7832	} else {	----
7833	llvm_unreachable("unhandled operand type");	0
7834	}	----
7835	}	----
7836		----
7837	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	0
7838		----
7839	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
7840	if (OpSelIdx != -1)	0
7841	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	0
7842		----
7843	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);	0
7844		----
7845	if (OpSelIdx == -1)	0
7846	return;	0
7847		----
7848	const int Ops[] = { AMDGPU::OpName::src0,	0
7849	AMDGPU::OpName::src1,	----
7850	AMDGPU::OpName::src2 };	----
7851	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	0
7852	AMDGPU::OpName::src1_modifiers,	----
7853	AMDGPU::OpName::src2_modifiers };	----
7854		----
7855	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
7856		----
7857	for (int J = 0; J < 3; ++J) {	0
7858	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	0
7859	if (OpIdx == -1)	0
7860	break;	0
7861		----
7862	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	0
7863	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	0
7864		----
7865	if ((OpSel & (1 << J)) != 0)	0
7866	ModVal \|= SISrcMods::OP_SEL_0;	0
7867	if (ModOps[J] == AMDGPU::OpName::src0_modifiers &&	0
7868	(OpSel & (1 << 3)) != 0)	0
7869	ModVal \|= SISrcMods::DST_OP_SEL;	0
7870		----
7871	Inst.getOperand(ModIdx).setImm(ModVal);	0
7872	}	----
7873	}	0
7874		----
7875	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,	0
7876	OptionalImmIndexMap &OptionalIdx) {	----
7877	unsigned Opc = Inst.getOpcode();	0
7878		----
7879	unsigned I = 1;	0
7880	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
7881	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
7882	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
7883	}	----
7884		----
7885	for (unsigned E = Operands.size(); I != E; ++I) {	0
7886	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
7887	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
7888	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
7889	} else if (Op.isImmModifier()) {	0
7890	OptionalIdx[Op.getImmTy()] = I;	0
7891	} else if (Op.isRegOrImm()) {	0
7892	Op.addRegOrImmOperands(Inst, 1);	0
7893	} else {	----
7894	llvm_unreachable("unhandled operand type");	0
7895	}	----
7896	}	----
7897		----
7898	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
7899	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7900	AMDGPUOperand::ImmTyClampSI);	----
7901		----
7902	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
7903	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7904	AMDGPUOperand::ImmTyOModSI);	----
7905		----
7906	// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):	----
7907	// it has src2 register operand that is tied to dst operand	----
7908	// we don't allow modifiers for this operand in assembler so src2_modifiers	----
7909	// should be 0.	----
7910	if (isMAC(Opc)) {	0
7911	auto it = Inst.begin();	0
7912	std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));	0
7913	it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2	0
7914	++it;	0
7915	// Copy the operand to ensure it's not invalidated when Inst grows.	----
7916	Inst.insert(it, MCOperand(Inst.getOperand(0))); // src2 = dst	0
7917	}	----
7918	}	0
7919		----
7920	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {	0
7921	OptionalImmIndexMap OptionalIdx;	0
7922	cvtVOP3(Inst, Operands, OptionalIdx);	0
7923	}	0
7924		----
7925	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	0
7926	OptionalImmIndexMap &OptIdx) {	----
7927	const int Opc = Inst.getOpcode();	0
7928	const MCInstrDesc &Desc = MII.get(Opc);	0
7929		----
7930	const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;	0
7931		----
7932	if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi \|\|	0
7933	Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) {	----
7934	Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods	0
7935	Inst.addOperand(Inst.getOperand(0));	0
7936	}	----
7937		----
7938	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {	0
7939	assert(!IsPacked);	0
7940	Inst.addOperand(Inst.getOperand(0));	0
7941	}	----
7942		----
7943	// FIXME: This is messy. Parse the modifiers as if it was a normal VOP3	----
7944	// instruction, and then figure out where to actually put the modifiers	----
7945		----
7946	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
7947	if (OpSelIdx != -1) {	0
7948	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);	0
7949	}	----
7950		----
7951	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	0
7952	if (OpSelHiIdx != -1) {	0
7953	int DefaultVal = IsPacked ? -1 : 0;	0
7954	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,	0
7955	DefaultVal);	----
7956	}	----
7957		----
7958	int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);	0
7959	if (NegLoIdx != -1) {	0
7960	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);	0
7961	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);	0
7962	}	----
7963		----
7964	const int Ops[] = { AMDGPU::OpName::src0,	0
7965	AMDGPU::OpName::src1,	----
7966	AMDGPU::OpName::src2 };	----
7967	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	0
7968	AMDGPU::OpName::src1_modifiers,	----
7969	AMDGPU::OpName::src2_modifiers };	----
7970		----
7971	unsigned OpSel = 0;	0
7972	unsigned OpSelHi = 0;	0
7973	unsigned NegLo = 0;	0
7974	unsigned NegHi = 0;	0
7975		----
7976	if (OpSelIdx != -1)	0
7977	OpSel = Inst.getOperand(OpSelIdx).getImm();	0
7978		----
7979	if (OpSelHiIdx != -1)	0
7980	OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();	0
7981		----
7982	if (NegLoIdx != -1) {	0
7983	int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);	0
7984	NegLo = Inst.getOperand(NegLoIdx).getImm();	0
7985	NegHi = Inst.getOperand(NegHiIdx).getImm();	0
7986	}	----
7987		----
7988	for (int J = 0; J < 3; ++J) {	0
7989	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	0
7990	if (OpIdx == -1)	0
7991	break;	0
7992		----
7993	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	0
7994		----
7995	if (ModIdx == -1)	0
7996	continue;	0
7997		----
7998	uint32_t ModVal = 0;	0
7999		----
8000	if ((OpSel & (1 << J)) != 0)	0
8001	ModVal \|= SISrcMods::OP_SEL_0;	0
8002		----
8003	if ((OpSelHi & (1 << J)) != 0)	0
8004	ModVal \|= SISrcMods::OP_SEL_1;	0
8005		----
8006	if ((NegLo & (1 << J)) != 0)	0
8007	ModVal \|= SISrcMods::NEG;	0
8008		----
8009	if ((NegHi & (1 << J)) != 0)	0
8010	ModVal \|= SISrcMods::NEG_HI;	0
8011		----
8012	Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() \| ModVal);	0
8013	}	----
8014	}	0
8015		----
8016	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {	0
8017	OptionalImmIndexMap OptIdx;	0
8018	cvtVOP3(Inst, Operands, OptIdx);	0
8019	cvtVOP3P(Inst, Operands, OptIdx);	0
8020	}	0
8021		----
8022	//===----------------------------------------------------------------------===//	----
8023	// VOPD	----
8024	//===----------------------------------------------------------------------===//	----
8025		----
8026	ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {	0
8027	if (!hasVOPD(getSTI()))	0
8028	return ParseStatus::NoMatch;	0
8029		----
8030	if (isToken(AsmToken::Colon) && peekToken(false).is(AsmToken::Colon)) {	0
8031	SMLoc S = getLoc();	0
8032	lex();	0
8033	lex();	0
8034	Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));	0
8035	SMLoc OpYLoc = getLoc();	0
8036	StringRef OpYName;	0
8037	if (isToken(AsmToken::Identifier) && !Parser.parseIdentifier(OpYName)) {	0
8038	Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));	0
8039	return ParseStatus::Success;	0
8040	}	----
8041	return Error(OpYLoc, "expected a VOPDY instruction after ::");	0
8042	}	----
8043	return ParseStatus::NoMatch;	0
8044	}	----
8045		----
8046	// Create VOPD MCInst operands using parsed assembler operands.	----
8047	void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {	0
8048	auto addOp = [&](uint16_t ParsedOprIdx) { // NOLINT:function pointer	0
8049	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);	0
8050	if (Op.isReg()) {	0
8051	Op.addRegOperands(Inst, 1);	0
8052	return;	0
8053	}	----
8054	if (Op.isImm()) {	0
8055	Op.addImmOperands(Inst, 1);	0
8056	return;	0
8057	}	----
8058	llvm_unreachable("Unhandled operand type in cvtVOPD");	0
8059	};	0
8060		----
8061	const auto &InstInfo = getVOPDInstInfo(Inst.getOpcode(), &MII);	0
8062		----
8063	// MCInst operands are ordered as follows:	----
8064	// dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]	----
8065		----
8066	for (auto CompIdx : VOPD::COMPONENTS) {	0
8067	addOp(InstInfo[CompIdx].getIndexOfDstInParsedOperands());	0
8068	}	----
8069		----
8070	for (auto CompIdx : VOPD::COMPONENTS) {	0
8071	const auto &CInfo = InstInfo[CompIdx];	0
8072	auto CompSrcOperandsNum = InstInfo[CompIdx].getCompParsedSrcOperandsNum();	0
8073	for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOperandsNum; ++CompSrcIdx)	0
8074	addOp(CInfo.getIndexOfSrcInParsedOperands(CompSrcIdx));	0
8075	if (CInfo.hasSrc2Acc())	0
8076	addOp(CInfo.getIndexOfDstInParsedOperands());	0
8077	}	----
8078	}	0
8079		----
8080	//===----------------------------------------------------------------------===//	----
8081	// dpp	----
8082	//===----------------------------------------------------------------------===//	----
8083		----
8084	bool AMDGPUOperand::isDPP8() const {	0
8085	return isImmTy(ImmTyDPP8);	0
8086	}	----
8087		----
8088	bool AMDGPUOperand::isDPPCtrl() const {	0
8089	using namespace AMDGPU::DPP;	----
8090		----
8091	bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());	0
8092	if (result) {	0
8093	int64_t Imm = getImm();	0
8094	return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) \|\|	0
8095	(Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) \|\|	0
8096	(Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) \|\|	0
8097	(Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) \|\|	0
8098	(Imm == DppCtrl::WAVE_SHL1) \|\|	0
8099	(Imm == DppCtrl::WAVE_ROL1) \|\|	0
8100	(Imm == DppCtrl::WAVE_SHR1) \|\|	0
8101	(Imm == DppCtrl::WAVE_ROR1) \|\|	0
8102	(Imm == DppCtrl::ROW_MIRROR) \|\|	0
8103	(Imm == DppCtrl::ROW_HALF_MIRROR) \|\|	0
8104	(Imm == DppCtrl::BCAST15) \|\|	0
8105	(Imm == DppCtrl::BCAST31) \|\|	0
8106	(Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) \|\|	0
8107	(Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST);	0
8108	}	----
8109	return false;	0
8110	}	----
8111		----
8112	//===----------------------------------------------------------------------===//	----
8113	// mAI	----
8114	//===----------------------------------------------------------------------===//	----
8115		----
8116	bool AMDGPUOperand::isBLGP() const {	0
8117	return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());	0
8118	}	----
8119		----
8120	bool AMDGPUOperand::isCBSZ() const {	0
8121	return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());	0
8122	}	----
8123		----
8124	bool AMDGPUOperand::isABID() const {	0
8125	return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());	0
8126	}	----
8127		----
8128	bool AMDGPUOperand::isS16Imm() const {	0
8129	return isImmLiteral() && (isInt<16>(getImm()) \|\| isUInt<16>(getImm()));	0
8130	}	----
8131		----
8132	bool AMDGPUOperand::isU16Imm() const {	0
8133	return isImmLiteral() && isUInt<16>(getImm());	0
8134	}	----
8135		----
8136	//===----------------------------------------------------------------------===//	----
8137	// dim	----
8138	//===----------------------------------------------------------------------===//	----
8139		----
8140	bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {	0
8141	// We want to allow "dim:1D" etc.,	----
8142	// but the initial 1 is tokenized as an integer.	----
8143	std::string Token;	0
8144	if (isToken(AsmToken::Integer)) {	0
8145	SMLoc Loc = getToken().getEndLoc();	0
8146	Token = std::string(getTokenStr());	0
8147	lex();	0
8148	if (getLoc() != Loc)	0
8149	return false;	0
8150	}	----
8151		----
8152	StringRef Suffix;	0
8153	if (!parseId(Suffix))	0
8154	return false;	0
8155	Token += Suffix;	0
8156		----
8157	StringRef DimId = Token;	0
8158	if (DimId.startswith("SQ_RSRC_IMG_"))	0
8159	DimId = DimId.drop_front(12);	0
8160		----
8161	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);	0
8162	if (!DimInfo)	0
8163	return false;	0
8164		----
8165	Encoding = DimInfo->Encoding;	0
8166	return true;	0
8167	}	0
8168		----
8169	ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {	0
8170	if (!isGFX10Plus())	0
8171	return ParseStatus::NoMatch;	0
8172		----
8173	SMLoc S = getLoc();	0
8174		----
8175	if (!trySkipId("dim", AsmToken::Colon))	0
8176	return ParseStatus::NoMatch;	0
8177		----
8178	unsigned Encoding;	----
8179	SMLoc Loc = getLoc();	0
8180	if (!parseDimId(Encoding))	0
8181	return Error(Loc, "invalid dim value");	0
8182		----
8183	Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,	0
8184	AMDGPUOperand::ImmTyDim));	----
8185	return ParseStatus::Success;	0
8186	}	----
8187		----
8188	//===----------------------------------------------------------------------===//	----
8189	// dpp	----
8190	//===----------------------------------------------------------------------===//	----
8191		----
8192	ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {	0
8193	SMLoc S = getLoc();	0
8194		----
8195	if (!isGFX10Plus() \|\| !trySkipId("dpp8", AsmToken::Colon))	0
8196	return ParseStatus::NoMatch;	0
8197		----
8198	// dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]	----
8199		----
8200	int64_t Sels[8];	----
8201		----
8202	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	0
8203	return ParseStatus::Failure;	0
8204		----
8205	for (size_t i = 0; i < 8; ++i) {	0
8206	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	0
8207	return ParseStatus::Failure;	0
8208		----
8209	SMLoc Loc = getLoc();	0
8210	if (getParser().parseAbsoluteExpression(Sels[i]))	0
8211	return ParseStatus::Failure;	0
8212	if (0 > Sels[i] \|\| 7 < Sels[i])	0
8213	return Error(Loc, "expected a 3-bit value");	0
8214	}	----
8215		----
8216	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
8217	return ParseStatus::Failure;	0
8218		----
8219	unsigned DPP8 = 0;	0
8220	for (size_t i = 0; i < 8; ++i)	0
8221	DPP8 \|= (Sels[i] << (i * 3));	0
8222		----
8223	Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));	0
8224	return ParseStatus::Success;	0
8225	}	----
8226		----
8227	bool	----
8228	AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,	0
8229	const OperandVector &Operands) {	----
8230	if (Ctrl == "row_newbcast")	0
8231	return isGFX90A();	0
8232		----
8233	if (Ctrl == "row_share" \|\|	0
8234	Ctrl == "row_xmask")	0
8235	return isGFX10Plus();	0
8236		----
8237	if (Ctrl == "wave_shl" \|\|	0
8238	Ctrl == "wave_shr" \|\|	0
8239	Ctrl == "wave_rol" \|\|	0
8240	Ctrl == "wave_ror" \|\|	0
8241	Ctrl == "row_bcast")	0
8242	return isVI() \|\| isGFX9();	0
8243		----
8244	return Ctrl == "row_mirror" \|\|	0
8245	Ctrl == "row_half_mirror" \|\|	0
8246	Ctrl == "quad_perm" \|\|	0
8247	Ctrl == "row_shl" \|\|	0
8248	Ctrl == "row_shr" \|\|	0
8249	Ctrl == "row_ror";	0
8250	}	----
8251		----
8252	int64_t	----
8253	AMDGPUAsmParser::parseDPPCtrlPerm() {	0
8254	// quad_perm:[%d,%d,%d,%d]	----
8255		----
8256	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	0
8257	return -1;	0
8258		----
8259	int64_t Val = 0;	0
8260	for (int i = 0; i < 4; ++i) {	0
8261	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	0
8262	return -1;	0
8263		----
8264	int64_t Temp;	----
8265	SMLoc Loc = getLoc();	0
8266	if (getParser().parseAbsoluteExpression(Temp))	0
8267	return -1;	0
8268	if (Temp < 0 \|\| Temp > 3) {	0
8269	Error(Loc, "expected a 2-bit value");	0
8270	return -1;	0
8271	}	----
8272		----
8273	Val += (Temp << i * 2);	0
8274	}	----
8275		----
8276	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
8277	return -1;	0
8278		----
8279	return Val;	0
8280	}	----
8281		----
8282	int64_t	----
8283	AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {	0
8284	using namespace AMDGPU::DPP;	----
8285		----
8286	// sel:%d	----
8287		----
8288	int64_t Val;	----
8289	SMLoc Loc = getLoc();	0
8290		----
8291	if (getParser().parseAbsoluteExpression(Val))	0
8292	return -1;	0
8293		----
8294	struct DppCtrlCheck {	----
8295	int64_t Ctrl;	----
8296	int Lo;	----
8297	int Hi;	----
8298	};	----
8299		----
8300	DppCtrlCheck Check = StringSwitch(Ctrl)	0
8301	.Case("wave_shl", {DppCtrl::WAVE_SHL1, 1, 1})	0
8302	.Case("wave_rol", {DppCtrl::WAVE_ROL1, 1, 1})	0
8303	.Case("wave_shr", {DppCtrl::WAVE_SHR1, 1, 1})	0
8304	.Case("wave_ror", {DppCtrl::WAVE_ROR1, 1, 1})	0
8305	.Case("row_shl", {DppCtrl::ROW_SHL0, 1, 15})	0
8306	.Case("row_shr", {DppCtrl::ROW_SHR0, 1, 15})	0
8307	.Case("row_ror", {DppCtrl::ROW_ROR0, 1, 15})	0
8308	.Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})	0
8309	.Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})	0
8310	.Case("row_newbcast", {DppCtrl::ROW_NEWBCAST_FIRST, 0, 15})	0
8311	.Default({-1, 0, 0});	0
8312		----
8313	bool Valid;	----
8314	if (Check.Ctrl == -1) {	0
8315	Valid = (Ctrl == "row_bcast" && (Val == 15 \|\| Val == 31));	0
8316	Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31;	0
8317	} else {	----
8318	Valid = Check.Lo <= Val && Val <= Check.Hi;	0
8319	Val = (Check.Lo == Check.Hi) ? Check.Ctrl : (Check.Ctrl \| Val);	0
8320	}	----
8321		----
8322	if (!Valid) {	0
8323	Error(Loc, Twine("invalid ", Ctrl) + Twine(" value"));	0
8324	return -1;	0
8325	}	----
8326		----
8327	return Val;	0
8328	}	----
8329		----
8330	ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {	0
8331	using namespace AMDGPU::DPP;	----
8332		----
8333	if (!isToken(AsmToken::Identifier) \|\|	0
8334	!isSupportedDPPCtrl(getTokenStr(), Operands))	0
8335	return ParseStatus::NoMatch;	0
8336		----
8337	SMLoc S = getLoc();	0
8338	int64_t Val = -1;	0
8339	StringRef Ctrl;	0
8340		----
8341	parseId(Ctrl);	0
8342		----
8343	if (Ctrl == "row_mirror") {	0
8344	Val = DppCtrl::ROW_MIRROR;	0
8345	} else if (Ctrl == "row_half_mirror") {	0
8346	Val = DppCtrl::ROW_HALF_MIRROR;	0
8347	} else {	----
8348	if (skipToken(AsmToken::Colon, "expected a colon")) {	0
8349	if (Ctrl == "quad_perm") {	0
8350	Val = parseDPPCtrlPerm();	0
8351	} else {	----
8352	Val = parseDPPCtrlSel(Ctrl);	0
8353	}	----
8354	}	----
8355	}	----
8356		----
8357	if (Val == -1)	0
8358	return ParseStatus::Failure;	0
8359		----
8360	Operands.push_back(	0
8361	AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyDppCtrl));	0
8362	return ParseStatus::Success;	0
8363	}	----
8364		----
8365	void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	0
8366	bool IsDPP8) {	----
8367	OptionalImmIndexMap OptionalIdx;	0
8368	unsigned Opc = Inst.getOpcode();	0
8369	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
8370		----
8371	// MAC instructions are special because they have 'old'	----
8372	// operand which is not tied to dst (but assumed to be).	----
8373	// They also have dummy unused src2_modifiers.	----
8374	int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old);	0
8375	int Src2ModIdx =	0
8376	AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);	0
8377	bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&	0
8378	Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;	0
8379		----
8380	unsigned I = 1;	0
8381	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
8382	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
8383	}	----
8384		----
8385	int Fi = 0;	0
8386	for (unsigned E = Operands.size(); I != E; ++I) {	0
8387		----
8388	if (IsMAC) {	0
8389	int NumOperands = Inst.getNumOperands();	0
8390	if (OldIdx == NumOperands) {	0
8391	// Handle old operand	----
8392	constexpr int DST_IDX = 0;	0
8393	Inst.addOperand(Inst.getOperand(DST_IDX));	0
8394	} else if (Src2ModIdx == NumOperands) {	0
8395	// Add unused dummy src2_modifiers	----
8396	Inst.addOperand(MCOperand::createImm(0));	0
8397	}	----
8398	}	----
8399		----
8400	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	0
8401	MCOI::TIED_TO);	----
8402	if (TiedTo != -1) {	0
8403	assert((unsigned)TiedTo < Inst.getNumOperands());	0
8404	// handle tied old or src2 for MAC instructions	----
8405	Inst.addOperand(Inst.getOperand(TiedTo));	0
8406	}	----
8407	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
8408	// Add the register arguments	----
8409	if (IsDPP8 && Op.isDppFI()) {	0
8410	Fi = Op.getImm();	0
8411	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8412	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
8413	} else if (Op.isReg()) {	0
8414	Op.addRegOperands(Inst, 1);	0
8415	} else if (Op.isImm() &&	0
8416	Desc.operands()[Inst.getNumOperands()].RegClass != -1) {	0
8417	assert(!Op.IsImmKindLiteral() && "Cannot use literal with DPP");	0
8418	Op.addImmOperands(Inst, 1);	0
8419	} else if (Op.isImm()) {	0
8420	OptionalIdx[Op.getImmTy()] = I;	0
8421	} else {	----
8422	llvm_unreachable("unhandled operand type");	0
8423	}	----
8424	}	----
8425	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
8426	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	0
8427		----
8428	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
8429	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);	0
8430		----
8431	if (Desc.TSFlags & SIInstrFlags::VOP3P)	0
8432	cvtVOP3P(Inst, Operands, OptionalIdx);	0
8433	else if (Desc.TSFlags & SIInstrFlags::VOP3)	0
8434	cvtVOP3OpSel(Inst, Operands, OptionalIdx);	0
8435	else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {	0
8436	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	0
8437	}	----
8438		----
8439	if (IsDPP8) {	0
8440	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);	0
8441	using namespace llvm::AMDGPU::DPP;	----
8442	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	0
8443	} else {	----
8444	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);	0
8445	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	0
8446	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	0
8447	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	0
8448		----
8449	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))	0
8450	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8451	AMDGPUOperand::ImmTyDppFI);	----
8452	}	----
8453	}	0
8454		----
8455	void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {	0
8456	OptionalImmIndexMap OptionalIdx;	0
8457		----
8458	unsigned I = 1;	0
8459	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
8460	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
8461	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
8462	}	----
8463		----
8464	int Fi = 0;	0
8465	for (unsigned E = Operands.size(); I != E; ++I) {	0
8466	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	0
8467	MCOI::TIED_TO);	----
8468	if (TiedTo != -1) {	0
8469	assert((unsigned)TiedTo < Inst.getNumOperands());	0
8470	// handle tied old or src2 for MAC instructions	----
8471	Inst.addOperand(Inst.getOperand(TiedTo));	0
8472	}	----
8473	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
8474	// Add the register arguments	----
8475	if (Op.isReg() && validateVccOperand(Op.getReg())) {	0
8476	// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.	----
8477	// Skip it.	----
8478	continue;	0
8479	}	----
8480		----
8481	if (IsDPP8) {	0
8482	if (Op.isDPP8()) {	0
8483	Op.addImmOperands(Inst, 1);	0
8484	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8485	Op.addRegWithFPInputModsOperands(Inst, 2);	0
8486	} else if (Op.isDppFI()) {	0
8487	Fi = Op.getImm();	0
8488	} else if (Op.isReg()) {	0
8489	Op.addRegOperands(Inst, 1);	0
8490	} else {	----
8491	llvm_unreachable("Invalid operand type");	0
8492	}	----
8493	} else {	----
8494	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8495	Op.addRegWithFPInputModsOperands(Inst, 2);	0
8496	} else if (Op.isReg()) {	0
8497	Op.addRegOperands(Inst, 1);	0
8498	} else if (Op.isDPPCtrl()) {	0
8499	Op.addImmOperands(Inst, 1);	0
8500	} else if (Op.isImm()) {	0
8501	// Handle optional arguments	----
8502	OptionalIdx[Op.getImmTy()] = I;	0
8503	} else {	----
8504	llvm_unreachable("Invalid operand type");	0
8505	}	----
8506	}	----
8507	}	----
8508		----
8509	if (IsDPP8) {	0
8510	using namespace llvm::AMDGPU::DPP;	----
8511	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	0
8512	} else {	----
8513	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	0
8514	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	0
8515	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	0
8516	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {	0
8517	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8518	AMDGPUOperand::ImmTyDppFI);	----
8519	}	----
8520	}	----
8521	}	0
8522		----
8523	//===----------------------------------------------------------------------===//	----
8524	// sdwa	----
8525	//===----------------------------------------------------------------------===//	----
8526		----
8527	ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,	0
8528	StringRef Prefix,	----
8529	AMDGPUOperand::ImmTy Type) {	----
8530	using namespace llvm::AMDGPU::SDWA;	----
8531		----
8532	SMLoc S = getLoc();	0
8533	StringRef Value;	0
8534		----
8535	SMLoc StringLoc;	0
8536	ParseStatus Res = parseStringWithPrefix(Prefix, Value, StringLoc);	0
8537	if (!Res.isSuccess())	0
8538	return Res;	0
8539		----
8540	int64_t Int;	----
8541	Int = StringSwitch(Value)	0
8542	.Case("BYTE_0", SdwaSel::BYTE_0)	0
8543	.Case("BYTE_1", SdwaSel::BYTE_1)	0
8544	.Case("BYTE_2", SdwaSel::BYTE_2)	0
8545	.Case("BYTE_3", SdwaSel::BYTE_3)	0
8546	.Case("WORD_0", SdwaSel::WORD_0)	0
8547	.Case("WORD_1", SdwaSel::WORD_1)	0
8548	.Case("DWORD", SdwaSel::DWORD)	0
8549	.Default(0xffffffff);	0
8550		----
8551	if (Int == 0xffffffff)	0
8552	return Error(StringLoc, "invalid " + Twine(Prefix) + " value");	0
8553		----
8554	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));	0
8555	return ParseStatus::Success;	0
8556	}	----
8557		----
8558	ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {	0
8559	using namespace llvm::AMDGPU::SDWA;	----
8560		----
8561	SMLoc S = getLoc();	0
8562	StringRef Value;	0
8563		----
8564	SMLoc StringLoc;	0
8565	ParseStatus Res = parseStringWithPrefix("dst_unused", Value, StringLoc);	0
8566	if (!Res.isSuccess())	0
8567	return Res;	0
8568		----
8569	int64_t Int;	----
8570	Int = StringSwitch(Value)	0
8571	.Case("UNUSED_PAD", DstUnused::UNUSED_PAD)	0
8572	.Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)	0
8573	.Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)	0
8574	.Default(0xffffffff);	0
8575		----
8576	if (Int == 0xffffffff)	0
8577	return Error(StringLoc, "invalid dst_unused value");	0
8578		----
8579	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));	0
8580	return ParseStatus::Success;	0
8581	}	----
8582		----
8583	void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {	0
8584	cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);	0
8585	}	0
8586		----
8587	void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {	0
8588	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);	0
8589	}	0
8590		----
8591	void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {	0
8592	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);	0
8593	}	0
8594		----
8595	void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {	0
8596	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);	0
8597	}	0
8598		----
8599	void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {	0
8600	cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());	0
8601	}	0
8602		----
8603	void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,	0
8604	uint64_t BasicInstType,	----
8605	bool SkipDstVcc,	----
8606	bool SkipSrcVcc) {	----
8607	using namespace llvm::AMDGPU::SDWA;	----
8608		----
8609	OptionalImmIndexMap OptionalIdx;	0
8610	bool SkipVcc = SkipDstVcc \|\| SkipSrcVcc;	0
8611	bool SkippedVcc = false;	0
8612		----
8613	unsigned I = 1;	0
8614	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
8615	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
8616	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
8617	}	----
8618		----
8619	for (unsigned E = Operands.size(); I != E; ++I) {	0
8620	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
8621	if (SkipVcc && !SkippedVcc && Op.isReg() &&	0
8622	(Op.getReg() == AMDGPU::VCC \|\| Op.getReg() == AMDGPU::VCC_LO)) {	0
8623	// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.	----
8624	// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)	----
8625	// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.	----
8626	// Skip VCC only if we didn't skip it on previous iteration.	----
8627	// Note that src0 and src1 occupy 2 slots each because of modifiers.	----
8628	if (BasicInstType == SIInstrFlags::VOP2 &&	0
8629	((SkipDstVcc && Inst.getNumOperands() == 1) \|\|	0
8630	(SkipSrcVcc && Inst.getNumOperands() == 5))) {	0
8631	SkippedVcc = true;	0
8632	continue;	0
8633	} else if (BasicInstType == SIInstrFlags::VOPC &&	0
8634	Inst.getNumOperands() == 0) {	0
8635	SkippedVcc = true;	0
8636	continue;	0
8637	}	----
8638	}	----
8639	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8640	Op.addRegOrImmWithInputModsOperands(Inst, 2);	0
8641	} else if (Op.isImm()) {	0
8642	// Handle optional arguments	----
8643	OptionalIdx[Op.getImmTy()] = I;	0
8644	} else {	----
8645	llvm_unreachable("Invalid operand type");	0
8646	}	----
8647	SkippedVcc = false;	0
8648	}	----
8649		----
8650	const unsigned Opc = Inst.getOpcode();	0
8651	if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&	0
8652	Opc != AMDGPU::V_NOP_sdwa_vi) {	----
8653	// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments	----
8654	switch (BasicInstType) {	0
8655	case SIInstrFlags::VOP1:	0
8656	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
8657	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8658	AMDGPUOperand::ImmTyClampSI, 0);	----
8659		----
8660	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
8661	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8662	AMDGPUOperand::ImmTyOModSI, 0);	----
8663		----
8664	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))	0
8665	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8666	AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	----
8667		----
8668	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))	0
8669	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8670	AMDGPUOperand::ImmTySDWADstUnused,	----
8671	DstUnused::UNUSED_PRESERVE);	----
8672		----
8673	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0
8674	break;	0
8675		----
8676	case SIInstrFlags::VOP2:	0
8677	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	0
8678		----
8679	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))	0
8680	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);	0
8681		----
8682	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	0
8683	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);	0
8684	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0
8685	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	0
8686	break;	0
8687		----
8688	case SIInstrFlags::VOPC:	0
8689	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))	0
8690	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	0
8691	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0
8692	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	0
8693	break;	0
8694		----
8695	default:	0
8696	llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");	0
8697	}	----
8698	}	----
8699		----
8700	// special case v_mac_{f16, f32}:	----
8701	// it has src2 register operand that is tied to dst operand	----
8702	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	0
8703	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	0
8704	auto it = Inst.begin();	0
8705	std::advance(	0
8706	it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));	0
8707	Inst.insert(it, Inst.getOperand(0)); // src2 = dst	0
8708	}	----
8709	}	0
8710		----
8711	/// Force static initialization.	----
8712	extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8713	RegisterMCAsmParser A(getTheR600Target());	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8714	RegisterMCAsmParser B(getTheGCNTarget());	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8715	}	2	../DebugInfoTest/example_mips_dbg.ll ../DebugInfoTest/example_mips.ll
8716		----
8717	#define GET_REGISTER_MATCHER	----
8718	#define GET_MATCHER_IMPLEMENTATION	----
8719	#define GET_MNEMONIC_SPELL_CHECKER	----
8720	#define GET_MNEMONIC_CHECKER	----
8721	#include "AMDGPUGenAsmMatcher.inc"	----
8722		----
8723	ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,	0
8724	unsigned MCK) {	----
8725	switch (MCK) {	0
8726	case MCK_addr64:	0
8727	return parseTokenOp("addr64", Operands);	0
8728	case MCK_done:	0
8729	return parseTokenOp("done", Operands);	0
8730	case MCK_idxen:	0
8731	return parseTokenOp("idxen", Operands);	0
8732	case MCK_lds:	0
8733	return parseTokenOp("lds", Operands);	0
8734	case MCK_offen:	0
8735	return parseTokenOp("offen", Operands);	0
8736	case MCK_off:	0
8737	return parseTokenOp("off", Operands);	0
8738	case MCK_row_95_en:	0
8739	return parseTokenOp("row_en", Operands);	0
8740	case MCK_gds:	0
8741	return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);	0
8742	case MCK_tfe:	0
8743	return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);	0
8744	}	----
8745	return tryCustomParseOperand(Operands, MCK);	0
8746	}	----
8747		----
8748	// This function should be defined after auto-generated include so that we have	----
8749	// MatchClassKind enum defined	----
8750	unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,	0
8751	unsigned Kind) {	----
8752	// Tokens like "glc" would be parsed as immediate operands in ParseOperand().	----
8753	// But MatchInstructionImpl() expects to meet token and fails to validate	----
8754	// operand. This method checks if we are given immediate operand but expect to	----
8755	// get corresponding token.	----
8756	AMDGPUOperand &Operand = (AMDGPUOperand&)Op;	0
8757	switch (Kind) {	0
8758	case MCK_addr64:	0
8759	return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;	0
8760	case MCK_gds:	0
8761	return Operand.isGDS() ? Match_Success : Match_InvalidOperand;	0
8762	case MCK_lds:	0
8763	return Operand.isLDS() ? Match_Success : Match_InvalidOperand;	0
8764	case MCK_idxen:	0
8765	return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;	0
8766	case MCK_offen:	0
8767	return Operand.isOffen() ? Match_Success : Match_InvalidOperand;	0
8768	case MCK_tfe:	0
8769	return Operand.isTFE() ? Match_Success : Match_InvalidOperand;	0
8770	case MCK_SSrcB32:	0
8771	// When operands have expression values, they will return true for isToken,	----
8772	// because it is not possible to distinguish between a token and an	----
8773	// expression at parse time. MatchInstructionImpl() will always try to	----
8774	// match an operand as a token, when isToken returns true, and when the	----
8775	// name of the expression is not a valid token, the match will fail,	----
8776	// so we need to handle it here.	----
8777	return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;	0
8778	case MCK_SSrcF32:	0
8779	return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;	0
8780	case MCK_SOPPBrTarget:	0
8781	return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;	0
8782	case MCK_VReg32OrOff:	0
8783	return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;	0
8784	case MCK_InterpSlot:	0
8785	return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;	0
8786	case MCK_InterpAttr:	0
8787	return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;	0
8788	case MCK_InterpAttrChan:	0
8789	return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;	0
8790	case MCK_SReg_64:	0
8791	case MCK_SReg_64_XEXEC:	----
8792	// Null is defined as a 32-bit register but	----
8793	// it should also be enabled with 64-bit operands.	----
8794	// The following code enables it for SReg_64 operands	----
8795	// used as source and destination. Remaining source	----
8796	// operands are handled in isInlinableImm.	----
8797	return Operand.isNull() ? Match_Success : Match_InvalidOperand;	0
8798	default:	0
8799	return Match_InvalidOperand;	0
8800	}	----
8801	}	----
8802		----
8803	//===----------------------------------------------------------------------===//	----
8804	// endpgm	----
8805	//===----------------------------------------------------------------------===//	----
8806		----
8807	ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {	0
8808	SMLoc S = getLoc();	0
8809	int64_t Imm = 0;	0
8810		----
8811	if (!parseExpr(Imm)) {	0
8812	// The operand is optional, if not present default to 0	----
8813	Imm = 0;	0
8814	}	----
8815		----
8816	if (!isUInt<16>(Imm))	0
8817	return Error(S, "expected a 16-bit value");	0
8818		----
8819	Operands.push_back(	0
8820	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));	0
8821	return ParseStatus::Success;	0
8822	}	----
8823		----
8824	bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }	0
8825		----
8826	//===----------------------------------------------------------------------===//	----
8827	// LDSDIR	----
8828	//===----------------------------------------------------------------------===//	----
8829		----
8830	bool AMDGPUOperand::isWaitVDST() const {	0
8831	return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());	0
8832	}	----
8833		----
8834	//===----------------------------------------------------------------------===//	----
8835	// VINTERP	----
8836	//===----------------------------------------------------------------------===//	----
8837		----
8838	bool AMDGPUOperand::isWaitEXP() const {	0
8839	return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());	0
8840	}	----
8841		----

Functions Report

Function name	Number of hits
_ZN12_GLOBAL__N_113AMDGPUOperandC2ENS0_6KindTyEPKNS_15AMDGPUAsmParserE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9Modifiers14hasFPModifiersEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9Modifiers15hasIntModifiersEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9Modifiers12hasModifiersEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9Modifiers21getFPModifiersOperandEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9Modifiers22getIntModifiersOperandEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9Modifiers19getModifiersOperandEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isTokenEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isSymbolRefExprEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isImmEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14setImmKindNoneEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand17setImmKindLiteralEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand26setImmKindMandatoryLiteralEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15setImmKindConstEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand16IsImmKindLiteralEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand25IsImmKindMandatoryLiteralEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isImmKindConstEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isRegKindEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isRegEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isRegOrInlineEjN4llvm3MVTE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand23isRegOrImmWithInputModsEjN4llvm3MVTE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand28isRegOrImmWithInt32InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand34isRegOrInlineImmWithInt32InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand28isRegOrImmWithInt64InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand27isRegOrImmWithFP16InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand27isRegOrImmWithFP32InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand27isRegOrImmWithFP64InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand33isRegOrInlineImmWithFP16InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand33isRegOrInlineImmWithFP32InputModsEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isVReg32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isVReg32OrOffEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand6isNullEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isImmTyENS0_5ImmTyE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isImmLiteralEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isImmModifierEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isClampSIEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isOModSIEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isDMaskEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isDimEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isUNormEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand4isDAEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isR128A16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isA16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isLWEEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isOffEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isExpTgtEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isExpVMEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isExpComprEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isOffenEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isIdxenEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isAddr64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isOffsetEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isOffset0Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isOffset1Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isSMEMOffsetModEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isFlatOffsetEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isGDSEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isLDSEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand6isCPolEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isTFEEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isD16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isFORMATEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isDppBankMaskEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isDppRowMaskEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isDppBoundCtrlEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isDppFIEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isSDWADstSelEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isSDWASrc0SelEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isSDWASrc1SelEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isSDWADstUnusedEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isInterpSlotEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isInterpAttrEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand16isInterpAttrChanEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isOpSelEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isOpSelHiEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isNegLoEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isNegHiEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand6isHighEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isRegOrImmEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand19isRegOrInlineNoModsEjN4llvm3MVTE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isSCSrcB32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isSCSrcB64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isSSrcB32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isSSrcB64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isSSrcF32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isSSrcOrLdsB32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isVCSrcB32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand17isVCSrcTB16_Lo128Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isVCSrcB16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isVCSrcV2B16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isVCSrcF32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isVCSrcF64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand17isVCSrcTF16_Lo128Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isVCSrcF16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isVCSrcV2F16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isVSrcB32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isVSrcB64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand16isVSrcTB16_Lo128Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isVSrcB16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand11isVSrcV2B16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isVSrcV2FP32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isVSrcV2INT32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isVSrcF32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isVSrcF64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand16isVSrcTF16_Lo128Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isVSrcF16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand11isVSrcV2F16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isVISrc_64F64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isVISrc_256F64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isVISrc_128B32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isVISrc_128F32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isVISrc_512B32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isVISrc_512F32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isVISrc_1024B32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isVISrc_1024F32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand13isAISrc_64F64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isAISrc_128B32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isAISrc_128F32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isAISrc_256F64Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isAISrc_512B32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isAISrc_512F32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isAISrc_1024B32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15isAISrc_1024F32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isKImmFP32Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isKImmFP16Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5isMemEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand6isExprEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14isSOPPBrTargetEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8getTokenEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand6getImmEv	0
_ZN12_GLOBAL__N_113AMDGPUOperand6setImmEl	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8getImmTyEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand6getRegEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand11getStartLocEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9getEndLocEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12getModifiersEv	0
_ZN12_GLOBAL__N_113AMDGPUOperand12setModifiersENS0_9ModifiersE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12hasModifiersEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand14hasFPModifiersEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand15hasIntModifiersEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand19addRegOrImmOperandsERN4llvm6MCInstEj	0
_ZNK12_GLOBAL__N_113AMDGPUOperand32addRegOrImmWithInputModsOperandsERN4llvm6MCInstEj	0
_ZNK12_GLOBAL__N_113AMDGPUOperand34addRegOrImmWithFPInputModsOperandsERN4llvm6MCInstEj	0
_ZNK12_GLOBAL__N_113AMDGPUOperand27addRegWithInputModsOperandsERN4llvm6MCInstEj	0
_ZNK12_GLOBAL__N_113AMDGPUOperand29addRegWithFPInputModsOperandsERN4llvm6MCInstEj	0
_ZN12_GLOBAL__N_113AMDGPUOperand10printImmTyERN4llvm11raw_ostreamENS0_5ImmTyE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand5printERN4llvm11raw_ostreamE	0
_ZN12_GLOBAL__N_113AMDGPUOperand9CreateImmEPKNS_15AMDGPUAsmParserElN4llvm5SMLocENS0_5ImmTyEb	0
_ZN12_GLOBAL__N_113AMDGPUOperand11CreateTokenEPKNS_15AMDGPUAsmParserEN4llvm9StringRefENS4_5SMLocEb	0
_ZN12_GLOBAL__N_113AMDGPUOperand9CreateRegEPKNS_15AMDGPUAsmParserEjN4llvm5SMLocES5_	0
_ZN12_GLOBAL__N_113AMDGPUOperand10CreateExprEPKNS_15AMDGPUAsmParserEPKN4llvm6MCExprENS4_5SMLocE	0
_ZN12_GLOBAL__N_1lsERN4llvm11raw_ostreamENS_13AMDGPUOperand9ModifiersE	0
_ZN12_GLOBAL__N_115KernelScopeInfo10usesSgprAtEi	0
_ZN12_GLOBAL__N_115KernelScopeInfo10usesVgprAtEi	0
_ZN12_GLOBAL__N_115KernelScopeInfo10usesAgprAtEi	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser13parseSWaitCntERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser10parseDelayERl	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser14parseSDelayALUERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand10isSWaitCntEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand11isSDelayALUEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser11depCtrErrorEN4llvm5SMLocEiNS1_9StringRefE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser11parseDepCtrERlRj	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser11parseDepCtrERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand8isDepCtrEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser14parseHwregBodyERNS0_13OperandInfoTyES2_S2_	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser13validateHwregERKNS0_13OperandInfoTyES3_S3_	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser10parseHwregERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand7isHwregEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser16parseSendMsgBodyERNS0_13OperandInfoTyES2_S2_	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser15validateSendMsgERKNS0_13OperandInfoTyES3_S3_	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser12parseSendMsgERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand9isSendMsgEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser15parseInterpSlotERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser15parseInterpAttrERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser11parseExpTgtERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser4isIdERKN4llvm8AsmTokenENS1_9StringRefE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser4isIdEN4llvm9StringRefE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser7isTokenEN4llvm8AsmToken9TokenKindE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser5getIdEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9trySkipIdEN4llvm9StringRefE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9trySkipIdEN4llvm9StringRefES2_	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9trySkipIdEN4llvm9StringRefENS1_8AsmToken9TokenKindE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser12trySkipTokenEN4llvm8AsmToken9TokenKindE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9skipTokenEN4llvm8AsmToken9TokenKindENS1_9StringRefE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9parseExprERlN4llvm9StringRefE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9parseExprERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser11parseStringERN4llvm9StringRefES2_	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser7parseIdERN4llvm9StringRefES2_	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser8getTokenEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser9peekTokenEb	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser10peekTokensEN4llvm15MutableArrayRefINS1_8AsmTokenEEE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser12getTokenKindEv	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser6getLocEv	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser11getTokenStrEv	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser3lexEv	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser10getInstLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser13getOperandLocESt8functionIFbRKNS_13AMDGPUOperandEEERKN4llvm15SmallVectorImplISt10unique_ptrINS7_18MCParsedAsmOperandESt14default_deleteISA_EEEE	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser9getImmLocENS_13AMDGPUOperand5ImmTyERKN4llvm15SmallVectorImplISt10unique_ptrINS3_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
_ZZNK12_GLOBAL__N_115AMDGPUAsmParser9getImmLocENS_13AMDGPUOperand5ImmTyERKN4llvm15SmallVectorImplISt10unique_ptrINS3_18MCParsedAsmOperandESt14default_deleteIS6_EEEEENKUlRKS1_E_clESE_	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser9getRegLocEjRKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZZNK12_GLOBAL__N_115AMDGPUAsmParser9getRegLocEjRKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEEENKUlRKNS_13AMDGPUOperandEE_clESD_	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser9getLitLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEEb	0
_ZZNK12_GLOBAL__N_115AMDGPUAsmParser9getLitLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEEbENKUlRKNS_13AMDGPUOperandEE_clESD_	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser18getMandatoryLitLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZZNK12_GLOBAL__N_115AMDGPUAsmParser18getMandatoryLitLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEEENKUlRKNS_13AMDGPUOperandEE_clESD_	0
_ZNK12_GLOBAL__N_115AMDGPUAsmParser11getConstLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZZNK12_GLOBAL__N_115AMDGPUAsmParser11getConstLocERKN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEEENKUlRKNS_13AMDGPUOperandEE_clESD_	0
_ZL17encodeBitmaskPermjjj	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser19parseSwizzleOperandERljjN4llvm9StringRefERNS2_5SMLocE	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser19parseSwizzleReverseERl	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser16parseSwizzleSwapERl	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser23parseSwizzleBitmaskPermERl	0
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_ZNK12_GLOBAL__N_113AMDGPUOperand9isSwizzleEv	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser15parseGPRIdxModeERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isGPRIdxModeEv	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser12parseBoolRegERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser12cvtMubufImplERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEEb	0
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_ZNK12_GLOBAL__N_113AMDGPUOperand13isSMRDOffset8Ev	0
_ZNK12_GLOBAL__N_113AMDGPUOperand12isSMEMOffsetEv	0
_ZNK12_GLOBAL__N_113AMDGPUOperand19isSMRDLiteralOffsetEv	0
_ZL14ConvertOmodMulRl	0
_ZL14ConvertOmodDivRl	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser12cvtVOP3OpSelERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
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_ZL23isRegOrImmWithInputModsRKN4llvm11MCInstrDescEj	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser13cvtVOP3InterpERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser10cvtVINTERPERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser7cvtVOP3ERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEERSt3mapINS_13AMDGPUOperand5ImmTyEjSt4lessISF_ESaISt4pairIKSF_jEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser7cvtVOP3ERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser10cvtVOP3DPPERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEEb	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser12cvtSdwaVOP2bERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
_ZN12_GLOBAL__N_115AMDGPUAsmParser12cvtSdwaVOP2eERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEE	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser7cvtSDWAERN4llvm6MCInstERKNS1_15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS6_EEEEmbb	0
LLVMInitializeAMDGPUAsmParser	2
_ZN12_GLOBAL__N_115AMDGPUAsmParser18parseCustomOperandERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEEj	0
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_ZN12_GLOBAL__N_115AMDGPUAsmParser11parseEndpgmERN4llvm15SmallVectorImplISt10unique_ptrINS1_18MCParsedAsmOperandESt14default_deleteIS4_EEEE	0
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Coverage Diff

Line Number	../DebugInfoTest/example_mips_dbg.ll BUT NOT ../DebugInfoTest/example_mips.ll	Line Number	../DebugInfoTest/example_mips.ll BUT NOT ../DebugInfoTest/example_mips_dbg.ll
1	//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//	1	//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//
2	//	2	//
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.	3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4	// See https://llvm.org/LICENSE.txt for license information.	4	// See https://llvm.org/LICENSE.txt for license information.
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception	5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6	//	6	//
7	//===----------------------------------------------------------------------===//	7	//===----------------------------------------------------------------------===//
8		8
9	#include "AMDKernelCodeT.h"	9	#include "AMDKernelCodeT.h"
10	#include "MCTargetDesc/AMDGPUMCTargetDesc.h"	10	#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
11	#include "MCTargetDesc/AMDGPUTargetStreamer.h"	11	#include "MCTargetDesc/AMDGPUTargetStreamer.h"
12	#include "SIDefines.h"	12	#include "SIDefines.h"
13	#include "SIInstrInfo.h"	13	#include "SIInstrInfo.h"
14	#include "SIRegisterInfo.h"	14	#include "SIRegisterInfo.h"
15	#include "TargetInfo/AMDGPUTargetInfo.h"	15	#include "TargetInfo/AMDGPUTargetInfo.h"
16	#include "Utils/AMDGPUAsmUtils.h"	16	#include "Utils/AMDGPUAsmUtils.h"
17	#include "Utils/AMDGPUBaseInfo.h"	17	#include "Utils/AMDGPUBaseInfo.h"
18	#include "Utils/AMDKernelCodeTUtils.h"	18	#include "Utils/AMDKernelCodeTUtils.h"
19	#include "llvm/ADT/APFloat.h"	19	#include "llvm/ADT/APFloat.h"
20	#include "llvm/ADT/SmallBitVector.h"	20	#include "llvm/ADT/SmallBitVector.h"
21	#include "llvm/ADT/StringSet.h"	21	#include "llvm/ADT/StringSet.h"
22	#include "llvm/ADT/Twine.h"	22	#include "llvm/ADT/Twine.h"
23	#include "llvm/BinaryFormat/ELF.h"	23	#include "llvm/BinaryFormat/ELF.h"
24	#include "llvm/CodeGen/MachineValueType.h"	24	#include "llvm/CodeGen/MachineValueType.h"
25	#include "llvm/MC/MCAsmInfo.h"	25	#include "llvm/MC/MCAsmInfo.h"
26	#include "llvm/MC/MCContext.h"	26	#include "llvm/MC/MCContext.h"
27	#include "llvm/MC/MCExpr.h"	27	#include "llvm/MC/MCExpr.h"
28	#include "llvm/MC/MCInst.h"	28	#include "llvm/MC/MCInst.h"
29	#include "llvm/MC/MCInstrDesc.h"	29	#include "llvm/MC/MCInstrDesc.h"
30	#include "llvm/MC/MCParser/MCAsmLexer.h"	30	#include "llvm/MC/MCParser/MCAsmLexer.h"
31	#include "llvm/MC/MCParser/MCAsmParser.h"	31	#include "llvm/MC/MCParser/MCAsmParser.h"
32	#include "llvm/MC/MCParser/MCParsedAsmOperand.h"	32	#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
33	#include "llvm/MC/MCParser/MCTargetAsmParser.h"	33	#include "llvm/MC/MCParser/MCTargetAsmParser.h"
34	#include "llvm/MC/MCSymbol.h"	34	#include "llvm/MC/MCSymbol.h"
35	#include "llvm/MC/TargetRegistry.h"	35	#include "llvm/MC/TargetRegistry.h"
36	#include "llvm/Support/AMDGPUMetadata.h"	36	#include "llvm/Support/AMDGPUMetadata.h"
37	#include "llvm/Support/AMDHSAKernelDescriptor.h"	37	#include "llvm/Support/AMDHSAKernelDescriptor.h"
38	#include "llvm/Support/Casting.h"	38	#include "llvm/Support/Casting.h"
39	#include "llvm/Support/MathExtras.h"	39	#include "llvm/Support/MathExtras.h"
40	#include "llvm/TargetParser/TargetParser.h"	40	#include "llvm/TargetParser/TargetParser.h"
41	#include	41	#include
42		42
43	using namespace llvm;	43	using namespace llvm;
44	using namespace llvm::AMDGPU;	44	using namespace llvm::AMDGPU;
45	using namespace llvm::amdhsa;	45	using namespace llvm::amdhsa;
46		46
47	namespace {	47	namespace {
48		48
49	class AMDGPUAsmParser;	49	class AMDGPUAsmParser;
50		50
51	enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL };	51	enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL };
52		52
53	//===----------------------------------------------------------------------===//	53	//===----------------------------------------------------------------------===//
54	// Operand	54	// Operand
55	//===----------------------------------------------------------------------===//	55	//===----------------------------------------------------------------------===//
56		56
57	class AMDGPUOperand : public MCParsedAsmOperand {	57	class AMDGPUOperand : public MCParsedAsmOperand {
58	enum KindTy {	58	enum KindTy {
59	Token,	59	Token,
60	Immediate,	60	Immediate,
61	Register,	61	Register,
62	Expression	62	Expression
63	} Kind;	63	} Kind;
64		64
65	SMLoc StartLoc, EndLoc;	65	SMLoc StartLoc, EndLoc;
66	const AMDGPUAsmParser *AsmParser;	66	const AMDGPUAsmParser *AsmParser;
67		67
68	public:	68	public:
69	AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)	69	AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)
70	: Kind(Kind_), AsmParser(AsmParser_) {}	70	: Kind(Kind_), AsmParser(AsmParser_) {}
71		71
72	using Ptr = std::unique_ptr;	72	using Ptr = std::unique_ptr;
73		73
74	struct Modifiers {	74	struct Modifiers {
75	bool Abs = false;	75	bool Abs = false;
76	bool Neg = false;	76	bool Neg = false;
77	bool Sext = false;	77	bool Sext = false;
78		78
79	bool hasFPModifiers() const { return Abs \|\| Neg; }	79	bool hasFPModifiers() const { return Abs \|\| Neg; }
80	bool hasIntModifiers() const { return Sext; }	80	bool hasIntModifiers() const { return Sext; }
81	bool hasModifiers() const { return hasFPModifiers() \|\| hasIntModifiers(); }	81	bool hasModifiers() const { return hasFPModifiers() \|\| hasIntModifiers(); }
82		82
83	int64_t getFPModifiersOperand() const {	83	int64_t getFPModifiersOperand() const {
84	int64_t Operand = 0;	84	int64_t Operand = 0;
85	Operand \|= Abs ? SISrcMods::ABS : 0u;	85	Operand \|= Abs ? SISrcMods::ABS : 0u;
86	Operand \|= Neg ? SISrcMods::NEG : 0u;	86	Operand \|= Neg ? SISrcMods::NEG : 0u;
87	return Operand;	87	return Operand;
88	}	88	}
89		89
90	int64_t getIntModifiersOperand() const {	90	int64_t getIntModifiersOperand() const {
91	int64_t Operand = 0;	91	int64_t Operand = 0;
92	Operand \|= Sext ? SISrcMods::SEXT : 0u;	92	Operand \|= Sext ? SISrcMods::SEXT : 0u;
93	return Operand;	93	return Operand;
94	}	94	}
95		95
96	int64_t getModifiersOperand() const {	96	int64_t getModifiersOperand() const {
97	assert(!(hasFPModifiers() && hasIntModifiers())	97	assert(!(hasFPModifiers() && hasIntModifiers())
98	&& "fp and int modifiers should not be used simultaneously");	98	&& "fp and int modifiers should not be used simultaneously");
99	if (hasFPModifiers()) {	99	if (hasFPModifiers()) {
100	return getFPModifiersOperand();	100	return getFPModifiersOperand();
101	} else if (hasIntModifiers()) {	101	} else if (hasIntModifiers()) {
102	return getIntModifiersOperand();	102	return getIntModifiersOperand();
103	} else {	103	} else {
104	return 0;	104	return 0;
105	}	105	}
106	}	106	}
107		107
108	friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);	108	friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);
109	};	109	};
110		110
111	enum ImmTy {	111	enum ImmTy {
112	ImmTyNone,	112	ImmTyNone,
113	ImmTyGDS,	113	ImmTyGDS,
114	ImmTyLDS,	114	ImmTyLDS,
115	ImmTyOffen,	115	ImmTyOffen,
116	ImmTyIdxen,	116	ImmTyIdxen,
117	ImmTyAddr64,	117	ImmTyAddr64,
118	ImmTyOffset,	118	ImmTyOffset,
119	ImmTyInstOffset,	119	ImmTyInstOffset,
120	ImmTyOffset0,	120	ImmTyOffset0,
121	ImmTyOffset1,	121	ImmTyOffset1,
122	ImmTySMEMOffsetMod,	122	ImmTySMEMOffsetMod,
123	ImmTyCPol,	123	ImmTyCPol,
124	ImmTyTFE,	124	ImmTyTFE,
125	ImmTyD16,	125	ImmTyD16,
126	ImmTyClampSI,	126	ImmTyClampSI,
127	ImmTyOModSI,	127	ImmTyOModSI,
128	ImmTySDWADstSel,	128	ImmTySDWADstSel,
129	ImmTySDWASrc0Sel,	129	ImmTySDWASrc0Sel,
130	ImmTySDWASrc1Sel,	130	ImmTySDWASrc1Sel,
131	ImmTySDWADstUnused,	131	ImmTySDWADstUnused,
132	ImmTyDMask,	132	ImmTyDMask,
133	ImmTyDim,	133	ImmTyDim,
134	ImmTyUNorm,	134	ImmTyUNorm,
135	ImmTyDA,	135	ImmTyDA,
136	ImmTyR128A16,	136	ImmTyR128A16,
137	ImmTyA16,	137	ImmTyA16,
138	ImmTyLWE,	138	ImmTyLWE,
139	ImmTyExpTgt,	139	ImmTyExpTgt,
140	ImmTyExpCompr,	140	ImmTyExpCompr,
141	ImmTyExpVM,	141	ImmTyExpVM,
142	ImmTyFORMAT,	142	ImmTyFORMAT,
143	ImmTyHwreg,	143	ImmTyHwreg,
144	ImmTyOff,	144	ImmTyOff,
145	ImmTySendMsg,	145	ImmTySendMsg,
146	ImmTyInterpSlot,	146	ImmTyInterpSlot,
147	ImmTyInterpAttr,	147	ImmTyInterpAttr,
148	ImmTyInterpAttrChan,	148	ImmTyInterpAttrChan,
149	ImmTyOpSel,	149	ImmTyOpSel,
150	ImmTyOpSelHi,	150	ImmTyOpSelHi,
151	ImmTyNegLo,	151	ImmTyNegLo,
152	ImmTyNegHi,	152	ImmTyNegHi,
153	ImmTyDPP8,	153	ImmTyDPP8,
154	ImmTyDppCtrl,	154	ImmTyDppCtrl,
155	ImmTyDppRowMask,	155	ImmTyDppRowMask,
156	ImmTyDppBankMask,	156	ImmTyDppBankMask,
157	ImmTyDppBoundCtrl,	157	ImmTyDppBoundCtrl,
158	ImmTyDppFI,	158	ImmTyDppFI,
159	ImmTySwizzle,	159	ImmTySwizzle,
160	ImmTyGprIdxMode,	160	ImmTyGprIdxMode,
161	ImmTyHigh,	161	ImmTyHigh,
162	ImmTyBLGP,	162	ImmTyBLGP,
163	ImmTyCBSZ,	163	ImmTyCBSZ,
164	ImmTyABID,	164	ImmTyABID,
165	ImmTyEndpgm,	165	ImmTyEndpgm,
166	ImmTyWaitVDST,	166	ImmTyWaitVDST,
167	ImmTyWaitEXP,	167	ImmTyWaitEXP,
168	};	168	};
169		169
170	// Immediate operand kind.	170	// Immediate operand kind.
171	// It helps to identify the location of an offending operand after an error.	171	// It helps to identify the location of an offending operand after an error.
172	// Note that regular literals and mandatory literals (KImm) must be handled	172	// Note that regular literals and mandatory literals (KImm) must be handled
173	// differently. When looking for an offending operand, we should usually	173	// differently. When looking for an offending operand, we should usually
174	// ignore mandatory literals because they are part of the instruction and	174	// ignore mandatory literals because they are part of the instruction and
175	// cannot be changed. Report location of mandatory operands only for VOPD,	175	// cannot be changed. Report location of mandatory operands only for VOPD,
176	// when both OpX and OpY have a KImm and there are no other literals.	176	// when both OpX and OpY have a KImm and there are no other literals.
177	enum ImmKindTy {	177	enum ImmKindTy {
178	ImmKindTyNone,	178	ImmKindTyNone,
179	ImmKindTyLiteral,	179	ImmKindTyLiteral,
180	ImmKindTyMandatoryLiteral,	180	ImmKindTyMandatoryLiteral,
181	ImmKindTyConst,	181	ImmKindTyConst,
182	};	182	};
183		183
184	private:	184	private:
185	struct TokOp {	185	struct TokOp {
186	const char *Data;	186	const char *Data;
187	unsigned Length;	187	unsigned Length;
188	};	188	};
189		189
190	struct ImmOp {	190	struct ImmOp {
191	int64_t Val;	191	int64_t Val;
192	ImmTy Type;	192	ImmTy Type;
193	bool IsFPImm;	193	bool IsFPImm;
194	mutable ImmKindTy Kind;	194	mutable ImmKindTy Kind;
195	Modifiers Mods;	195	Modifiers Mods;
196	};	196	};
197		197
198	struct RegOp {	198	struct RegOp {
199	unsigned RegNo;	199	unsigned RegNo;
200	Modifiers Mods;	200	Modifiers Mods;
201	};	201	};
202		202
203	union {	203	union {
204	TokOp Tok;	204	TokOp Tok;
205	ImmOp Imm;	205	ImmOp Imm;
206	RegOp Reg;	206	RegOp Reg;
207	const MCExpr *Expr;	207	const MCExpr *Expr;
208	};	208	};
209		209
210	public:	210	public:
211	bool isToken() const override { return Kind == Token; }	211	bool isToken() const override { return Kind == Token; }
212		212
213	bool isSymbolRefExpr() const {	213	bool isSymbolRefExpr() const {
214	return isExpr() && Expr && isa(Expr);	214	return isExpr() && Expr && isa(Expr);
215	}	215	}
216		216
217	bool isImm() const override {	217	bool isImm() const override {
218	return Kind == Immediate;	218	return Kind == Immediate;
219	}	219	}
220		220
221	void setImmKindNone() const {	221	void setImmKindNone() const {
222	assert(isImm());	222	assert(isImm());
223	Imm.Kind = ImmKindTyNone;	223	Imm.Kind = ImmKindTyNone;
224	}	224	}
225		225
226	void setImmKindLiteral() const {	226	void setImmKindLiteral() const {
227	assert(isImm());	227	assert(isImm());
228	Imm.Kind = ImmKindTyLiteral;	228	Imm.Kind = ImmKindTyLiteral;
229	}	229	}
230		230
231	void setImmKindMandatoryLiteral() const {	231	void setImmKindMandatoryLiteral() const {
232	assert(isImm());	232	assert(isImm());
233	Imm.Kind = ImmKindTyMandatoryLiteral;	233	Imm.Kind = ImmKindTyMandatoryLiteral;
234	}	234	}
235		235
236	void setImmKindConst() const {	236	void setImmKindConst() const {
237	assert(isImm());	237	assert(isImm());
238	Imm.Kind = ImmKindTyConst;	238	Imm.Kind = ImmKindTyConst;
239	}	239	}
240		240
241	bool IsImmKindLiteral() const {	241	bool IsImmKindLiteral() const {
242	return isImm() && Imm.Kind == ImmKindTyLiteral;	242	return isImm() && Imm.Kind == ImmKindTyLiteral;
243	}	243	}
244		244
245	bool IsImmKindMandatoryLiteral() const {	245	bool IsImmKindMandatoryLiteral() const {
246	return isImm() && Imm.Kind == ImmKindTyMandatoryLiteral;	246	return isImm() && Imm.Kind == ImmKindTyMandatoryLiteral;
247	}	247	}
248		248
249	bool isImmKindConst() const {	249	bool isImmKindConst() const {
250	return isImm() && Imm.Kind == ImmKindTyConst;	250	return isImm() && Imm.Kind == ImmKindTyConst;
251	}	251	}
252		252
253	bool isInlinableImm(MVT type) const;	253	bool isInlinableImm(MVT type) const;
254	bool isLiteralImm(MVT type) const;	254	bool isLiteralImm(MVT type) const;
255		255
256	bool isRegKind() const {	256	bool isRegKind() const {
257	return Kind == Register;	257	return Kind == Register;
258	}	258	}
259		259
260	bool isReg() const override {	260	bool isReg() const override {
261	return isRegKind() && !hasModifiers();	261	return isRegKind() && !hasModifiers();
262	}	262	}
263		263
264	bool isRegOrInline(unsigned RCID, MVT type) const {	264	bool isRegOrInline(unsigned RCID, MVT type) const {
265	return isRegClass(RCID) \|\| isInlinableImm(type);	265	return isRegClass(RCID) \|\| isInlinableImm(type);
266	}	266	}
267		267
268	bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {	268	bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {
269	return isRegOrInline(RCID, type) \|\| isLiteralImm(type);	269	return isRegOrInline(RCID, type) \|\| isLiteralImm(type);
270	}	270	}
271		271
272	bool isRegOrImmWithInt16InputMods() const {	272	bool isRegOrImmWithInt16InputMods() const {
273	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);	273	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);
274	}	274	}
275		275
276	bool isRegOrImmWithInt32InputMods() const {	276	bool isRegOrImmWithInt32InputMods() const {
277	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);	277	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);
278	}	278	}
279		279
280	bool isRegOrInlineImmWithInt16InputMods() const {	280	bool isRegOrInlineImmWithInt16InputMods() const {
281	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16);	281	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16);
282	}	282	}
283		283
284	bool isRegOrInlineImmWithInt32InputMods() const {	284	bool isRegOrInlineImmWithInt32InputMods() const {
285	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32);	285	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32);
286	}	286	}
287		287
288	bool isRegOrImmWithInt64InputMods() const {	288	bool isRegOrImmWithInt64InputMods() const {
289	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);	289	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);
290	}	290	}
291		291
292	bool isRegOrImmWithFP16InputMods() const {	292	bool isRegOrImmWithFP16InputMods() const {
293	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);	293	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);
294	}	294	}
295		295
296	bool isRegOrImmWithFP32InputMods() const {	296	bool isRegOrImmWithFP32InputMods() const {
297	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);	297	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);
298	}	298	}
299		299
300	bool isRegOrImmWithFP64InputMods() const {	300	bool isRegOrImmWithFP64InputMods() const {
301	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);	301	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);
302	}	302	}
303		303
304	bool isRegOrInlineImmWithFP16InputMods() const {	304	bool isRegOrInlineImmWithFP16InputMods() const {
305	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16);	305	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16);
306	}	306	}
307		307
308	bool isRegOrInlineImmWithFP32InputMods() const {	308	bool isRegOrInlineImmWithFP32InputMods() const {
309	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32);	309	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32);
310	}	310	}
311		311
312		312
313	bool isVReg() const {	313	bool isVReg() const {
314	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	314	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|
315	isRegClass(AMDGPU::VReg_64RegClassID) \|\|	315	isRegClass(AMDGPU::VReg_64RegClassID) \|\|
316	isRegClass(AMDGPU::VReg_96RegClassID) \|\|	316	isRegClass(AMDGPU::VReg_96RegClassID) \|\|
317	isRegClass(AMDGPU::VReg_128RegClassID) \|\|	317	isRegClass(AMDGPU::VReg_128RegClassID) \|\|
318	isRegClass(AMDGPU::VReg_160RegClassID) \|\|	318	isRegClass(AMDGPU::VReg_160RegClassID) \|\|
319	isRegClass(AMDGPU::VReg_192RegClassID) \|\|	319	isRegClass(AMDGPU::VReg_192RegClassID) \|\|
320	isRegClass(AMDGPU::VReg_256RegClassID) \|\|	320	isRegClass(AMDGPU::VReg_256RegClassID) \|\|
321	isRegClass(AMDGPU::VReg_512RegClassID) \|\|	321	isRegClass(AMDGPU::VReg_512RegClassID) \|\|
322	isRegClass(AMDGPU::VReg_1024RegClassID);	322	isRegClass(AMDGPU::VReg_1024RegClassID);
323	}	323	}
324		324
325	bool isVReg32() const {	325	bool isVReg32() const {
326	return isRegClass(AMDGPU::VGPR_32RegClassID);	326	return isRegClass(AMDGPU::VGPR_32RegClassID);
327	}	327	}
328		328
329	bool isVReg32OrOff() const {	329	bool isVReg32OrOff() const {
330	return isOff() \|\| isVReg32();	330	return isOff() \|\| isVReg32();
331	}	331	}
332		332
333	bool isNull() const {	333	bool isNull() const {
334	return isRegKind() && getReg() == AMDGPU::SGPR_NULL;	334	return isRegKind() && getReg() == AMDGPU::SGPR_NULL;
335	}	335	}
336		336
337	bool isVRegWithInputMods() const;	337	bool isVRegWithInputMods() const;
338	bool isT16VRegWithInputMods() const;	338	bool isT16VRegWithInputMods() const;
339		339
340	bool isSDWAOperand(MVT type) const;	340	bool isSDWAOperand(MVT type) const;
341	bool isSDWAFP16Operand() const;	341	bool isSDWAFP16Operand() const;
342	bool isSDWAFP32Operand() const;	342	bool isSDWAFP32Operand() const;
343	bool isSDWAInt16Operand() const;	343	bool isSDWAInt16Operand() const;
344	bool isSDWAInt32Operand() const;	344	bool isSDWAInt32Operand() const;
345		345
346	bool isImmTy(ImmTy ImmT) const {	346	bool isImmTy(ImmTy ImmT) const {
347	return isImm() && Imm.Type == ImmT;	347	return isImm() && Imm.Type == ImmT;
348	}	348	}
349		349
350	bool isImmLiteral() const { return isImmTy(ImmTyNone); }	350	bool isImmLiteral() const { return isImmTy(ImmTyNone); }
351		351
352	bool isImmModifier() const {	352	bool isImmModifier() const {
353	return isImm() && Imm.Type != ImmTyNone;	353	return isImm() && Imm.Type != ImmTyNone;
354	}	354	}
355		355
356	bool isClampSI() const { return isImmTy(ImmTyClampSI); }	356	bool isClampSI() const { return isImmTy(ImmTyClampSI); }
357	bool isOModSI() const { return isImmTy(ImmTyOModSI); }	357	bool isOModSI() const { return isImmTy(ImmTyOModSI); }
358	bool isDMask() const { return isImmTy(ImmTyDMask); }	358	bool isDMask() const { return isImmTy(ImmTyDMask); }
359	bool isDim() const { return isImmTy(ImmTyDim); }	359	bool isDim() const { return isImmTy(ImmTyDim); }
360	bool isUNorm() const { return isImmTy(ImmTyUNorm); }	360	bool isUNorm() const { return isImmTy(ImmTyUNorm); }
361	bool isDA() const { return isImmTy(ImmTyDA); }	361	bool isDA() const { return isImmTy(ImmTyDA); }
362	bool isR128A16() const { return isImmTy(ImmTyR128A16); }	362	bool isR128A16() const { return isImmTy(ImmTyR128A16); }
363	bool isA16() const { return isImmTy(ImmTyA16); }	363	bool isA16() const { return isImmTy(ImmTyA16); }
364	bool isLWE() const { return isImmTy(ImmTyLWE); }	364	bool isLWE() const { return isImmTy(ImmTyLWE); }
365	bool isOff() const { return isImmTy(ImmTyOff); }	365	bool isOff() const { return isImmTy(ImmTyOff); }
366	bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }	366	bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }
367	bool isExpVM() const { return isImmTy(ImmTyExpVM); }	367	bool isExpVM() const { return isImmTy(ImmTyExpVM); }
368	bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }	368	bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }
369	bool isOffen() const { return isImmTy(ImmTyOffen); }	369	bool isOffen() const { return isImmTy(ImmTyOffen); }
370	bool isIdxen() const { return isImmTy(ImmTyIdxen); }	370	bool isIdxen() const { return isImmTy(ImmTyIdxen); }
371	bool isAddr64() const { return isImmTy(ImmTyAddr64); }	371	bool isAddr64() const { return isImmTy(ImmTyAddr64); }
372	bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }	372	bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }
373	bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }	373	bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }
374	bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }	374	bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }
375	bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }	375	bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }
376	bool isFlatOffset() const { return isImmTy(ImmTyOffset) \|\| isImmTy(ImmTyInstOffset); }	376	bool isFlatOffset() const { return isImmTy(ImmTyOffset) \|\| isImmTy(ImmTyInstOffset); }
377	bool isGDS() const { return isImmTy(ImmTyGDS); }	377	bool isGDS() const { return isImmTy(ImmTyGDS); }
378	bool isLDS() const { return isImmTy(ImmTyLDS); }	378	bool isLDS() const { return isImmTy(ImmTyLDS); }
379	bool isCPol() const { return isImmTy(ImmTyCPol); }	379	bool isCPol() const { return isImmTy(ImmTyCPol); }
380	bool isTFE() const { return isImmTy(ImmTyTFE); }	380	bool isTFE() const { return isImmTy(ImmTyTFE); }
381	bool isD16() const { return isImmTy(ImmTyD16); }	381	bool isD16() const { return isImmTy(ImmTyD16); }
382	bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }	382	bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }
383	bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }	383	bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }
384	bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }	384	bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }
385	bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }	385	bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }
386	bool isDppFI() const { return isImmTy(ImmTyDppFI); }	386	bool isDppFI() const { return isImmTy(ImmTyDppFI); }
387	bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }	387	bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }
388	bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }	388	bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }
389	bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); }	389	bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); }
390	bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }	390	bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }
391	bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }	391	bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }
392	bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }	392	bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }
393	bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }	393	bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }
394	bool isOpSel() const { return isImmTy(ImmTyOpSel); }	394	bool isOpSel() const { return isImmTy(ImmTyOpSel); }
395	bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }	395	bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }
396	bool isNegLo() const { return isImmTy(ImmTyNegLo); }	396	bool isNegLo() const { return isImmTy(ImmTyNegLo); }
397	bool isNegHi() const { return isImmTy(ImmTyNegHi); }	397	bool isNegHi() const { return isImmTy(ImmTyNegHi); }
398	bool isHigh() const { return isImmTy(ImmTyHigh); }	398	bool isHigh() const { return isImmTy(ImmTyHigh); }
399		399
400	bool isRegOrImm() const {	400	bool isRegOrImm() const {
401	return isReg() \|\| isImm();	401	return isReg() \|\| isImm();
402	}	402	}
403		403
404	bool isRegClass(unsigned RCID) const;	404	bool isRegClass(unsigned RCID) const;
405		405
406	bool isInlineValue() const;	406	bool isInlineValue() const;
407		407
408	bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {	408	bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {
409	return isRegOrInline(RCID, type) && !hasModifiers();	409	return isRegOrInline(RCID, type) && !hasModifiers();
410	}	410	}
411		411
412	bool isSCSrcB16() const {	412	bool isSCSrcB16() const {
413	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);	413	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);
414	}	414	}
415		415
416	bool isSCSrcV2B16() const {	416	bool isSCSrcV2B16() const {
417	return isSCSrcB16();	417	return isSCSrcB16();
418	}	418	}
419		419
420	bool isSCSrcB32() const {	420	bool isSCSrcB32() const {
421	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);	421	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);
422	}	422	}
423		423
424	bool isSCSrcB64() const {	424	bool isSCSrcB64() const {
425	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);	425	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);
426	}	426	}
427		427
428	bool isBoolReg() const;	428	bool isBoolReg() const;
429		429
430	bool isSCSrcF16() const {	430	bool isSCSrcF16() const {
431	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);	431	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);
432	}	432	}
433		433
434	bool isSCSrcV2F16() const {	434	bool isSCSrcV2F16() const {
435	return isSCSrcF16();	435	return isSCSrcF16();
436	}	436	}
437		437
438	bool isSCSrcF32() const {	438	bool isSCSrcF32() const {
439	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);	439	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);
440	}	440	}
441		441
442	bool isSCSrcF64() const {	442	bool isSCSrcF64() const {
443	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);	443	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);
444	}	444	}
445		445
446	bool isSSrcB32() const {	446	bool isSSrcB32() const {
447	return isSCSrcB32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	447	return isSCSrcB32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();
448	}	448	}
449		449
450	bool isSSrcB16() const {	450	bool isSSrcB16() const {
451	return isSCSrcB16() \|\| isLiteralImm(MVT::i16);	451	return isSCSrcB16() \|\| isLiteralImm(MVT::i16);
452	}	452	}
453		453
454	bool isSSrcV2B16() const {	454	bool isSSrcV2B16() const {
455	llvm_unreachable("cannot happen");	455	llvm_unreachable("cannot happen");
456	return isSSrcB16();	456	return isSSrcB16();
457	}	457	}
458		458
459	bool isSSrcB64() const {	459	bool isSSrcB64() const {
460	// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.	460	// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.
461	// See isVSrc64().	461	// See isVSrc64().
462	return isSCSrcB64() \|\| isLiteralImm(MVT::i64);	462	return isSCSrcB64() \|\| isLiteralImm(MVT::i64);
463	}	463	}
464		464
465	bool isSSrcF32() const {	465	bool isSSrcF32() const {
466	return isSCSrcB32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	466	return isSCSrcB32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();
467	}	467	}
468		468
469	bool isSSrcF64() const {	469	bool isSSrcF64() const {
470	return isSCSrcB64() \|\| isLiteralImm(MVT::f64);	470	return isSCSrcB64() \|\| isLiteralImm(MVT::f64);
471	}	471	}
472		472
473	bool isSSrcF16() const {	473	bool isSSrcF16() const {
474	return isSCSrcB16() \|\| isLiteralImm(MVT::f16);	474	return isSCSrcB16() \|\| isLiteralImm(MVT::f16);
475	}	475	}
476		476
477	bool isSSrcV2F16() const {	477	bool isSSrcV2F16() const {
478	llvm_unreachable("cannot happen");	478	llvm_unreachable("cannot happen");
479	return isSSrcF16();	479	return isSSrcF16();
480	}	480	}
481		481
482	bool isSSrcV2FP32() const {	482	bool isSSrcV2FP32() const {
483	llvm_unreachable("cannot happen");	483	llvm_unreachable("cannot happen");
484	return isSSrcF32();	484	return isSSrcF32();
485	}	485	}
486		486
487	bool isSCSrcV2FP32() const {	487	bool isSCSrcV2FP32() const {
488	llvm_unreachable("cannot happen");	488	llvm_unreachable("cannot happen");
489	return isSCSrcF32();	489	return isSCSrcF32();
490	}	490	}
491		491
492	bool isSSrcV2INT32() const {	492	bool isSSrcV2INT32() const {
493	llvm_unreachable("cannot happen");	493	llvm_unreachable("cannot happen");
494	return isSSrcB32();	494	return isSSrcB32();
495	}	495	}
496		496
497	bool isSCSrcV2INT32() const {	497	bool isSCSrcV2INT32() const {
498	llvm_unreachable("cannot happen");	498	llvm_unreachable("cannot happen");
499	return isSCSrcB32();	499	return isSCSrcB32();
500	}	500	}
501		501
502	bool isSSrcOrLdsB32() const {	502	bool isSSrcOrLdsB32() const {
503	return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) \|\|	503	return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) \|\|
504	isLiteralImm(MVT::i32) \|\| isExpr();	504	isLiteralImm(MVT::i32) \|\| isExpr();
505	}	505	}
506		506
507	bool isVCSrcB32() const {	507	bool isVCSrcB32() const {
508	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);	508	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);
509	}	509	}
510		510
511	bool isVCSrcB64() const {	511	bool isVCSrcB64() const {
512	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);	512	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);
513	}	513	}
514		514
515	bool isVCSrcTB16_Lo128() const {	515	bool isVCSrcTB16_Lo128() const {
516	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16);	516	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16);
517	}	517	}
518		518
519	bool isVCSrcB16() const {	519	bool isVCSrcB16() const {
520	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16);	520	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16);
521	}	521	}
522		522
523	bool isVCSrcV2B16() const {	523	bool isVCSrcV2B16() const {
524	return isVCSrcB16();	524	return isVCSrcB16();
525	}	525	}
526		526
527	bool isVCSrcF32() const {	527	bool isVCSrcF32() const {
528	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);	528	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);
529	}	529	}
530		530
531	bool isVCSrcF64() const {	531	bool isVCSrcF64() const {
532	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);	532	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);
533	}	533	}
534		534
535	bool isVCSrcTF16_Lo128() const {	535	bool isVCSrcTF16_Lo128() const {
536	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16);	536	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16);
537	}	537	}
538		538
539	bool isVCSrcF16() const {	539	bool isVCSrcF16() const {
540	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);	540	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);
541	}	541	}
542		542
543	bool isVCSrcV2F16() const {	543	bool isVCSrcV2F16() const {
544	return isVCSrcF16();	544	return isVCSrcF16();
545	}	545	}
546		546
547	bool isVSrcB32() const {	547	bool isVSrcB32() const {
548	return isVCSrcF32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	548	return isVCSrcF32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();
549	}	549	}
550		550
551	bool isVSrcB64() const {	551	bool isVSrcB64() const {
552	return isVCSrcF64() \|\| isLiteralImm(MVT::i64);	552	return isVCSrcF64() \|\| isLiteralImm(MVT::i64);
553	}	553	}
554		554
555	bool isVSrcTB16_Lo128() const {	555	bool isVSrcTB16_Lo128() const {
556	return isVCSrcTB16_Lo128() \|\| isLiteralImm(MVT::i16);	556	return isVCSrcTB16_Lo128() \|\| isLiteralImm(MVT::i16);
557	}	557	}
558		558
559	bool isVSrcB16() const {	559	bool isVSrcB16() const {
560	return isVCSrcB16() \|\| isLiteralImm(MVT::i16);	560	return isVCSrcB16() \|\| isLiteralImm(MVT::i16);
561	}	561	}
562		562
563	bool isVSrcV2B16() const {	563	bool isVSrcV2B16() const {
564	return isVSrcB16() \|\| isLiteralImm(MVT::v2i16);	564	return isVSrcB16() \|\| isLiteralImm(MVT::v2i16);
565	}	565	}
566		566
567	bool isVCSrcV2FP32() const {	567	bool isVCSrcV2FP32() const {
568	return isVCSrcF64();	568	return isVCSrcF64();
569	}	569	}
570		570
571	bool isVSrcV2FP32() const {	571	bool isVSrcV2FP32() const {
572	return isVSrcF64() \|\| isLiteralImm(MVT::v2f32);	572	return isVSrcF64() \|\| isLiteralImm(MVT::v2f32);
573	}	573	}
574		574
575	bool isVCSrcV2INT32() const {	575	bool isVCSrcV2INT32() const {
576	return isVCSrcB64();	576	return isVCSrcB64();
577	}	577	}
578		578
579	bool isVSrcV2INT32() const {	579	bool isVSrcV2INT32() const {
580	return isVSrcB64() \|\| isLiteralImm(MVT::v2i32);	580	return isVSrcB64() \|\| isLiteralImm(MVT::v2i32);
581	}	581	}
582		582
583	bool isVSrcF32() const {	583	bool isVSrcF32() const {
584	return isVCSrcF32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	584	return isVCSrcF32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();
585	}	585	}
586		586
587	bool isVSrcF64() const {	587	bool isVSrcF64() const {
588	return isVCSrcF64() \|\| isLiteralImm(MVT::f64);	588	return isVCSrcF64() \|\| isLiteralImm(MVT::f64);
589	}	589	}
590		590
591	bool isVSrcTF16_Lo128() const {	591	bool isVSrcTF16_Lo128() const {
592	return isVCSrcTF16_Lo128() \|\| isLiteralImm(MVT::f16);	592	return isVCSrcTF16_Lo128() \|\| isLiteralImm(MVT::f16);
593	}	593	}
594		594
595	bool isVSrcF16() const {	595	bool isVSrcF16() const {
596	return isVCSrcF16() \|\| isLiteralImm(MVT::f16);	596	return isVCSrcF16() \|\| isLiteralImm(MVT::f16);
597	}	597	}
598		598
599	bool isVSrcV2F16() const {	599	bool isVSrcV2F16() const {
600	return isVSrcF16() \|\| isLiteralImm(MVT::v2f16);	600	return isVSrcF16() \|\| isLiteralImm(MVT::v2f16);
601	}	601	}
602		602
603	bool isVISrcB32() const {	603	bool isVISrcB32() const {
604	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32);	604	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32);
605	}	605	}
606		606
607	bool isVISrcB16() const {	607	bool isVISrcB16() const {
608	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16);	608	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16);
609	}	609	}
610		610
611	bool isVISrcV2B16() const {	611	bool isVISrcV2B16() const {
612	return isVISrcB16();	612	return isVISrcB16();
613	}	613	}
614		614
615	bool isVISrcF32() const {	615	bool isVISrcF32() const {
616	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32);	616	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32);
617	}	617	}
618		618
619	bool isVISrcF16() const {	619	bool isVISrcF16() const {
620	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16);	620	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16);
621	}	621	}
622		622
623	bool isVISrcV2F16() const {	623	bool isVISrcV2F16() const {
624	return isVISrcF16() \|\| isVISrcB32();	624	return isVISrcF16() \|\| isVISrcB32();
625	}	625	}
626		626
627	bool isVISrc_64B64() const {	627	bool isVISrc_64B64() const {
628	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64);	628	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64);
629	}	629	}
630		630
631	bool isVISrc_64F64() const {	631	bool isVISrc_64F64() const {
632	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64);	632	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64);
633	}	633	}
634		634
635	bool isVISrc_64V2FP32() const {	635	bool isVISrc_64V2FP32() const {
636	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32);	636	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32);
637	}	637	}
638		638
639	bool isVISrc_64V2INT32() const {	639	bool isVISrc_64V2INT32() const {
640	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32);	640	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32);
641	}	641	}
642		642
643	bool isVISrc_256B64() const {	643	bool isVISrc_256B64() const {
644	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64);	644	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64);
645	}	645	}
646		646
647	bool isVISrc_256F64() const {	647	bool isVISrc_256F64() const {
648	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64);	648	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64);
649	}	649	}
650		650
651	bool isVISrc_128B16() const {	651	bool isVISrc_128B16() const {
652	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16);	652	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16);
653	}	653	}
654		654
655	bool isVISrc_128V2B16() const {	655	bool isVISrc_128V2B16() const {
656	return isVISrc_128B16();	656	return isVISrc_128B16();
657	}	657	}
658		658
659	bool isVISrc_128B32() const {	659	bool isVISrc_128B32() const {
660	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32);	660	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32);
661	}	661	}
662		662
663	bool isVISrc_128F32() const {	663	bool isVISrc_128F32() const {
664	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32);	664	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32);
665	}	665	}
666		666
667	bool isVISrc_256V2FP32() const {	667	bool isVISrc_256V2FP32() const {
668	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32);	668	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32);
669	}	669	}
670		670
671	bool isVISrc_256V2INT32() const {	671	bool isVISrc_256V2INT32() const {
672	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32);	672	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32);
673	}	673	}
674		674
675	bool isVISrc_512B32() const {	675	bool isVISrc_512B32() const {
676	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32);	676	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32);
677	}	677	}
678		678
679	bool isVISrc_512B16() const {	679	bool isVISrc_512B16() const {
680	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16);	680	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16);
681	}	681	}
682		682
683	bool isVISrc_512V2B16() const {	683	bool isVISrc_512V2B16() const {
684	return isVISrc_512B16();	684	return isVISrc_512B16();
685	}	685	}
686		686
687	bool isVISrc_512F32() const {	687	bool isVISrc_512F32() const {
688	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32);	688	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32);
689	}	689	}
690		690
691	bool isVISrc_512F16() const {	691	bool isVISrc_512F16() const {
692	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16);	692	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16);
693	}	693	}
694		694
695	bool isVISrc_512V2F16() const {	695	bool isVISrc_512V2F16() const {
696	return isVISrc_512F16() \|\| isVISrc_512B32();	696	return isVISrc_512F16() \|\| isVISrc_512B32();
697	}	697	}
698		698
699	bool isVISrc_1024B32() const {	699	bool isVISrc_1024B32() const {
700	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32);	700	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32);
701	}	701	}
702		702
703	bool isVISrc_1024B16() const {	703	bool isVISrc_1024B16() const {
704	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16);	704	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16);
705	}	705	}
706		706
707	bool isVISrc_1024V2B16() const {	707	bool isVISrc_1024V2B16() const {
708	return isVISrc_1024B16();	708	return isVISrc_1024B16();
709	}	709	}
710		710
711	bool isVISrc_1024F32() const {	711	bool isVISrc_1024F32() const {
712	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32);	712	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32);
713	}	713	}
714		714
715	bool isVISrc_1024F16() const {	715	bool isVISrc_1024F16() const {
716	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16);	716	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16);
717	}	717	}
718		718
719	bool isVISrc_1024V2F16() const {	719	bool isVISrc_1024V2F16() const {
720	return isVISrc_1024F16() \|\| isVISrc_1024B32();	720	return isVISrc_1024F16() \|\| isVISrc_1024B32();
721	}	721	}
722		722
723	bool isAISrcB32() const {	723	bool isAISrcB32() const {
724	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32);	724	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32);
725	}	725	}
726		726
727	bool isAISrcB16() const {	727	bool isAISrcB16() const {
728	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16);	728	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16);
729	}	729	}
730		730
731	bool isAISrcV2B16() const {	731	bool isAISrcV2B16() const {
732	return isAISrcB16();	732	return isAISrcB16();
733	}	733	}
734		734
735	bool isAISrcF32() const {	735	bool isAISrcF32() const {
736	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);	736	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);
737	}	737	}
738		738
739	bool isAISrcF16() const {	739	bool isAISrcF16() const {
740	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);	740	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);
741	}	741	}
742		742
743	bool isAISrcV2F16() const {	743	bool isAISrcV2F16() const {
744	return isAISrcF16() \|\| isAISrcB32();	744	return isAISrcF16() \|\| isAISrcB32();
745	}	745	}
746		746
747	bool isAISrc_64B64() const {	747	bool isAISrc_64B64() const {
748	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64);	748	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64);
749	}	749	}
750		750
751	bool isAISrc_64F64() const {	751	bool isAISrc_64F64() const {
752	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64);	752	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64);
753	}	753	}
754		754
755	bool isAISrc_128B32() const {	755	bool isAISrc_128B32() const {
756	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32);	756	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32);
757	}	757	}
758		758
759	bool isAISrc_128B16() const {	759	bool isAISrc_128B16() const {
760	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16);	760	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16);
761	}	761	}
762		762
763	bool isAISrc_128V2B16() const {	763	bool isAISrc_128V2B16() const {
764	return isAISrc_128B16();	764	return isAISrc_128B16();
765	}	765	}
766		766
767	bool isAISrc_128F32() const {	767	bool isAISrc_128F32() const {
768	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);	768	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);
769	}	769	}
770		770
771	bool isAISrc_128F16() const {	771	bool isAISrc_128F16() const {
772	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);	772	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);
773	}	773	}
774		774
775	bool isAISrc_128V2F16() const {	775	bool isAISrc_128V2F16() const {
776	return isAISrc_128F16() \|\| isAISrc_128B32();	776	return isAISrc_128F16() \|\| isAISrc_128B32();
777	}	777	}
778		778
779	bool isVISrc_128F16() const {	779	bool isVISrc_128F16() const {
780	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16);	780	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16);
781	}	781	}
782		782
783	bool isVISrc_128V2F16() const {	783	bool isVISrc_128V2F16() const {
784	return isVISrc_128F16() \|\| isVISrc_128B32();	784	return isVISrc_128F16() \|\| isVISrc_128B32();
785	}	785	}
786		786
787	bool isAISrc_256B64() const {	787	bool isAISrc_256B64() const {
788	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64);	788	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64);
789	}	789	}
790		790
791	bool isAISrc_256F64() const {	791	bool isAISrc_256F64() const {
792	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64);	792	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64);
793	}	793	}
794		794
795	bool isAISrc_512B32() const {	795	bool isAISrc_512B32() const {
796	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32);	796	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32);
797	}	797	}
798		798
799	bool isAISrc_512B16() const {	799	bool isAISrc_512B16() const {
800	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16);	800	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16);
801	}	801	}
802		802
803	bool isAISrc_512V2B16() const {	803	bool isAISrc_512V2B16() const {
804	return isAISrc_512B16();	804	return isAISrc_512B16();
805	}	805	}
806		806
807	bool isAISrc_512F32() const {	807	bool isAISrc_512F32() const {
808	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);	808	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);
809	}	809	}
810		810
811	bool isAISrc_512F16() const {	811	bool isAISrc_512F16() const {
812	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);	812	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);
813	}	813	}
814		814
815	bool isAISrc_512V2F16() const {	815	bool isAISrc_512V2F16() const {
816	return isAISrc_512F16() \|\| isAISrc_512B32();	816	return isAISrc_512F16() \|\| isAISrc_512B32();
817	}	817	}
818		818
819	bool isAISrc_1024B32() const {	819	bool isAISrc_1024B32() const {
820	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32);	820	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32);
821	}	821	}
822		822
823	bool isAISrc_1024B16() const {	823	bool isAISrc_1024B16() const {
824	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16);	824	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16);
825	}	825	}
826		826
827	bool isAISrc_1024V2B16() const {	827	bool isAISrc_1024V2B16() const {
828	return isAISrc_1024B16();	828	return isAISrc_1024B16();
829	}	829	}
830		830
831	bool isAISrc_1024F32() const {	831	bool isAISrc_1024F32() const {
832	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);	832	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);
833	}	833	}
834		834
835	bool isAISrc_1024F16() const {	835	bool isAISrc_1024F16() const {
836	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);	836	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);
837	}	837	}
838		838
839	bool isAISrc_1024V2F16() const {	839	bool isAISrc_1024V2F16() const {
840	return isAISrc_1024F16() \|\| isAISrc_1024B32();	840	return isAISrc_1024F16() \|\| isAISrc_1024B32();
841	}	841	}
842		842
843	bool isKImmFP32() const {	843	bool isKImmFP32() const {
844	return isLiteralImm(MVT::f32);	844	return isLiteralImm(MVT::f32);
845	}	845	}
846		846
847	bool isKImmFP16() const {	847	bool isKImmFP16() const {
848	return isLiteralImm(MVT::f16);	848	return isLiteralImm(MVT::f16);
849	}	849	}
850		850
851	bool isMem() const override {	851	bool isMem() const override {
852	return false;	852	return false;
853	}	853	}
854		854
855	bool isExpr() const {	855	bool isExpr() const {
856	return Kind == Expression;	856	return Kind == Expression;
857	}	857	}
858		858
859	bool isSOPPBrTarget() const { return isExpr() \|\| isImm(); }	859	bool isSOPPBrTarget() const { return isExpr() \|\| isImm(); }
860		860
861	bool isSWaitCnt() const;	861	bool isSWaitCnt() const;
862	bool isDepCtr() const;	862	bool isDepCtr() const;
863	bool isSDelayALU() const;	863	bool isSDelayALU() const;
864	bool isHwreg() const;	864	bool isHwreg() const;
865	bool isSendMsg() const;	865	bool isSendMsg() const;
866	bool isSwizzle() const;	866	bool isSwizzle() const;
867	bool isSMRDOffset8() const;	867	bool isSMRDOffset8() const;
868	bool isSMEMOffset() const;	868	bool isSMEMOffset() const;
869	bool isSMRDLiteralOffset() const;	869	bool isSMRDLiteralOffset() const;
870	bool isDPP8() const;	870	bool isDPP8() const;
871	bool isDPPCtrl() const;	871	bool isDPPCtrl() const;
872	bool isBLGP() const;	872	bool isBLGP() const;
873	bool isCBSZ() const;	873	bool isCBSZ() const;
874	bool isABID() const;	874	bool isABID() const;
875	bool isGPRIdxMode() const;	875	bool isGPRIdxMode() const;
876	bool isS16Imm() const;	876	bool isS16Imm() const;
877	bool isU16Imm() const;	877	bool isU16Imm() const;
878	bool isEndpgm() const;	878	bool isEndpgm() const;
879	bool isWaitVDST() const;	879	bool isWaitVDST() const;
880	bool isWaitEXP() const;	880	bool isWaitEXP() const;
881		881
882	StringRef getToken() const {	882	StringRef getToken() const {
883	assert(isToken());	883	assert(isToken());
884	return StringRef(Tok.Data, Tok.Length);	884	return StringRef(Tok.Data, Tok.Length);
885	}	885	}
886		886
887	int64_t getImm() const {	887	int64_t getImm() const {
888	assert(isImm());	888	assert(isImm());
889	return Imm.Val;	889	return Imm.Val;
890	}	890	}
891		891
892	void setImm(int64_t Val) {	892	void setImm(int64_t Val) {
893	assert(isImm());	893	assert(isImm());
894	Imm.Val = Val;	894	Imm.Val = Val;
895	}	895	}
896		896
897	ImmTy getImmTy() const {	897	ImmTy getImmTy() const {
898	assert(isImm());	898	assert(isImm());
899	return Imm.Type;	899	return Imm.Type;
900	}	900	}
901		901
902	unsigned getReg() const override {	902	unsigned getReg() const override {
903	assert(isRegKind());	903	assert(isRegKind());
904	return Reg.RegNo;	904	return Reg.RegNo;
905	}	905	}
906		906
907	SMLoc getStartLoc() const override {	907	SMLoc getStartLoc() const override {
908	return StartLoc;	908	return StartLoc;
909	}	909	}
910		910
911	SMLoc getEndLoc() const override {	911	SMLoc getEndLoc() const override {
912	return EndLoc;	912	return EndLoc;
913	}	913	}
914		914
915	SMRange getLocRange() const {	915	SMRange getLocRange() const {
916	return SMRange(StartLoc, EndLoc);	916	return SMRange(StartLoc, EndLoc);
917	}	917	}
918		918
919	Modifiers getModifiers() const {	919	Modifiers getModifiers() const {
920	assert(isRegKind() \|\| isImmTy(ImmTyNone));	920	assert(isRegKind() \|\| isImmTy(ImmTyNone));
921	return isRegKind() ? Reg.Mods : Imm.Mods;	921	return isRegKind() ? Reg.Mods : Imm.Mods;
922	}	922	}
923		923
924	void setModifiers(Modifiers Mods) {	924	void setModifiers(Modifiers Mods) {
925	assert(isRegKind() \|\| isImmTy(ImmTyNone));	925	assert(isRegKind() \|\| isImmTy(ImmTyNone));
926	if (isRegKind())	926	if (isRegKind())
927	Reg.Mods = Mods;	927	Reg.Mods = Mods;
928	else	928	else
929	Imm.Mods = Mods;	929	Imm.Mods = Mods;
930	}	930	}
931		931
932	bool hasModifiers() const {	932	bool hasModifiers() const {
933	return getModifiers().hasModifiers();	933	return getModifiers().hasModifiers();
934	}	934	}
935		935
936	bool hasFPModifiers() const {	936	bool hasFPModifiers() const {
937	return getModifiers().hasFPModifiers();	937	return getModifiers().hasFPModifiers();
938	}	938	}
939		939
940	bool hasIntModifiers() const {	940	bool hasIntModifiers() const {
941	return getModifiers().hasIntModifiers();	941	return getModifiers().hasIntModifiers();
942	}	942	}
943		943
944	uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;	944	uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;
945		945
946	void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;	946	void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;
947		947
948	void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;	948	void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;
949		949
950	void addRegOperands(MCInst &Inst, unsigned N) const;	950	void addRegOperands(MCInst &Inst, unsigned N) const;
951		951
952	void addRegOrImmOperands(MCInst &Inst, unsigned N) const {	952	void addRegOrImmOperands(MCInst &Inst, unsigned N) const {
953	if (isRegKind())	953	if (isRegKind())
954	addRegOperands(Inst, N);	954	addRegOperands(Inst, N);
955	else	955	else
956	addImmOperands(Inst, N);	956	addImmOperands(Inst, N);
957	}	957	}
958		958
959	void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {	959	void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {
960	Modifiers Mods = getModifiers();	960	Modifiers Mods = getModifiers();
961	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	961	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));
962	if (isRegKind()) {	962	if (isRegKind()) {
963	addRegOperands(Inst, N);	963	addRegOperands(Inst, N);
964	} else {	964	} else {
965	addImmOperands(Inst, N, false);	965	addImmOperands(Inst, N, false);
966	}	966	}
967	}	967	}
968		968
969	void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	969	void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {
970	assert(!hasIntModifiers());	970	assert(!hasIntModifiers());
971	addRegOrImmWithInputModsOperands(Inst, N);	971	addRegOrImmWithInputModsOperands(Inst, N);
972	}	972	}
973		973
974	void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	974	void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {
975	assert(!hasFPModifiers());	975	assert(!hasFPModifiers());
976	addRegOrImmWithInputModsOperands(Inst, N);	976	addRegOrImmWithInputModsOperands(Inst, N);
977	}	977	}
978		978
979	void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {	979	void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {
980	Modifiers Mods = getModifiers();	980	Modifiers Mods = getModifiers();
981	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	981	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));
982	assert(isRegKind());	982	assert(isRegKind());
983	addRegOperands(Inst, N);	983	addRegOperands(Inst, N);
984	}	984	}
985		985
986	void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	986	void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {
987	assert(!hasIntModifiers());	987	assert(!hasIntModifiers());
988	addRegWithInputModsOperands(Inst, N);	988	addRegWithInputModsOperands(Inst, N);
989	}	989	}
990		990
991	void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	991	void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {
992	assert(!hasFPModifiers());	992	assert(!hasFPModifiers());
993	addRegWithInputModsOperands(Inst, N);	993	addRegWithInputModsOperands(Inst, N);
994	}	994	}
995		995
996	static void printImmTy(raw_ostream& OS, ImmTy Type) {	996	static void printImmTy(raw_ostream& OS, ImmTy Type) {
997	switch (Type) {	997	switch (Type) {
998	case ImmTyNone: OS << "None"; break;	998	case ImmTyNone: OS << "None"; break;
999	case ImmTyGDS: OS << "GDS"; break;	999	case ImmTyGDS: OS << "GDS"; break;
1000	case ImmTyLDS: OS << "LDS"; break;	1000	case ImmTyLDS: OS << "LDS"; break;
1001	case ImmTyOffen: OS << "Offen"; break;	1001	case ImmTyOffen: OS << "Offen"; break;
1002	case ImmTyIdxen: OS << "Idxen"; break;	1002	case ImmTyIdxen: OS << "Idxen"; break;
1003	case ImmTyAddr64: OS << "Addr64"; break;	1003	case ImmTyAddr64: OS << "Addr64"; break;
1004	case ImmTyOffset: OS << "Offset"; break;	1004	case ImmTyOffset: OS << "Offset"; break;
1005	case ImmTyInstOffset: OS << "InstOffset"; break;	1005	case ImmTyInstOffset: OS << "InstOffset"; break;
1006	case ImmTyOffset0: OS << "Offset0"; break;	1006	case ImmTyOffset0: OS << "Offset0"; break;
1007	case ImmTyOffset1: OS << "Offset1"; break;	1007	case ImmTyOffset1: OS << "Offset1"; break;
1008	case ImmTySMEMOffsetMod: OS << "SMEMOffsetMod"; break;	1008	case ImmTySMEMOffsetMod: OS << "SMEMOffsetMod"; break;
1009	case ImmTyCPol: OS << "CPol"; break;	1009	case ImmTyCPol: OS << "CPol"; break;
1010	case ImmTyTFE: OS << "TFE"; break;	1010	case ImmTyTFE: OS << "TFE"; break;
1011	case ImmTyD16: OS << "D16"; break;	1011	case ImmTyD16: OS << "D16"; break;
1012	case ImmTyFORMAT: OS << "FORMAT"; break;	1012	case ImmTyFORMAT: OS << "FORMAT"; break;
1013	case ImmTyClampSI: OS << "ClampSI"; break;	1013	case ImmTyClampSI: OS << "ClampSI"; break;
1014	case ImmTyOModSI: OS << "OModSI"; break;	1014	case ImmTyOModSI: OS << "OModSI"; break;
1015	case ImmTyDPP8: OS << "DPP8"; break;	1015	case ImmTyDPP8: OS << "DPP8"; break;
1016	case ImmTyDppCtrl: OS << "DppCtrl"; break;	1016	case ImmTyDppCtrl: OS << "DppCtrl"; break;
1017	case ImmTyDppRowMask: OS << "DppRowMask"; break;	1017	case ImmTyDppRowMask: OS << "DppRowMask"; break;
1018	case ImmTyDppBankMask: OS << "DppBankMask"; break;	1018	case ImmTyDppBankMask: OS << "DppBankMask"; break;
1019	case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;	1019	case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;
1020	case ImmTyDppFI: OS << "DppFI"; break;	1020	case ImmTyDppFI: OS << "DppFI"; break;
1021	case ImmTySDWADstSel: OS << "SDWADstSel"; break;	1021	case ImmTySDWADstSel: OS << "SDWADstSel"; break;
1022	case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break;	1022	case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break;
1023	case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break;	1023	case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break;
1024	case ImmTySDWADstUnused: OS << "SDWADstUnused"; break;	1024	case ImmTySDWADstUnused: OS << "SDWADstUnused"; break;
1025	case ImmTyDMask: OS << "DMask"; break;	1025	case ImmTyDMask: OS << "DMask"; break;
1026	case ImmTyDim: OS << "Dim"; break;	1026	case ImmTyDim: OS << "Dim"; break;
1027	case ImmTyUNorm: OS << "UNorm"; break;	1027	case ImmTyUNorm: OS << "UNorm"; break;
1028	case ImmTyDA: OS << "DA"; break;	1028	case ImmTyDA: OS << "DA"; break;
1029	case ImmTyR128A16: OS << "R128A16"; break;	1029	case ImmTyR128A16: OS << "R128A16"; break;
1030	case ImmTyA16: OS << "A16"; break;	1030	case ImmTyA16: OS << "A16"; break;
1031	case ImmTyLWE: OS << "LWE"; break;	1031	case ImmTyLWE: OS << "LWE"; break;
1032	case ImmTyOff: OS << "Off"; break;	1032	case ImmTyOff: OS << "Off"; break;
1033	case ImmTyExpTgt: OS << "ExpTgt"; break;	1033	case ImmTyExpTgt: OS << "ExpTgt"; break;
1034	case ImmTyExpCompr: OS << "ExpCompr"; break;	1034	case ImmTyExpCompr: OS << "ExpCompr"; break;
1035	case ImmTyExpVM: OS << "ExpVM"; break;	1035	case ImmTyExpVM: OS << "ExpVM"; break;
1036	case ImmTyHwreg: OS << "Hwreg"; break;	1036	case ImmTyHwreg: OS << "Hwreg"; break;
1037	case ImmTySendMsg: OS << "SendMsg"; break;	1037	case ImmTySendMsg: OS << "SendMsg"; break;
1038	case ImmTyInterpSlot: OS << "InterpSlot"; break;	1038	case ImmTyInterpSlot: OS << "InterpSlot"; break;
1039	case ImmTyInterpAttr: OS << "InterpAttr"; break;	1039	case ImmTyInterpAttr: OS << "InterpAttr"; break;
1040	case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;	1040	case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;
1041	case ImmTyOpSel: OS << "OpSel"; break;	1041	case ImmTyOpSel: OS << "OpSel"; break;
1042	case ImmTyOpSelHi: OS << "OpSelHi"; break;	1042	case ImmTyOpSelHi: OS << "OpSelHi"; break;
1043	case ImmTyNegLo: OS << "NegLo"; break;	1043	case ImmTyNegLo: OS << "NegLo"; break;
1044	case ImmTyNegHi: OS << "NegHi"; break;	1044	case ImmTyNegHi: OS << "NegHi"; break;
1045	case ImmTySwizzle: OS << "Swizzle"; break;	1045	case ImmTySwizzle: OS << "Swizzle"; break;
1046	case ImmTyGprIdxMode: OS << "GprIdxMode"; break;	1046	case ImmTyGprIdxMode: OS << "GprIdxMode"; break;
1047	case ImmTyHigh: OS << "High"; break;	1047	case ImmTyHigh: OS << "High"; break;
1048	case ImmTyBLGP: OS << "BLGP"; break;	1048	case ImmTyBLGP: OS << "BLGP"; break;
1049	case ImmTyCBSZ: OS << "CBSZ"; break;	1049	case ImmTyCBSZ: OS << "CBSZ"; break;
1050	case ImmTyABID: OS << "ABID"; break;	1050	case ImmTyABID: OS << "ABID"; break;
1051	case ImmTyEndpgm: OS << "Endpgm"; break;	1051	case ImmTyEndpgm: OS << "Endpgm"; break;
1052	case ImmTyWaitVDST: OS << "WaitVDST"; break;	1052	case ImmTyWaitVDST: OS << "WaitVDST"; break;
1053	case ImmTyWaitEXP: OS << "WaitEXP"; break;	1053	case ImmTyWaitEXP: OS << "WaitEXP"; break;
1054	}	1054	}
1055	}	1055	}
1056		1056
1057	void print(raw_ostream &OS) const override {	1057	void print(raw_ostream &OS) const override {
1058	switch (Kind) {	1058	switch (Kind) {
1059	case Register:	1059	case Register:
1060	OS << "';	1060	OS << "';
1061	break;	1061	break;
1062	case Immediate:	1062	case Immediate:
1063	OS << '<' << getImm();	1063	OS << '<' << getImm();
1064	if (getImmTy() != ImmTyNone) {	1064	if (getImmTy() != ImmTyNone) {
1065	OS << " type: "; printImmTy(OS, getImmTy());	1065	OS << " type: "; printImmTy(OS, getImmTy());
1066	}	1066	}
1067	OS << " mods: " << Imm.Mods << '>';	1067	OS << " mods: " << Imm.Mods << '>';
1068	break;	1068	break;
1069	case Token:	1069	case Token:
1070	OS << '\'' << getToken() << '\'';	1070	OS << '\'' << getToken() << '\'';
1071	break;	1071	break;
1072	case Expression:	1072	case Expression:
1073	OS << "';	1073	OS << "';
1074	break;	1074	break;
1075	}	1075	}
1076	}	1076	}
1077		1077
1078	static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,	1078	static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,
1079	int64_t Val, SMLoc Loc,	1079	int64_t Val, SMLoc Loc,
1080	ImmTy Type = ImmTyNone,	1080	ImmTy Type = ImmTyNone,
1081	bool IsFPImm = false) {	1081	bool IsFPImm = false) {
1082	auto Op = std::make_unique(Immediate, AsmParser);	1082	auto Op = std::make_unique(Immediate, AsmParser);
1083	Op->Imm.Val = Val;	1083	Op->Imm.Val = Val;
1084	Op->Imm.IsFPImm = IsFPImm;	1084	Op->Imm.IsFPImm = IsFPImm;
1085	Op->Imm.Kind = ImmKindTyNone;	1085	Op->Imm.Kind = ImmKindTyNone;
1086	Op->Imm.Type = Type;	1086	Op->Imm.Type = Type;
1087	Op->Imm.Mods = Modifiers();	1087	Op->Imm.Mods = Modifiers();
1088	Op->StartLoc = Loc;	1088	Op->StartLoc = Loc;
1089	Op->EndLoc = Loc;	1089	Op->EndLoc = Loc;
1090	return Op;	1090	return Op;
1091	}	1091	}
1092		1092
1093	static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,	1093	static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,
1094	StringRef Str, SMLoc Loc,	1094	StringRef Str, SMLoc Loc,
1095	bool HasExplicitEncodingSize = true) {	1095	bool HasExplicitEncodingSize = true) {
1096	auto Res = std::make_unique(Token, AsmParser);	1096	auto Res = std::make_unique(Token, AsmParser);
1097	Res->Tok.Data = Str.data();	1097	Res->Tok.Data = Str.data();
1098	Res->Tok.Length = Str.size();	1098	Res->Tok.Length = Str.size();
1099	Res->StartLoc = Loc;	1099	Res->StartLoc = Loc;
1100	Res->EndLoc = Loc;	1100	Res->EndLoc = Loc;
1101	return Res;	1101	return Res;
1102	}	1102	}
1103		1103
1104	static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,	1104	static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,
1105	unsigned RegNo, SMLoc S,	1105	unsigned RegNo, SMLoc S,
1106	SMLoc E) {	1106	SMLoc E) {
1107	auto Op = std::make_unique(Register, AsmParser);	1107	auto Op = std::make_unique(Register, AsmParser);
1108	Op->Reg.RegNo = RegNo;	1108	Op->Reg.RegNo = RegNo;
1109	Op->Reg.Mods = Modifiers();	1109	Op->Reg.Mods = Modifiers();
1110	Op->StartLoc = S;	1110	Op->StartLoc = S;
1111	Op->EndLoc = E;	1111	Op->EndLoc = E;
1112	return Op;	1112	return Op;
1113	}	1113	}
1114		1114
1115	static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,	1115	static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,
1116	const class MCExpr *Expr, SMLoc S) {	1116	const class MCExpr *Expr, SMLoc S) {
1117	auto Op = std::make_unique(Expression, AsmParser);	1117	auto Op = std::make_unique(Expression, AsmParser);
1118	Op->Expr = Expr;	1118	Op->Expr = Expr;
1119	Op->StartLoc = S;	1119	Op->StartLoc = S;
1120	Op->EndLoc = S;	1120	Op->EndLoc = S;
1121	return Op;	1121	return Op;
1122	}	1122	}
1123	};	1123	};
1124		1124
1125	raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) {	1125	raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) {
1126	OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;	1126	OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;
1127	return OS;	1127	return OS;
1128	}	1128	}
1129		1129
1130	//===----------------------------------------------------------------------===//	1130	//===----------------------------------------------------------------------===//
1131	// AsmParser	1131	// AsmParser
1132	//===----------------------------------------------------------------------===//	1132	//===----------------------------------------------------------------------===//
1133		1133
1134	// Holds info related to the current kernel, e.g. count of SGPRs used.	1134	// Holds info related to the current kernel, e.g. count of SGPRs used.
1135	// Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next	1135	// Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next
1136	// .amdgpu_hsa_kernel or at EOF.	1136	// .amdgpu_hsa_kernel or at EOF.
1137	class KernelScopeInfo {	1137	class KernelScopeInfo {
1138	int SgprIndexUnusedMin = -1;	1138	int SgprIndexUnusedMin = -1;
1139	int VgprIndexUnusedMin = -1;	1139	int VgprIndexUnusedMin = -1;
1140	int AgprIndexUnusedMin = -1;	1140	int AgprIndexUnusedMin = -1;
1141	MCContext *Ctx = nullptr;	1141	MCContext *Ctx = nullptr;
1142	MCSubtargetInfo const *MSTI = nullptr;	1142	MCSubtargetInfo const *MSTI = nullptr;
1143		1143
1144	void usesSgprAt(int i) {	1144	void usesSgprAt(int i) {
1145	if (i >= SgprIndexUnusedMin) {	1145	if (i >= SgprIndexUnusedMin) {
1146	SgprIndexUnusedMin = ++i;	1146	SgprIndexUnusedMin = ++i;
1147	if (Ctx) {	1147	if (Ctx) {
1148	MCSymbol* const Sym =	1148	MCSymbol* const Sym =
1149	Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));	1149	Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));
1150	Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));	1150	Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));
1151	}	1151	}
1152	}	1152	}
1153	}	1153	}
1154		1154
1155	void usesVgprAt(int i) {	1155	void usesVgprAt(int i) {
1156	if (i >= VgprIndexUnusedMin) {	1156	if (i >= VgprIndexUnusedMin) {
1157	VgprIndexUnusedMin = ++i;	1157	VgprIndexUnusedMin = ++i;
1158	if (Ctx) {	1158	if (Ctx) {
1159	MCSymbol* const Sym =	1159	MCSymbol* const Sym =
1160	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	1160	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));
1161	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	1161	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,
1162	VgprIndexUnusedMin);	1162	VgprIndexUnusedMin);
1163	Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	1163	Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));
1164	}	1164	}
1165	}	1165	}
1166	}	1166	}
1167		1167
1168	void usesAgprAt(int i) {	1168	void usesAgprAt(int i) {
1169	// Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction	1169	// Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction
1170	if (!hasMAIInsts(*MSTI))	1170	if (!hasMAIInsts(*MSTI))
1171	return;	1171	return;
1172		1172
1173	if (i >= AgprIndexUnusedMin) {	1173	if (i >= AgprIndexUnusedMin) {
1174	AgprIndexUnusedMin = ++i;	1174	AgprIndexUnusedMin = ++i;
1175	if (Ctx) {	1175	if (Ctx) {
1176	MCSymbol* const Sym =	1176	MCSymbol* const Sym =
1177	Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count"));	1177	Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count"));
1178	Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx));	1178	Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx));
1179		1179
1180	// Also update vgpr_count (dependent on agpr_count for gfx908/gfx90a)	1180	// Also update vgpr_count (dependent on agpr_count for gfx908/gfx90a)
1181	MCSymbol* const vSym =	1181	MCSymbol* const vSym =
1182	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	1182	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));
1183	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	1183	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,
1184	VgprIndexUnusedMin);	1184	VgprIndexUnusedMin);
1185	vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	1185	vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));
1186	}	1186	}
1187	}	1187	}
1188	}	1188	}
1189		1189
1190	public:	1190	public:
1191	KernelScopeInfo() = default;	1191	KernelScopeInfo() = default;
1192		1192
1193	void initialize(MCContext &Context) {	1193	void initialize(MCContext &Context) {
1194	Ctx = &Context;	1194	Ctx = &Context;
1195	MSTI = Ctx->getSubtargetInfo();	1195	MSTI = Ctx->getSubtargetInfo();
1196		1196
1197	usesSgprAt(SgprIndexUnusedMin = -1);	1197	usesSgprAt(SgprIndexUnusedMin = -1);
1198	usesVgprAt(VgprIndexUnusedMin = -1);	1198	usesVgprAt(VgprIndexUnusedMin = -1);
1199	if (hasMAIInsts(*MSTI)) {	1199	if (hasMAIInsts(*MSTI)) {
1200	usesAgprAt(AgprIndexUnusedMin = -1);	1200	usesAgprAt(AgprIndexUnusedMin = -1);
1201	}	1201	}
1202	}	1202	}
1203		1203
1204	void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex,	1204	void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex,
1205	unsigned RegWidth) {	1205	unsigned RegWidth) {
1206	switch (RegKind) {	1206	switch (RegKind) {
1207	case IS_SGPR:	1207	case IS_SGPR:
1208	usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	1208	usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1209	break;	1209	break;
1210	case IS_AGPR:	1210	case IS_AGPR:
1211	usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	1211	usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1212	break;	1212	break;
1213	case IS_VGPR:	1213	case IS_VGPR:
1214	usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	1214	usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);
1215	break;	1215	break;
1216	default:	1216	default:
1217	break;	1217	break;
1218	}	1218	}
1219	}	1219	}
1220	};	1220	};
1221		1221
1222	class AMDGPUAsmParser : public MCTargetAsmParser {	1222	class AMDGPUAsmParser : public MCTargetAsmParser {
1223	MCAsmParser &Parser;	1223	MCAsmParser &Parser;
1224		1224
1225	unsigned ForcedEncodingSize = 0;	1225	unsigned ForcedEncodingSize = 0;
1226	bool ForcedDPP = false;	1226	bool ForcedDPP = false;
1227	bool ForcedSDWA = false;	1227	bool ForcedSDWA = false;
1228	KernelScopeInfo KernelScope;	1228	KernelScopeInfo KernelScope;
1229		1229
1230	/// @name Auto-generated Match Functions	1230	/// @name Auto-generated Match Functions
1231	/// {	1231	/// {
1232		1232
1233	#define GET_ASSEMBLER_HEADER	1233	#define GET_ASSEMBLER_HEADER
1234	#include "AMDGPUGenAsmMatcher.inc"	1234	#include "AMDGPUGenAsmMatcher.inc"
1235		1235
1236	/// }	1236	/// }
1237		1237
1238	private:	1238	private:
1239	bool ParseAsAbsoluteExpression(uint32_t &Ret);	1239	bool ParseAsAbsoluteExpression(uint32_t &Ret);
1240	bool OutOfRangeError(SMRange Range);	1240	bool OutOfRangeError(SMRange Range);
1241	/// Calculate VGPR/SGPR blocks required for given target, reserved	1241	/// Calculate VGPR/SGPR blocks required for given target, reserved
1242	/// registers, and user-specified NextFreeXGPR values.	1242	/// registers, and user-specified NextFreeXGPR values.
1243	///	1243	///
1244	/// \param Features [in] Target features, used for bug corrections.	1244	/// \param Features [in] Target features, used for bug corrections.
1245	/// \param VCCUsed [in] Whether VCC special SGPR is reserved.	1245	/// \param VCCUsed [in] Whether VCC special SGPR is reserved.
1246	/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.	1246	/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.
1247	/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.	1247	/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.
1248	/// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel	1248	/// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel
1249	/// descriptor field, if valid.	1249	/// descriptor field, if valid.
1250	/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.	1250	/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.
1251	/// \param VGPRRange [in] Token range, used for VGPR diagnostics.	1251	/// \param VGPRRange [in] Token range, used for VGPR diagnostics.
1252	/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.	1252	/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.
1253	/// \param SGPRRange [in] Token range, used for SGPR diagnostics.	1253	/// \param SGPRRange [in] Token range, used for SGPR diagnostics.
1254	/// \param VGPRBlocks [out] Result VGPR block count.	1254	/// \param VGPRBlocks [out] Result VGPR block count.
1255	/// \param SGPRBlocks [out] Result SGPR block count.	1255	/// \param SGPRBlocks [out] Result SGPR block count.
1256	bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,	1256	bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,
1257	bool FlatScrUsed, bool XNACKUsed,	1257	bool FlatScrUsed, bool XNACKUsed,
1258	std::optional EnableWavefrontSize32,	1258	std::optional EnableWavefrontSize32,
1259	unsigned NextFreeVGPR, SMRange VGPRRange,	1259	unsigned NextFreeVGPR, SMRange VGPRRange,
1260	unsigned NextFreeSGPR, SMRange SGPRRange,	1260	unsigned NextFreeSGPR, SMRange SGPRRange,
1261	unsigned &VGPRBlocks, unsigned &SGPRBlocks);	1261	unsigned &VGPRBlocks, unsigned &SGPRBlocks);
1262	bool ParseDirectiveAMDGCNTarget();	1262	bool ParseDirectiveAMDGCNTarget();
1263	bool ParseDirectiveAMDHSAKernel();	1263	bool ParseDirectiveAMDHSAKernel();
1264	bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);	1264	bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);
1265	bool ParseDirectiveHSACodeObjectVersion();	1265	bool ParseDirectiveHSACodeObjectVersion();
1266	bool ParseDirectiveHSACodeObjectISA();	1266	bool ParseDirectiveHSACodeObjectISA();
1267	bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);	1267	bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);
1268	bool ParseDirectiveAMDKernelCodeT();	1268	bool ParseDirectiveAMDKernelCodeT();
1269	// TODO: Possibly make subtargetHasRegister const.	1269	// TODO: Possibly make subtargetHasRegister const.
1270	bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);	1270	bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);
1271	bool ParseDirectiveAMDGPUHsaKernel();	1271	bool ParseDirectiveAMDGPUHsaKernel();
1272		1272
1273	bool ParseDirectiveISAVersion();	1273	bool ParseDirectiveISAVersion();
1274	bool ParseDirectiveHSAMetadata();	1274	bool ParseDirectiveHSAMetadata();
1275	bool ParseDirectivePALMetadataBegin();	1275	bool ParseDirectivePALMetadataBegin();
1276	bool ParseDirectivePALMetadata();	1276	bool ParseDirectivePALMetadata();
1277	bool ParseDirectiveAMDGPULDS();	1277	bool ParseDirectiveAMDGPULDS();
1278		1278
1279	/// Common code to parse out a block of text (typically YAML) between start and	1279	/// Common code to parse out a block of text (typically YAML) between start and
1280	/// end directives.	1280	/// end directives.
1281	bool ParseToEndDirective(const char *AssemblerDirectiveBegin,	1281	bool ParseToEndDirective(const char *AssemblerDirectiveBegin,
1282	const char *AssemblerDirectiveEnd,	1282	const char *AssemblerDirectiveEnd,
1283	std::string &CollectString);	1283	std::string &CollectString);
1284		1284
1285	bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,	1285	bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,
1286	RegisterKind RegKind, unsigned Reg1, SMLoc Loc);	1286	RegisterKind RegKind, unsigned Reg1, SMLoc Loc);
1287	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	1287	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1288	unsigned &RegNum, unsigned &RegWidth,	1288	unsigned &RegNum, unsigned &RegWidth,
1289	bool RestoreOnFailure = false);	1289	bool RestoreOnFailure = false);
1290	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	1290	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
1291	unsigned &RegNum, unsigned &RegWidth,	1291	unsigned &RegNum, unsigned &RegWidth,
1292	SmallVectorImpl &Tokens);	1292	SmallVectorImpl &Tokens);
1293	unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,	1293	unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,
1294	unsigned &RegWidth,	1294	unsigned &RegWidth,
1295	SmallVectorImpl &Tokens);	1295	SmallVectorImpl &Tokens);
1296	unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,	1296	unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,
1297	unsigned &RegWidth,	1297	unsigned &RegWidth,
1298	SmallVectorImpl &Tokens);	1298	SmallVectorImpl &Tokens);
1299	unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	1299	unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
1300	unsigned &RegWidth, SmallVectorImpl &Tokens);	1300	unsigned &RegWidth, SmallVectorImpl &Tokens);
1301	bool ParseRegRange(unsigned& Num, unsigned& Width);	1301	bool ParseRegRange(unsigned& Num, unsigned& Width);
1302	unsigned getRegularReg(RegisterKind RegKind,	1302	unsigned getRegularReg(RegisterKind RegKind,
1303	unsigned RegNum,	1303	unsigned RegNum,
1304	unsigned RegWidth,	1304	unsigned RegWidth,
1305	SMLoc Loc);	1305	SMLoc Loc);
1306		1306
1307	bool isRegister();	1307	bool isRegister();
1308	bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;	1308	bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;
1309	std::optional getGprCountSymbolName(RegisterKind RegKind);	1309	std::optional getGprCountSymbolName(RegisterKind RegKind);
1310	void initializeGprCountSymbol(RegisterKind RegKind);	1310	void initializeGprCountSymbol(RegisterKind RegKind);
1311	bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,	1311	bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,
1312	unsigned RegWidth);	1312	unsigned RegWidth);
1313	void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,	1313	void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
1314	bool IsAtomic);	1314	bool IsAtomic);
1315		1315
1316	public:	1316	public:
1317	enum AMDGPUMatchResultTy {	1317	enum AMDGPUMatchResultTy {
1318	Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY	1318	Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY
1319	};	1319	};
1320	enum OperandMode {	1320	enum OperandMode {
1321	OperandMode_Default,	1321	OperandMode_Default,
1322	OperandMode_NSA,	1322	OperandMode_NSA,
1323	};	1323	};
1324		1324
1325	using OptionalImmIndexMap = std::map;	1325	using OptionalImmIndexMap = std::map;
1326		1326
1327	AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,	1327	AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,
1328	const MCInstrInfo &MII,	1328	const MCInstrInfo &MII,
1329	const MCTargetOptions &Options)	1329	const MCTargetOptions &Options)
1330	: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {	1330	: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {
1331	MCAsmParserExtension::Initialize(Parser);	1331	MCAsmParserExtension::Initialize(Parser);
1332		1332
1333	if (getFeatureBits().none()) {	1333	if (getFeatureBits().none()) {
1334	// Set default features.	1334	// Set default features.
1335	copySTI().ToggleFeature("southern-islands");	1335	copySTI().ToggleFeature("southern-islands");
1336	}	1336	}
1337		1337
1338	setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));	1338	setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));
1339		1339
1340	{	1340	{
1341	// TODO: make those pre-defined variables read-only.	1341	// TODO: make those pre-defined variables read-only.
1342	// Currently there is none suitable machinery in the core llvm-mc for this.	1342	// Currently there is none suitable machinery in the core llvm-mc for this.
1343	// MCSymbol::isRedefinable is intended for another purpose, and	1343	// MCSymbol::isRedefinable is intended for another purpose, and
1344	// AsmParser::parseDirectiveSet() cannot be specialized for specific target.	1344	// AsmParser::parseDirectiveSet() cannot be specialized for specific target.
1345	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	1345	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
1346	MCContext &Ctx = getContext();	1346	MCContext &Ctx = getContext();
1347	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	1347	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {
1348	MCSymbol *Sym =	1348	MCSymbol *Sym =
1349	Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));	1349	Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));
1350	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	1350	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
1351	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));	1351	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));
1352	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	1352	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
1353	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));	1353	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));
1354	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	1354	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
1355	} else {	1355	} else {
1356	MCSymbol *Sym =	1356	MCSymbol *Sym =
1357	Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));	1357	Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));
1358	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	1358	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));
1359	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));	1359	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));
1360	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	1360	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));
1361	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));	1361	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));
1362	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	1362	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));
1363	}	1363	}
1364	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	1364	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {
1365	initializeGprCountSymbol(IS_VGPR);	1365	initializeGprCountSymbol(IS_VGPR);
1366	initializeGprCountSymbol(IS_SGPR);	1366	initializeGprCountSymbol(IS_SGPR);
1367	} else	1367	} else
1368	KernelScope.initialize(getContext());	1368	KernelScope.initialize(getContext());
1369	}	1369	}
1370	}	1370	}
1371		1371
1372	bool hasMIMG_R128() const {	1372	bool hasMIMG_R128() const {
1373	return AMDGPU::hasMIMG_R128(getSTI());	1373	return AMDGPU::hasMIMG_R128(getSTI());
1374	}	1374	}
1375		1375
1376	bool hasPackedD16() const {	1376	bool hasPackedD16() const {
1377	return AMDGPU::hasPackedD16(getSTI());	1377	return AMDGPU::hasPackedD16(getSTI());
1378	}	1378	}
1379		1379
1380	bool hasA16() const { return AMDGPU::hasA16(getSTI()); }	1380	bool hasA16() const { return AMDGPU::hasA16(getSTI()); }
1381		1381
1382	bool hasG16() const { return AMDGPU::hasG16(getSTI()); }	1382	bool hasG16() const { return AMDGPU::hasG16(getSTI()); }
1383		1383
1384	bool isSI() const {	1384	bool isSI() const {
1385	return AMDGPU::isSI(getSTI());	1385	return AMDGPU::isSI(getSTI());
1386	}	1386	}
1387		1387
1388	bool isCI() const {	1388	bool isCI() const {
1389	return AMDGPU::isCI(getSTI());	1389	return AMDGPU::isCI(getSTI());
1390	}	1390	}
1391		1391
1392	bool isVI() const {	1392	bool isVI() const {
1393	return AMDGPU::isVI(getSTI());	1393	return AMDGPU::isVI(getSTI());
1394	}	1394	}
1395		1395
1396	bool isGFX9() const {	1396	bool isGFX9() const {
1397	return AMDGPU::isGFX9(getSTI());	1397	return AMDGPU::isGFX9(getSTI());
1398	}	1398	}
1399		1399
1400	// TODO: isGFX90A is also true for GFX940. We need to clean it.	1400	// TODO: isGFX90A is also true for GFX940. We need to clean it.
1401	bool isGFX90A() const {	1401	bool isGFX90A() const {
1402	return AMDGPU::isGFX90A(getSTI());	1402	return AMDGPU::isGFX90A(getSTI());
1403	}	1403	}
1404		1404
1405	bool isGFX940() const {	1405	bool isGFX940() const {
1406	return AMDGPU::isGFX940(getSTI());	1406	return AMDGPU::isGFX940(getSTI());
1407	}	1407	}
1408		1408
1409	bool isGFX9Plus() const {	1409	bool isGFX9Plus() const {
1410	return AMDGPU::isGFX9Plus(getSTI());	1410	return AMDGPU::isGFX9Plus(getSTI());
1411	}	1411	}
1412		1412
1413	bool isGFX10() const {	1413	bool isGFX10() const {
1414	return AMDGPU::isGFX10(getSTI());	1414	return AMDGPU::isGFX10(getSTI());
1415	}	1415	}
1416		1416
1417	bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); }	1417	bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); }
1418		1418
1419	bool isGFX11() const {	1419	bool isGFX11() const {
1420	return AMDGPU::isGFX11(getSTI());	1420	return AMDGPU::isGFX11(getSTI());
1421	}	1421	}
1422		1422
1423	bool isGFX11Plus() const {	1423	bool isGFX11Plus() const {
1424	return AMDGPU::isGFX11Plus(getSTI());	1424	return AMDGPU::isGFX11Plus(getSTI());
1425	}	1425	}
1426		1426
1427	bool isGFX10_AEncoding() const { return AMDGPU::isGFX10_AEncoding(getSTI()); }	1427	bool isGFX10_AEncoding() const { return AMDGPU::isGFX10_AEncoding(getSTI()); }
1428		1428
1429	bool isGFX10_BEncoding() const {	1429	bool isGFX10_BEncoding() const {
1430	return AMDGPU::isGFX10_BEncoding(getSTI());	1430	return AMDGPU::isGFX10_BEncoding(getSTI());
1431	}	1431	}
1432		1432
1433	bool hasInv2PiInlineImm() const {	1433	bool hasInv2PiInlineImm() const {
1434	return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];	1434	return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];
1435	}	1435	}
1436		1436
1437	bool hasFlatOffsets() const {	1437	bool hasFlatOffsets() const {
1438	return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];	1438	return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];
1439	}	1439	}
1440		1440
1441	bool hasArchitectedFlatScratch() const {	1441	bool hasArchitectedFlatScratch() const {
1442	return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];	1442	return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];
1443	}	1443	}
1444		1444
1445	bool hasSGPR102_SGPR103() const {	1445	bool hasSGPR102_SGPR103() const {
1446	return !isVI() && !isGFX9();	1446	return !isVI() && !isGFX9();
1447	}	1447	}
1448		1448
1449	bool hasSGPR104_SGPR105() const { return isGFX10Plus(); }	1449	bool hasSGPR104_SGPR105() const { return isGFX10Plus(); }
1450		1450
1451	bool hasIntClamp() const {	1451	bool hasIntClamp() const {
1452	return getFeatureBits()[AMDGPU::FeatureIntClamp];	1452	return getFeatureBits()[AMDGPU::FeatureIntClamp];
1453	}	1453	}
1454		1454
1455	bool hasPartialNSAEncoding() const {	1455	bool hasPartialNSAEncoding() const {
1456	return getFeatureBits()[AMDGPU::FeaturePartialNSAEncoding];	1456	return getFeatureBits()[AMDGPU::FeaturePartialNSAEncoding];
1457	}	1457	}
1458		1458
1459	unsigned getNSAMaxSize() const {	1459	unsigned getNSAMaxSize() const {
1460	return AMDGPU::getNSAMaxSize(getSTI());	1460	return AMDGPU::getNSAMaxSize(getSTI());
1461	}	1461	}
1462		1462
1463	AMDGPUTargetStreamer &getTargetStreamer() {	1463	AMDGPUTargetStreamer &getTargetStreamer() {
1464	MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();	1464	MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
1465	return static_cast(TS);	1465	return static_cast(TS);
1466	}	1466	}
1467		1467
1468	const MCRegisterInfo *getMRI() const {	1468	const MCRegisterInfo *getMRI() const {
1469	// We need this const_cast because for some reason getContext() is not const	1469	// We need this const_cast because for some reason getContext() is not const
1470	// in MCAsmParser.	1470	// in MCAsmParser.
1471	return const_cast(this)->getContext().getRegisterInfo();	1471	return const_cast(this)->getContext().getRegisterInfo();
1472	}	1472	}
1473		1473
1474	const MCInstrInfo *getMII() const {	1474	const MCInstrInfo *getMII() const {
1475	return &MII;	1475	return &MII;
1476	}	1476	}
1477		1477
1478	const FeatureBitset &getFeatureBits() const {	1478	const FeatureBitset &getFeatureBits() const {
1479	return getSTI().getFeatureBits();	1479	return getSTI().getFeatureBits();
1480	}	1480	}
1481		1481
1482	void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }	1482	void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }
1483	void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }	1483	void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }
1484	void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }	1484	void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }
1485		1485
1486	unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }	1486	unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }
1487	bool isForcedVOP3() const { return ForcedEncodingSize == 64; }	1487	bool isForcedVOP3() const { return ForcedEncodingSize == 64; }
1488	bool isForcedDPP() const { return ForcedDPP; }	1488	bool isForcedDPP() const { return ForcedDPP; }
1489	bool isForcedSDWA() const { return ForcedSDWA; }	1489	bool isForcedSDWA() const { return ForcedSDWA; }
1490	ArrayRef getMatchedVariants() const;	1490	ArrayRef getMatchedVariants() const;
1491	StringRef getMatchedVariantName() const;	1491	StringRef getMatchedVariantName() const;
1492		1492
1493	std::unique_ptr parseRegister(bool RestoreOnFailure = false);	1493	std::unique_ptr parseRegister(bool RestoreOnFailure = false);
1494	bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,	1494	bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,
1495	bool RestoreOnFailure);	1495	bool RestoreOnFailure);
1496	bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	1496	bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1497	SMLoc &EndLoc) override;	1497	SMLoc &EndLoc) override;
1498	OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	1498	OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
1499	SMLoc &EndLoc) override;	1499	SMLoc &EndLoc) override;
1500	unsigned checkTargetMatchPredicate(MCInst &Inst) override;	1500	unsigned checkTargetMatchPredicate(MCInst &Inst) override;
1501	unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,	1501	unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
1502	unsigned Kind) override;	1502	unsigned Kind) override;
1503	bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	1503	bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1504	OperandVector &Operands, MCStreamer &Out,	1504	OperandVector &Operands, MCStreamer &Out,
1505	uint64_t &ErrorInfo,	1505	uint64_t &ErrorInfo,
1506	bool MatchingInlineAsm) override;	1506	bool MatchingInlineAsm) override;
1507	bool ParseDirective(AsmToken DirectiveID) override;	1507	bool ParseDirective(AsmToken DirectiveID) override;
1508	ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,	1508	ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,
1509	OperandMode Mode = OperandMode_Default);	1509	OperandMode Mode = OperandMode_Default);
1510	StringRef parseMnemonicSuffix(StringRef Name);	1510	StringRef parseMnemonicSuffix(StringRef Name);
1511	bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,	1511	bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1512	SMLoc NameLoc, OperandVector &Operands) override;	1512	SMLoc NameLoc, OperandVector &Operands) override;
1513	//bool ProcessInstruction(MCInst &Inst);	1513	//bool ProcessInstruction(MCInst &Inst);
1514		1514
1515	ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);	1515	ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);
1516		1516
1517	ParseStatus parseIntWithPrefix(const char *Prefix, int64_t &Int);	1517	ParseStatus parseIntWithPrefix(const char *Prefix, int64_t &Int);
1518		1518
1519	ParseStatus	1519	ParseStatus
1520	parseIntWithPrefix(const char *Prefix, OperandVector &Operands,	1520	parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
1521	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	1521	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
1522	std::function ConvertResult = nullptr);	1522	std::function ConvertResult = nullptr);
1523		1523
1524	ParseStatus parseOperandArrayWithPrefix(	1524	ParseStatus parseOperandArrayWithPrefix(
1525	const char *Prefix, OperandVector &Operands,	1525	const char *Prefix, OperandVector &Operands,
1526	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	1526	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
1527	bool (*ConvertResult)(int64_t &) = nullptr);	1527	bool (*ConvertResult)(int64_t &) = nullptr);
1528		1528
1529	ParseStatus	1529	ParseStatus
1530	parseNamedBit(StringRef Name, OperandVector &Operands,	1530	parseNamedBit(StringRef Name, OperandVector &Operands,
1531	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);	1531	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
1532	unsigned getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const;	1532	unsigned getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const;
1533	ParseStatus parseCPol(OperandVector &Operands);	1533	ParseStatus parseCPol(OperandVector &Operands);
1534	ParseStatus parseStringWithPrefix(StringRef Prefix, StringRef &Value,	1534	ParseStatus parseStringWithPrefix(StringRef Prefix, StringRef &Value,
1535	SMLoc &StringLoc);	1535	SMLoc &StringLoc);
1536		1536
1537	bool isModifier();	1537	bool isModifier();
1538	bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	1538	bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;
1539	bool isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	1539	bool isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;
1540	bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	1540	bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;
1541	bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;	1541	bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;
1542	bool parseSP3NegModifier();	1542	bool parseSP3NegModifier();
1543	ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);	1543	ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);
1544	ParseStatus parseReg(OperandVector &Operands);	1544	ParseStatus parseReg(OperandVector &Operands);
1545	ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);	1545	ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);
1546	ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,	1546	ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,
1547	bool AllowImm = true);	1547	bool AllowImm = true);
1548	ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,	1548	ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,
1549	bool AllowImm = true);	1549	bool AllowImm = true);
1550	ParseStatus parseRegWithFPInputMods(OperandVector &Operands);	1550	ParseStatus parseRegWithFPInputMods(OperandVector &Operands);
1551	ParseStatus parseRegWithIntInputMods(OperandVector &Operands);	1551	ParseStatus parseRegWithIntInputMods(OperandVector &Operands);
1552	ParseStatus parseVReg32OrOff(OperandVector &Operands);	1552	ParseStatus parseVReg32OrOff(OperandVector &Operands);
1553	ParseStatus parseDfmtNfmt(int64_t &Format);	1553	ParseStatus parseDfmtNfmt(int64_t &Format);
1554	ParseStatus parseUfmt(int64_t &Format);	1554	ParseStatus parseUfmt(int64_t &Format);
1555	ParseStatus parseSymbolicSplitFormat(StringRef FormatStr, SMLoc Loc,	1555	ParseStatus parseSymbolicSplitFormat(StringRef FormatStr, SMLoc Loc,
1556	int64_t &Format);	1556	int64_t &Format);
1557	ParseStatus parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc,	1557	ParseStatus parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc,
1558	int64_t &Format);	1558	int64_t &Format);
1559	ParseStatus parseFORMAT(OperandVector &Operands);	1559	ParseStatus parseFORMAT(OperandVector &Operands);
1560	ParseStatus parseSymbolicOrNumericFormat(int64_t &Format);	1560	ParseStatus parseSymbolicOrNumericFormat(int64_t &Format);
1561	ParseStatus parseNumericFormat(int64_t &Format);	1561	ParseStatus parseNumericFormat(int64_t &Format);
1562	ParseStatus parseFlatOffset(OperandVector &Operands);	1562	ParseStatus parseFlatOffset(OperandVector &Operands);
1563	ParseStatus parseR128A16(OperandVector &Operands);	1563	ParseStatus parseR128A16(OperandVector &Operands);
1564	ParseStatus parseBLGP(OperandVector &Operands);	1564	ParseStatus parseBLGP(OperandVector &Operands);
1565	bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);	1565	bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);
1566	bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);	1566	bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);
1567		1567
1568	void cvtExp(MCInst &Inst, const OperandVector &Operands);	1568	void cvtExp(MCInst &Inst, const OperandVector &Operands);
1569		1569
1570	bool parseCnt(int64_t &IntVal);	1570	bool parseCnt(int64_t &IntVal);
1571	ParseStatus parseSWaitCnt(OperandVector &Operands);	1571	ParseStatus parseSWaitCnt(OperandVector &Operands);
1572		1572
1573	bool parseDepCtr(int64_t &IntVal, unsigned &Mask);	1573	bool parseDepCtr(int64_t &IntVal, unsigned &Mask);
1574	void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);	1574	void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);
1575	ParseStatus parseDepCtr(OperandVector &Operands);	1575	ParseStatus parseDepCtr(OperandVector &Operands);
1576		1576
1577	bool parseDelay(int64_t &Delay);	1577	bool parseDelay(int64_t &Delay);
1578	ParseStatus parseSDelayALU(OperandVector &Operands);	1578	ParseStatus parseSDelayALU(OperandVector &Operands);
1579		1579
1580	ParseStatus parseHwreg(OperandVector &Operands);	1580	ParseStatus parseHwreg(OperandVector &Operands);
1581		1581
1582	private:	1582	private:
1583	struct OperandInfoTy {	1583	struct OperandInfoTy {
1584	SMLoc Loc;	1584	SMLoc Loc;
1585	int64_t Id;	1585	int64_t Id;
1586	bool IsSymbolic = false;	1586	bool IsSymbolic = false;
1587	bool IsDefined = false;	1587	bool IsDefined = false;
1588		1588
1589	OperandInfoTy(int64_t Id_) : Id(Id_) {}	1589	OperandInfoTy(int64_t Id_) : Id(Id_) {}
1590	};	1590	};
1591		1591
1592	bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);	1592	bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);
1593	bool validateSendMsg(const OperandInfoTy &Msg,	1593	bool validateSendMsg(const OperandInfoTy &Msg,
1594	const OperandInfoTy &Op,	1594	const OperandInfoTy &Op,
1595	const OperandInfoTy &Stream);	1595	const OperandInfoTy &Stream);
1596		1596
1597	bool parseHwregBody(OperandInfoTy &HwReg,	1597	bool parseHwregBody(OperandInfoTy &HwReg,
1598	OperandInfoTy &Offset,	1598	OperandInfoTy &Offset,
1599	OperandInfoTy &Width);	1599	OperandInfoTy &Width);
1600	bool validateHwreg(const OperandInfoTy &HwReg,	1600	bool validateHwreg(const OperandInfoTy &HwReg,
1601	const OperandInfoTy &Offset,	1601	const OperandInfoTy &Offset,
1602	const OperandInfoTy &Width);	1602	const OperandInfoTy &Width);
1603		1603
1604	SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;	1604	SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;
1605	SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;	1605	SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;
1606	SMLoc getBLGPLoc(const OperandVector &Operands) const;	1606	SMLoc getBLGPLoc(const OperandVector &Operands) const;
1607		1607
1608	SMLoc getOperandLoc(std::function Test,	1608	SMLoc getOperandLoc(std::function Test,
1609	const OperandVector &Operands) const;	1609	const OperandVector &Operands) const;
1610	SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;	1610	SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;
1611	SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;	1611	SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;
1612	SMLoc getLitLoc(const OperandVector &Operands,	1612	SMLoc getLitLoc(const OperandVector &Operands,
1613	bool SearchMandatoryLiterals = false) const;	1613	bool SearchMandatoryLiterals = false) const;
1614	SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;	1614	SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;
1615	SMLoc getConstLoc(const OperandVector &Operands) const;	1615	SMLoc getConstLoc(const OperandVector &Operands) const;
1616	SMLoc getInstLoc(const OperandVector &Operands) const;	1616	SMLoc getInstLoc(const OperandVector &Operands) const;
1617		1617
1618	bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);	1618	bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);
1619	bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);	1619	bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);
1620	bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);	1620	bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);
1621	bool validateSOPLiteral(const MCInst &Inst) const;	1621	bool validateSOPLiteral(const MCInst &Inst) const;
1622	bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);	1622	bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);
1623	bool validateVOPDRegBankConstraints(const MCInst &Inst,	1623	bool validateVOPDRegBankConstraints(const MCInst &Inst,
1624	const OperandVector &Operands);	1624	const OperandVector &Operands);
1625	bool validateIntClampSupported(const MCInst &Inst);	1625	bool validateIntClampSupported(const MCInst &Inst);
1626	bool validateMIMGAtomicDMask(const MCInst &Inst);	1626	bool validateMIMGAtomicDMask(const MCInst &Inst);
1627	bool validateMIMGGatherDMask(const MCInst &Inst);	1627	bool validateMIMGGatherDMask(const MCInst &Inst);
1628	bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);	1628	bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);
1629	bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);	1629	bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);
1630	bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);	1630	bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);
1631	bool validateMIMGD16(const MCInst &Inst);	1631	bool validateMIMGD16(const MCInst &Inst);
1632	bool validateMIMGMSAA(const MCInst &Inst);	1632	bool validateMIMGMSAA(const MCInst &Inst);
1633	bool validateOpSel(const MCInst &Inst);	1633	bool validateOpSel(const MCInst &Inst);
1634	bool validateDPP(const MCInst &Inst, const OperandVector &Operands);	1634	bool validateDPP(const MCInst &Inst, const OperandVector &Operands);
1635	bool validateVccOperand(unsigned Reg) const;	1635	bool validateVccOperand(unsigned Reg) const;
1636	bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);	1636	bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);
1637	bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);	1637	bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);
1638	bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);	1638	bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);
1639	bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);	1639	bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);
1640	bool validateAGPRLdSt(const MCInst &Inst) const;	1640	bool validateAGPRLdSt(const MCInst &Inst) const;
1641	bool validateVGPRAlign(const MCInst &Inst) const;	1641	bool validateVGPRAlign(const MCInst &Inst) const;
1642	bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);	1642	bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);
1643	bool validateGWS(const MCInst &Inst, const OperandVector &Operands);	1643	bool validateGWS(const MCInst &Inst, const OperandVector &Operands);
1644	bool validateDivScale(const MCInst &Inst);	1644	bool validateDivScale(const MCInst &Inst);
1645	bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);	1645	bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);
1646	bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,	1646	bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,
1647	const SMLoc &IDLoc);	1647	const SMLoc &IDLoc);
1648	bool validateExeczVcczOperands(const OperandVector &Operands);	1648	bool validateExeczVcczOperands(const OperandVector &Operands);
1649	bool validateTFE(const MCInst &Inst, const OperandVector &Operands);	1649	bool validateTFE(const MCInst &Inst, const OperandVector &Operands);
1650	std::optional validateLdsDirect(const MCInst &Inst);	1650	std::optional validateLdsDirect(const MCInst &Inst);
1651	unsigned getConstantBusLimit(unsigned Opcode) const;	1651	unsigned getConstantBusLimit(unsigned Opcode) const;
1652	bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);	1652	bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);
1653	bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;	1653	bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;
1654	unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;	1654	unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;
1655		1655
1656	bool isSupportedMnemo(StringRef Mnemo,	1656	bool isSupportedMnemo(StringRef Mnemo,
1657	const FeatureBitset &FBS);	1657	const FeatureBitset &FBS);
1658	bool isSupportedMnemo(StringRef Mnemo,	1658	bool isSupportedMnemo(StringRef Mnemo,
1659	const FeatureBitset &FBS,	1659	const FeatureBitset &FBS,
1660	ArrayRef Variants);	1660	ArrayRef Variants);
1661	bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);	1661	bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);
1662		1662
1663	bool isId(const StringRef Id) const;	1663	bool isId(const StringRef Id) const;
1664	bool isId(const AsmToken &Token, const StringRef Id) const;	1664	bool isId(const AsmToken &Token, const StringRef Id) const;
1665	bool isToken(const AsmToken::TokenKind Kind) const;	1665	bool isToken(const AsmToken::TokenKind Kind) const;
1666	StringRef getId() const;	1666	StringRef getId() const;
1667	bool trySkipId(const StringRef Id);	1667	bool trySkipId(const StringRef Id);
1668	bool trySkipId(const StringRef Pref, const StringRef Id);	1668	bool trySkipId(const StringRef Pref, const StringRef Id);
1669	bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind);	1669	bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind);
1670	bool trySkipToken(const AsmToken::TokenKind Kind);	1670	bool trySkipToken(const AsmToken::TokenKind Kind);
1671	bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);	1671	bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);
1672	bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");	1672	bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");
1673	bool parseId(StringRef &Val, const StringRef ErrMsg = "");	1673	bool parseId(StringRef &Val, const StringRef ErrMsg = "");
1674		1674
1675	void peekTokens(MutableArrayRef Tokens);	1675	void peekTokens(MutableArrayRef Tokens);
1676	AsmToken::TokenKind getTokenKind() const;	1676	AsmToken::TokenKind getTokenKind() const;
1677	bool parseExpr(int64_t &Imm, StringRef Expected = "");	1677	bool parseExpr(int64_t &Imm, StringRef Expected = "");
1678	bool parseExpr(OperandVector &Operands);	1678	bool parseExpr(OperandVector &Operands);
1679	StringRef getTokenStr() const;	1679	StringRef getTokenStr() const;
1680	AsmToken peekToken(bool ShouldSkipSpace = true);	1680	AsmToken peekToken(bool ShouldSkipSpace = true);
1681	AsmToken getToken() const;	1681	AsmToken getToken() const;
1682	SMLoc getLoc() const;	1682	SMLoc getLoc() const;
1683	void lex();	1683	void lex();
1684		1684
1685	public:	1685	public:
1686	void onBeginOfFile() override;	1686	void onBeginOfFile() override;
1687		1687
1688	ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);	1688	ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);
1689		1689
1690	ParseStatus parseExpTgt(OperandVector &Operands);	1690	ParseStatus parseExpTgt(OperandVector &Operands);
1691	ParseStatus parseSendMsg(OperandVector &Operands);	1691	ParseStatus parseSendMsg(OperandVector &Operands);
1692	ParseStatus parseInterpSlot(OperandVector &Operands);	1692	ParseStatus parseInterpSlot(OperandVector &Operands);
1693	ParseStatus parseInterpAttr(OperandVector &Operands);	1693	ParseStatus parseInterpAttr(OperandVector &Operands);
1694	ParseStatus parseSOPPBrTarget(OperandVector &Operands);	1694	ParseStatus parseSOPPBrTarget(OperandVector &Operands);
1695	ParseStatus parseBoolReg(OperandVector &Operands);	1695	ParseStatus parseBoolReg(OperandVector &Operands);
1696		1696
1697	bool parseSwizzleOperand(int64_t &Op,	1697	bool parseSwizzleOperand(int64_t &Op,
1698	const unsigned MinVal,	1698	const unsigned MinVal,
1699	const unsigned MaxVal,	1699	const unsigned MaxVal,
1700	const StringRef ErrMsg,	1700	const StringRef ErrMsg,
1701	SMLoc &Loc);	1701	SMLoc &Loc);
1702	bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	1702	bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
1703	const unsigned MinVal,	1703	const unsigned MinVal,
1704	const unsigned MaxVal,	1704	const unsigned MaxVal,
1705	const StringRef ErrMsg);	1705	const StringRef ErrMsg);
1706	ParseStatus parseSwizzle(OperandVector &Operands);	1706	ParseStatus parseSwizzle(OperandVector &Operands);
1707	bool parseSwizzleOffset(int64_t &Imm);	1707	bool parseSwizzleOffset(int64_t &Imm);
1708	bool parseSwizzleMacro(int64_t &Imm);	1708	bool parseSwizzleMacro(int64_t &Imm);
1709	bool parseSwizzleQuadPerm(int64_t &Imm);	1709	bool parseSwizzleQuadPerm(int64_t &Imm);
1710	bool parseSwizzleBitmaskPerm(int64_t &Imm);	1710	bool parseSwizzleBitmaskPerm(int64_t &Imm);
1711	bool parseSwizzleBroadcast(int64_t &Imm);	1711	bool parseSwizzleBroadcast(int64_t &Imm);
1712	bool parseSwizzleSwap(int64_t &Imm);	1712	bool parseSwizzleSwap(int64_t &Imm);
1713	bool parseSwizzleReverse(int64_t &Imm);	1713	bool parseSwizzleReverse(int64_t &Imm);
1714		1714
1715	ParseStatus parseGPRIdxMode(OperandVector &Operands);	1715	ParseStatus parseGPRIdxMode(OperandVector &Operands);
1716	int64_t parseGPRIdxMacro();	1716	int64_t parseGPRIdxMacro();
1717		1717
1718	void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }	1718	void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }
1719	void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }	1719	void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }
1720		1720
1721	ParseStatus parseOModSI(OperandVector &Operands);	1721	ParseStatus parseOModSI(OperandVector &Operands);
1722		1722
1723	void cvtVOP3(MCInst &Inst, const OperandVector &Operands,	1723	void cvtVOP3(MCInst &Inst, const OperandVector &Operands,
1724	OptionalImmIndexMap &OptionalIdx);	1724	OptionalImmIndexMap &OptionalIdx);
1725	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);	1725	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);
1726	void cvtVOP3(MCInst &Inst, const OperandVector &Operands);	1726	void cvtVOP3(MCInst &Inst, const OperandVector &Operands);
1727	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);	1727	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);
1728	void cvtVOPD(MCInst &Inst, const OperandVector &Operands);	1728	void cvtVOPD(MCInst &Inst, const OperandVector &Operands);
1729	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	1729	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
1730	OptionalImmIndexMap &OptionalIdx);	1730	OptionalImmIndexMap &OptionalIdx);
1731	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	1731	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
1732	OptionalImmIndexMap &OptionalIdx);	1732	OptionalImmIndexMap &OptionalIdx);
1733		1733
1734	void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);	1734	void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
1735	void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);	1735	void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
1736	void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);	1736	void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);
1737		1737
1738	bool parseDimId(unsigned &Encoding);	1738	bool parseDimId(unsigned &Encoding);
1739	ParseStatus parseDim(OperandVector &Operands);	1739	ParseStatus parseDim(OperandVector &Operands);
1740	bool convertDppBoundCtrl(int64_t &BoundCtrl);	1740	bool convertDppBoundCtrl(int64_t &BoundCtrl);
1741	ParseStatus parseDPP8(OperandVector &Operands);	1741	ParseStatus parseDPP8(OperandVector &Operands);
1742	ParseStatus parseDPPCtrl(OperandVector &Operands);	1742	ParseStatus parseDPPCtrl(OperandVector &Operands);
1743	bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);	1743	bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);
1744	int64_t parseDPPCtrlSel(StringRef Ctrl);	1744	int64_t parseDPPCtrlSel(StringRef Ctrl);
1745	int64_t parseDPPCtrlPerm();	1745	int64_t parseDPPCtrlPerm();
1746	void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);	1746	void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);
1747	void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {	1747	void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {
1748	cvtDPP(Inst, Operands, true);	1748	cvtDPP(Inst, Operands, true);
1749	}	1749	}
1750	void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	1750	void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
1751	bool IsDPP8 = false);	1751	bool IsDPP8 = false);
1752	void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {	1752	void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {
1753	cvtVOP3DPP(Inst, Operands, true);	1753	cvtVOP3DPP(Inst, Operands, true);
1754	}	1754	}
1755		1755
1756	ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,	1756	ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,
1757	AMDGPUOperand::ImmTy Type);	1757	AMDGPUOperand::ImmTy Type);
1758	ParseStatus parseSDWADstUnused(OperandVector &Operands);	1758	ParseStatus parseSDWADstUnused(OperandVector &Operands);
1759	void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);	1759	void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);
1760	void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);	1760	void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);
1761	void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);	1761	void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);
1762	void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);	1762	void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);
1763	void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);	1763	void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);
1764	void cvtSDWA(MCInst &Inst, const OperandVector &Operands,	1764	void cvtSDWA(MCInst &Inst, const OperandVector &Operands,
1765	uint64_t BasicInstType,	1765	uint64_t BasicInstType,
1766	bool SkipDstVcc = false,	1766	bool SkipDstVcc = false,
1767	bool SkipSrcVcc = false);	1767	bool SkipSrcVcc = false);
1768		1768
1769	ParseStatus parseEndpgm(OperandVector &Operands);	1769	ParseStatus parseEndpgm(OperandVector &Operands);
1770		1770
1771	ParseStatus parseVOPD(OperandVector &Operands);	1771	ParseStatus parseVOPD(OperandVector &Operands);
1772	};	1772	};
1773		1773
1774	} // end anonymous namespace	1774	} // end anonymous namespace
1775		1775
1776	// May be called with integer type with equivalent bitwidth.	1776	// May be called with integer type with equivalent bitwidth.
1777	static const fltSemantics *getFltSemantics(unsigned Size) {	1777	static const fltSemantics *getFltSemantics(unsigned Size) {
1778	switch (Size) {	1778	switch (Size) {
1779	case 4:	1779	case 4:
1780	return &APFloat::IEEEsingle();	1780	return &APFloat::IEEEsingle();
1781	case 8:	1781	case 8:
1782	return &APFloat::IEEEdouble();	1782	return &APFloat::IEEEdouble();
1783	case 2:	1783	case 2:
1784	return &APFloat::IEEEhalf();	1784	return &APFloat::IEEEhalf();
1785	default:	1785	default:
1786	llvm_unreachable("unsupported fp type");	1786	llvm_unreachable("unsupported fp type");
1787	}	1787	}
1788	}	1788	}
1789		1789
1790	static const fltSemantics *getFltSemantics(MVT VT) {	1790	static const fltSemantics *getFltSemantics(MVT VT) {
1791	return getFltSemantics(VT.getSizeInBits() / 8);	1791	return getFltSemantics(VT.getSizeInBits() / 8);
1792	}	1792	}
1793		1793
1794	static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {	1794	static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {
1795	switch (OperandType) {	1795	switch (OperandType) {
1796	case AMDGPU::OPERAND_REG_IMM_INT32:	1796	case AMDGPU::OPERAND_REG_IMM_INT32:
1797	case AMDGPU::OPERAND_REG_IMM_FP32:	1797	case AMDGPU::OPERAND_REG_IMM_FP32:
1798	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	1798	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
1799	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	1799	case AMDGPU::OPERAND_REG_INLINE_C_INT32:
1800	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	1800	case AMDGPU::OPERAND_REG_INLINE_C_FP32:
1801	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	1801	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
1802	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	1802	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
1803	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	1803	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
1804	case AMDGPU::OPERAND_REG_IMM_V2FP32:	1804	case AMDGPU::OPERAND_REG_IMM_V2FP32:
1805	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	1805	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
1806	case AMDGPU::OPERAND_REG_IMM_V2INT32:	1806	case AMDGPU::OPERAND_REG_IMM_V2INT32:
1807	case AMDGPU::OPERAND_KIMM32:	1807	case AMDGPU::OPERAND_KIMM32:
1808	return &APFloat::IEEEsingle();	1808	return &APFloat::IEEEsingle();
1809	case AMDGPU::OPERAND_REG_IMM_INT64:	1809	case AMDGPU::OPERAND_REG_IMM_INT64:
1810	case AMDGPU::OPERAND_REG_IMM_FP64:	1810	case AMDGPU::OPERAND_REG_IMM_FP64:
1811	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	1811	case AMDGPU::OPERAND_REG_INLINE_C_INT64:
1812	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	1812	case AMDGPU::OPERAND_REG_INLINE_C_FP64:
1813	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	1813	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
1814	return &APFloat::IEEEdouble();	1814	return &APFloat::IEEEdouble();
1815	case AMDGPU::OPERAND_REG_IMM_INT16:	1815	case AMDGPU::OPERAND_REG_IMM_INT16:
1816	case AMDGPU::OPERAND_REG_IMM_FP16:	1816	case AMDGPU::OPERAND_REG_IMM_FP16:
1817	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	1817	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
1818	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	1818	case AMDGPU::OPERAND_REG_INLINE_C_INT16:
1819	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	1819	case AMDGPU::OPERAND_REG_INLINE_C_FP16:
1820	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	1820	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
1821	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	1821	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
1822	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	1822	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
1823	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	1823	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
1824	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	1824	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
1825	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	1825	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
1826	case AMDGPU::OPERAND_REG_IMM_V2INT16:	1826	case AMDGPU::OPERAND_REG_IMM_V2INT16:
1827	case AMDGPU::OPERAND_REG_IMM_V2FP16:	1827	case AMDGPU::OPERAND_REG_IMM_V2FP16:
1828	case AMDGPU::OPERAND_KIMM16:	1828	case AMDGPU::OPERAND_KIMM16:
1829	return &APFloat::IEEEhalf();	1829	return &APFloat::IEEEhalf();
1830	default:	1830	default:
1831	llvm_unreachable("unsupported fp type");	1831	llvm_unreachable("unsupported fp type");
1832	}	1832	}
1833	}	1833	}
1834		1834
1835	//===----------------------------------------------------------------------===//	1835	//===----------------------------------------------------------------------===//
1836	// Operand	1836	// Operand
1837	//===----------------------------------------------------------------------===//	1837	//===----------------------------------------------------------------------===//
1838		1838
1839	static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) {	1839	static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) {
1840	bool Lost;	1840	bool Lost;
1841		1841
1842	// Convert literal to single precision	1842	// Convert literal to single precision
1843	APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT),	1843	APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT),
1844	APFloat::rmNearestTiesToEven,	1844	APFloat::rmNearestTiesToEven,
1845	&Lost);	1845	&Lost);
1846	// We allow precision lost but not overflow or underflow	1846	// We allow precision lost but not overflow or underflow
1847	if (Status != APFloat::opOK &&	1847	if (Status != APFloat::opOK &&
1848	Lost &&	1848	Lost &&
1849	((Status & APFloat::opOverflow) != 0 \|\|	1849	((Status & APFloat::opOverflow) != 0 \|\|
1850	(Status & APFloat::opUnderflow) != 0)) {	1850	(Status & APFloat::opUnderflow) != 0)) {
1851	return false;	1851	return false;
1852	}	1852	}
1853		1853
1854	return true;	1854	return true;
1855	}	1855	}
1856		1856
1857	static bool isSafeTruncation(int64_t Val, unsigned Size) {	1857	static bool isSafeTruncation(int64_t Val, unsigned Size) {
1858	return isUIntN(Size, Val) \|\| isIntN(Size, Val);	1858	return isUIntN(Size, Val) \|\| isIntN(Size, Val);
1859	}	1859	}
1860		1860
1861	static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) {	1861	static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) {
1862	if (VT.getScalarType() == MVT::i16) {	1862	if (VT.getScalarType() == MVT::i16) {
1863	// FP immediate values are broken.	1863	// FP immediate values are broken.
1864	return isInlinableIntLiteral(Val);	1864	return isInlinableIntLiteral(Val);
1865	}	1865	}
1866		1866
1867	// f16/v2f16 operands work correctly for all values.	1867	// f16/v2f16 operands work correctly for all values.
1868	return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi);	1868	return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi);
1869	}	1869	}
1870		1870
1871	bool AMDGPUOperand::isInlinableImm(MVT type) const {	1871	bool AMDGPUOperand::isInlinableImm(MVT type) const {
1872		1872
1873	// This is a hack to enable named inline values like	1873	// This is a hack to enable named inline values like
1874	// shared_base with both 32-bit and 64-bit operands.	1874	// shared_base with both 32-bit and 64-bit operands.
1875	// Note that these values are defined as	1875	// Note that these values are defined as
1876	// 32-bit operands only.	1876	// 32-bit operands only.
1877	if (isInlineValue()) {	1877	if (isInlineValue()) {
1878	return true;	1878	return true;
1879	}	1879	}
1880		1880
1881	if (!isImmTy(ImmTyNone)) {	1881	if (!isImmTy(ImmTyNone)) {
1882	// Only plain immediates are inlinable (e.g. "clamp" attribute is not)	1882	// Only plain immediates are inlinable (e.g. "clamp" attribute is not)
1883	return false;	1883	return false;
1884	}	1884	}
1885	// TODO: We should avoid using host float here. It would be better to	1885	// TODO: We should avoid using host float here. It would be better to
1886	// check the float bit values which is what a few other places do.	1886	// check the float bit values which is what a few other places do.
1887	// We've had bot failures before due to weird NaN support on mips hosts.	1887	// We've had bot failures before due to weird NaN support on mips hosts.
1888		1888
1889	APInt Literal(64, Imm.Val);	1889	APInt Literal(64, Imm.Val);
1890		1890
1891	if (Imm.IsFPImm) { // We got fp literal token	1891	if (Imm.IsFPImm) { // We got fp literal token
1892	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	1892	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand
1893	return AMDGPU::isInlinableLiteral64(Imm.Val,	1893	return AMDGPU::isInlinableLiteral64(Imm.Val,
1894	AsmParser->hasInv2PiInlineImm());	1894	AsmParser->hasInv2PiInlineImm());
1895	}	1895	}
1896		1896
1897	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	1897	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
1898	if (!canLosslesslyConvertToFPType(FPLiteral, type))	1898	if (!canLosslesslyConvertToFPType(FPLiteral, type))
1899	return false;	1899	return false;
1900		1900
1901	if (type.getScalarSizeInBits() == 16) {	1901	if (type.getScalarSizeInBits() == 16) {
1902	return isInlineableLiteralOp16(	1902	return isInlineableLiteralOp16(
1903	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	1903	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),
1904	type, AsmParser->hasInv2PiInlineImm());	1904	type, AsmParser->hasInv2PiInlineImm());
1905	}	1905	}
1906		1906
1907	// Check if single precision literal is inlinable	1907	// Check if single precision literal is inlinable
1908	return AMDGPU::isInlinableLiteral32(	1908	return AMDGPU::isInlinableLiteral32(
1909	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	1909	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),
1910	AsmParser->hasInv2PiInlineImm());	1910	AsmParser->hasInv2PiInlineImm());
1911	}	1911	}
1912		1912
1913	// We got int literal token.	1913	// We got int literal token.
1914	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	1914	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand
1915	return AMDGPU::isInlinableLiteral64(Imm.Val,	1915	return AMDGPU::isInlinableLiteral64(Imm.Val,
1916	AsmParser->hasInv2PiInlineImm());	1916	AsmParser->hasInv2PiInlineImm());
1917	}	1917	}
1918		1918
1919	if (!isSafeTruncation(Imm.Val, type.getScalarSizeInBits())) {	1919	if (!isSafeTruncation(Imm.Val, type.getScalarSizeInBits())) {
1920	return false;	1920	return false;
1921	}	1921	}
1922		1922
1923	if (type.getScalarSizeInBits() == 16) {	1923	if (type.getScalarSizeInBits() == 16) {
1924	return isInlineableLiteralOp16(	1924	return isInlineableLiteralOp16(
1925	static_cast(Literal.getLoBits(16).getSExtValue()),	1925	static_cast(Literal.getLoBits(16).getSExtValue()),
1926	type, AsmParser->hasInv2PiInlineImm());	1926	type, AsmParser->hasInv2PiInlineImm());
1927	}	1927	}
1928		1928
1929	return AMDGPU::isInlinableLiteral32(	1929	return AMDGPU::isInlinableLiteral32(
1930	static_cast(Literal.getLoBits(32).getZExtValue()),	1930	static_cast(Literal.getLoBits(32).getZExtValue()),
1931	AsmParser->hasInv2PiInlineImm());	1931	AsmParser->hasInv2PiInlineImm());
1932	}	1932	}
1933		1933
1934	bool AMDGPUOperand::isLiteralImm(MVT type) const {	1934	bool AMDGPUOperand::isLiteralImm(MVT type) const {
1935	// Check that this immediate can be added as literal	1935	// Check that this immediate can be added as literal
1936	if (!isImmTy(ImmTyNone)) {	1936	if (!isImmTy(ImmTyNone)) {
1937	return false;	1937	return false;
1938	}	1938	}
1939		1939
1940	if (!Imm.IsFPImm) {	1940	if (!Imm.IsFPImm) {
1941	// We got int literal token.	1941	// We got int literal token.
1942		1942
1943	if (type == MVT::f64 && hasFPModifiers()) {	1943	if (type == MVT::f64 && hasFPModifiers()) {
1944	// Cannot apply fp modifiers to int literals preserving the same semantics	1944	// Cannot apply fp modifiers to int literals preserving the same semantics
1945	// for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,	1945	// for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,
1946	// disable these cases.	1946	// disable these cases.
1947	return false;	1947	return false;
1948	}	1948	}
1949		1949
1950	unsigned Size = type.getSizeInBits();	1950	unsigned Size = type.getSizeInBits();
1951	if (Size == 64)	1951	if (Size == 64)
1952	Size = 32;	1952	Size = 32;
1953		1953
1954	// FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP	1954	// FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP
1955	// types.	1955	// types.
1956	return isSafeTruncation(Imm.Val, Size);	1956	return isSafeTruncation(Imm.Val, Size);
1957	}	1957	}
1958		1958
1959	// We got fp literal token	1959	// We got fp literal token
1960	if (type == MVT::f64) { // Expected 64-bit fp operand	1960	if (type == MVT::f64) { // Expected 64-bit fp operand
1961	// We would set low 64-bits of literal to zeroes but we accept this literals	1961	// We would set low 64-bits of literal to zeroes but we accept this literals
1962	return true;	1962	return true;
1963	}	1963	}
1964		1964
1965	if (type == MVT::i64) { // Expected 64-bit int operand	1965	if (type == MVT::i64) { // Expected 64-bit int operand
1966	// We don't allow fp literals in 64-bit integer instructions. It is	1966	// We don't allow fp literals in 64-bit integer instructions. It is
1967	// unclear how we should encode them.	1967	// unclear how we should encode them.
1968	return false;	1968	return false;
1969	}	1969	}
1970		1970
1971	// We allow fp literals with f16x2 operands assuming that the specified	1971	// We allow fp literals with f16x2 operands assuming that the specified
1972	// literal goes into the lower half and the upper half is zero. We also	1972	// literal goes into the lower half and the upper half is zero. We also
1973	// require that the literal may be losslessly converted to f16.	1973	// require that the literal may be losslessly converted to f16.
1974	MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :	1974	MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :
1975	(type == MVT::v2i16)? MVT::i16 :	1975	(type == MVT::v2i16)? MVT::i16 :
1976	(type == MVT::v2f32)? MVT::f32 : type;	1976	(type == MVT::v2f32)? MVT::f32 : type;
1977		1977
1978	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	1978	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));
1979	return canLosslesslyConvertToFPType(FPLiteral, ExpectedType);	1979	return canLosslesslyConvertToFPType(FPLiteral, ExpectedType);
1980	}	1980	}
1981		1981
1982	bool AMDGPUOperand::isRegClass(unsigned RCID) const {	1982	bool AMDGPUOperand::isRegClass(unsigned RCID) const {
1983	return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());	1983	return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());
1984	}	1984	}
1985		1985
1986	bool AMDGPUOperand::isVRegWithInputMods() const {	1986	bool AMDGPUOperand::isVRegWithInputMods() const {
1987	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	1987	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|
1988	// GFX90A allows DPP on 64-bit operands.	1988	// GFX90A allows DPP on 64-bit operands.
1989	(isRegClass(AMDGPU::VReg_64RegClassID) &&	1989	(isRegClass(AMDGPU::VReg_64RegClassID) &&
1990	AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]);	1990	AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]);
1991	}	1991	}
1992		1992
1993	bool AMDGPUOperand::isT16VRegWithInputMods() const {	1993	bool AMDGPUOperand::isT16VRegWithInputMods() const {
1994	return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID);	1994	return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID);
1995	}	1995	}
1996		1996
1997	bool AMDGPUOperand::isSDWAOperand(MVT type) const {	1997	bool AMDGPUOperand::isSDWAOperand(MVT type) const {
1998	if (AsmParser->isVI())	1998	if (AsmParser->isVI())
1999	return isVReg32();	1999	return isVReg32();
2000	else if (AsmParser->isGFX9Plus())	2000	else if (AsmParser->isGFX9Plus())
2001	return isRegClass(AMDGPU::VS_32RegClassID) \|\| isInlinableImm(type);	2001	return isRegClass(AMDGPU::VS_32RegClassID) \|\| isInlinableImm(type);
2002	else	2002	else
2003	return false;	2003	return false;
2004	}	2004	}
2005		2005
2006	bool AMDGPUOperand::isSDWAFP16Operand() const {	2006	bool AMDGPUOperand::isSDWAFP16Operand() const {
2007	return isSDWAOperand(MVT::f16);	2007	return isSDWAOperand(MVT::f16);
2008	}	2008	}
2009		2009
2010	bool AMDGPUOperand::isSDWAFP32Operand() const {	2010	bool AMDGPUOperand::isSDWAFP32Operand() const {
2011	return isSDWAOperand(MVT::f32);	2011	return isSDWAOperand(MVT::f32);
2012	}	2012	}
2013		2013
2014	bool AMDGPUOperand::isSDWAInt16Operand() const {	2014	bool AMDGPUOperand::isSDWAInt16Operand() const {
2015	return isSDWAOperand(MVT::i16);	2015	return isSDWAOperand(MVT::i16);
2016	}	2016	}
2017		2017
2018	bool AMDGPUOperand::isSDWAInt32Operand() const {	2018	bool AMDGPUOperand::isSDWAInt32Operand() const {
2019	return isSDWAOperand(MVT::i32);	2019	return isSDWAOperand(MVT::i32);
2020	}	2020	}
2021		2021
2022	bool AMDGPUOperand::isBoolReg() const {	2022	bool AMDGPUOperand::isBoolReg() const {
2023	auto FB = AsmParser->getFeatureBits();	2023	auto FB = AsmParser->getFeatureBits();
2024	return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) \|\|	2024	return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) \|\|
2025	(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));	2025	(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));
2026	}	2026	}
2027		2027
2028	uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const	2028	uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const
2029	{	2029	{
2030	assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	2030	assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
2031	assert(Size == 2 \|\| Size == 4 \|\| Size == 8);	2031	assert(Size == 2 \|\| Size == 4 \|\| Size == 8);
2032		2032
2033	const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));	2033	const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));
2034		2034
2035	if (Imm.Mods.Abs) {	2035	if (Imm.Mods.Abs) {
2036	Val &= ~FpSignMask;	2036	Val &= ~FpSignMask;
2037	}	2037	}
2038	if (Imm.Mods.Neg) {	2038	if (Imm.Mods.Neg) {
2039	Val ^= FpSignMask;	2039	Val ^= FpSignMask;
2040	}	2040	}
2041		2041
2042	return Val;	2042	return Val;
2043	}	2043	}
2044		2044
2045	void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {	2045	void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {
2046	if (isExpr()) {	2046	if (isExpr()) {
2047	Inst.addOperand(MCOperand::createExpr(Expr));	2047	Inst.addOperand(MCOperand::createExpr(Expr));
2048	return;	2048	return;
2049	}	2049	}
2050		2050
2051	if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),	2051	if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
2052	Inst.getNumOperands())) {	2052	Inst.getNumOperands())) {
2053	addLiteralImmOperand(Inst, Imm.Val,	2053	addLiteralImmOperand(Inst, Imm.Val,
2054	ApplyModifiers &	2054	ApplyModifiers &
2055	isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	2055	isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());
2056	} else {	2056	} else {
2057	assert(!isImmTy(ImmTyNone) \|\| !hasModifiers());	2057	assert(!isImmTy(ImmTyNone) \|\| !hasModifiers());
2058	Inst.addOperand(MCOperand::createImm(Imm.Val));	2058	Inst.addOperand(MCOperand::createImm(Imm.Val));
2059	setImmKindNone();	2059	setImmKindNone();
2060	}	2060	}
2061	}	2061	}
2062		2062
2063	void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {	2063	void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {
2064	const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());	2064	const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
2065	auto OpNum = Inst.getNumOperands();	2065	auto OpNum = Inst.getNumOperands();
2066	// Check that this operand accepts literals	2066	// Check that this operand accepts literals
2067	assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));	2067	assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));
2068		2068
2069	if (ApplyModifiers) {	2069	if (ApplyModifiers) {
2070	assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));	2070	assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));
2071	const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);	2071	const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);
2072	Val = applyInputFPModifiers(Val, Size);	2072	Val = applyInputFPModifiers(Val, Size);
2073	}	2073	}
2074		2074
2075	APInt Literal(64, Val);	2075	APInt Literal(64, Val);
2076	uint8_t OpTy = InstDesc.operands()[OpNum].OperandType;	2076	uint8_t OpTy = InstDesc.operands()[OpNum].OperandType;
2077		2077
2078	if (Imm.IsFPImm) { // We got fp literal token	2078	if (Imm.IsFPImm) { // We got fp literal token
2079	switch (OpTy) {	2079	switch (OpTy) {
2080	case AMDGPU::OPERAND_REG_IMM_INT64:	2080	case AMDGPU::OPERAND_REG_IMM_INT64:
2081	case AMDGPU::OPERAND_REG_IMM_FP64:	2081	case AMDGPU::OPERAND_REG_IMM_FP64:
2082	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	2082	case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2083	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	2083	case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2084	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	2084	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2085	if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),	2085	if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),
2086	AsmParser->hasInv2PiInlineImm())) {	2086	AsmParser->hasInv2PiInlineImm())) {
2087	Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));	2087	Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));
2088	setImmKindConst();	2088	setImmKindConst();
2089	return;	2089	return;
2090	}	2090	}
2091		2091
2092	// Non-inlineable	2092	// Non-inlineable
2093	if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand	2093	if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand
2094	// For fp operands we check if low 32 bits are zeros	2094	// For fp operands we check if low 32 bits are zeros
2095	if (Literal.getLoBits(32) != 0) {	2095	if (Literal.getLoBits(32) != 0) {
2096	const_cast(AsmParser)->Warning(Inst.getLoc(),	2096	const_cast(AsmParser)->Warning(Inst.getLoc(),
2097	"Can't encode literal as exact 64-bit floating-point operand. "	2097	"Can't encode literal as exact 64-bit floating-point operand. "
2098	"Low 32-bits will be set to zero");	2098	"Low 32-bits will be set to zero");
2099	}	2099	}
2100		2100
2101	Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue()));	2101	Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue()));
2102	setImmKindLiteral();	2102	setImmKindLiteral();
2103	return;	2103	return;
2104	}	2104	}
2105		2105
2106	// We don't allow fp literals in 64-bit integer instructions. It is	2106	// We don't allow fp literals in 64-bit integer instructions. It is
2107	// unclear how we should encode them. This case should be checked earlier	2107	// unclear how we should encode them. This case should be checked earlier
2108	// in predicate methods (isLiteralImm())	2108	// in predicate methods (isLiteralImm())
2109	llvm_unreachable("fp literal in 64-bit integer instruction.");	2109	llvm_unreachable("fp literal in 64-bit integer instruction.");
2110		2110
2111	case AMDGPU::OPERAND_REG_IMM_INT32:	2111	case AMDGPU::OPERAND_REG_IMM_INT32:
2112	case AMDGPU::OPERAND_REG_IMM_FP32:	2112	case AMDGPU::OPERAND_REG_IMM_FP32:
2113	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	2113	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
2114	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	2114	case AMDGPU::OPERAND_REG_INLINE_C_INT32:
2115	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	2115	case AMDGPU::OPERAND_REG_INLINE_C_FP32:
2116	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	2116	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
2117	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	2117	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
2118	case AMDGPU::OPERAND_REG_IMM_INT16:	2118	case AMDGPU::OPERAND_REG_IMM_INT16:
2119	case AMDGPU::OPERAND_REG_IMM_FP16:	2119	case AMDGPU::OPERAND_REG_IMM_FP16:
2120	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	2120	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
2121	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	2121	case AMDGPU::OPERAND_REG_INLINE_C_INT16:
2122	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	2122	case AMDGPU::OPERAND_REG_INLINE_C_FP16:
2123	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	2123	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2124	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	2124	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2125	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	2125	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
2126	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	2126	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
2127	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	2127	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
2128	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	2128	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
2129	case AMDGPU::OPERAND_REG_IMM_V2INT16:	2129	case AMDGPU::OPERAND_REG_IMM_V2INT16:
2130	case AMDGPU::OPERAND_REG_IMM_V2FP16:	2130	case AMDGPU::OPERAND_REG_IMM_V2FP16:
2131	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	2131	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
2132	case AMDGPU::OPERAND_REG_IMM_V2FP32:	2132	case AMDGPU::OPERAND_REG_IMM_V2FP32:
2133	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	2133	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
2134	case AMDGPU::OPERAND_REG_IMM_V2INT32:	2134	case AMDGPU::OPERAND_REG_IMM_V2INT32:
2135	case AMDGPU::OPERAND_KIMM32:	2135	case AMDGPU::OPERAND_KIMM32:
2136	case AMDGPU::OPERAND_KIMM16: {	2136	case AMDGPU::OPERAND_KIMM16: {
2137	bool lost;	2137	bool lost;
2138	APFloat FPLiteral(APFloat::IEEEdouble(), Literal);	2138	APFloat FPLiteral(APFloat::IEEEdouble(), Literal);
2139	// Convert literal to single precision	2139	// Convert literal to single precision
2140	FPLiteral.convert(*getOpFltSemantics(OpTy),	2140	FPLiteral.convert(*getOpFltSemantics(OpTy),
2141	APFloat::rmNearestTiesToEven, &lost);	2141	APFloat::rmNearestTiesToEven, &lost);
2142	// We allow precision lost but not overflow or underflow. This should be	2142	// We allow precision lost but not overflow or underflow. This should be
2143	// checked earlier in isLiteralImm()	2143	// checked earlier in isLiteralImm()
2144		2144
2145	uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();	2145	uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();
2146	Inst.addOperand(MCOperand::createImm(ImmVal));	2146	Inst.addOperand(MCOperand::createImm(ImmVal));
2147	if (OpTy == AMDGPU::OPERAND_KIMM32 \|\| OpTy == AMDGPU::OPERAND_KIMM16) {	2147	if (OpTy == AMDGPU::OPERAND_KIMM32 \|\| OpTy == AMDGPU::OPERAND_KIMM16) {
2148	setImmKindMandatoryLiteral();	2148	setImmKindMandatoryLiteral();
2149	} else {	2149	} else {
2150	setImmKindLiteral();	2150	setImmKindLiteral();
2151	}	2151	}
2152	return;	2152	return;
2153	}	2153	}
2154	default:	2154	default:
2155	llvm_unreachable("invalid operand size");	2155	llvm_unreachable("invalid operand size");
2156	}	2156	}
2157		2157
2158	return;	2158	return;
2159	}	2159	}
2160		2160
2161	// We got int literal token.	2161	// We got int literal token.
2162	// Only sign extend inline immediates.	2162	// Only sign extend inline immediates.
2163	switch (OpTy) {	2163	switch (OpTy) {
2164	case AMDGPU::OPERAND_REG_IMM_INT32:	2164	case AMDGPU::OPERAND_REG_IMM_INT32:
2165	case AMDGPU::OPERAND_REG_IMM_FP32:	2165	case AMDGPU::OPERAND_REG_IMM_FP32:
2166	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	2166	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
2167	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	2167	case AMDGPU::OPERAND_REG_INLINE_C_INT32:
2168	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	2168	case AMDGPU::OPERAND_REG_INLINE_C_FP32:
2169	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	2169	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
2170	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	2170	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
2171	case AMDGPU::OPERAND_REG_IMM_V2INT16:	2171	case AMDGPU::OPERAND_REG_IMM_V2INT16:
2172	case AMDGPU::OPERAND_REG_IMM_V2FP16:	2172	case AMDGPU::OPERAND_REG_IMM_V2FP16:
2173	case AMDGPU::OPERAND_REG_IMM_V2FP32:	2173	case AMDGPU::OPERAND_REG_IMM_V2FP32:
2174	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	2174	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
2175	case AMDGPU::OPERAND_REG_IMM_V2INT32:	2175	case AMDGPU::OPERAND_REG_IMM_V2INT32:
2176	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	2176	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
2177	if (isSafeTruncation(Val, 32) &&	2177	if (isSafeTruncation(Val, 32) &&
2178	AMDGPU::isInlinableLiteral32(static_cast(Val),	2178	AMDGPU::isInlinableLiteral32(static_cast(Val),
2179	AsmParser->hasInv2PiInlineImm())) {	2179	AsmParser->hasInv2PiInlineImm())) {
2180	Inst.addOperand(MCOperand::createImm(Val));	2180	Inst.addOperand(MCOperand::createImm(Val));
2181	setImmKindConst();	2181	setImmKindConst();
2182	return;	2182	return;
2183	}	2183	}
2184		2184
2185	Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));	2185	Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));
2186	setImmKindLiteral();	2186	setImmKindLiteral();
2187	return;	2187	return;
2188		2188
2189	case AMDGPU::OPERAND_REG_IMM_INT64:	2189	case AMDGPU::OPERAND_REG_IMM_INT64:
2190	case AMDGPU::OPERAND_REG_IMM_FP64:	2190	case AMDGPU::OPERAND_REG_IMM_FP64:
2191	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	2191	case AMDGPU::OPERAND_REG_INLINE_C_INT64:
2192	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	2192	case AMDGPU::OPERAND_REG_INLINE_C_FP64:
2193	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	2193	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
2194	if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {	2194	if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {
2195	Inst.addOperand(MCOperand::createImm(Val));	2195	Inst.addOperand(MCOperand::createImm(Val));
2196	setImmKindConst();	2196	setImmKindConst();
2197	return;	2197	return;
2198	}	2198	}
2199		2199
2200	Inst.addOperand(MCOperand::createImm(Lo_32(Val)));	2200	Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
2201	setImmKindLiteral();	2201	setImmKindLiteral();
2202	return;	2202	return;
2203		2203
2204	case AMDGPU::OPERAND_REG_IMM_INT16:	2204	case AMDGPU::OPERAND_REG_IMM_INT16:
2205	case AMDGPU::OPERAND_REG_IMM_FP16:	2205	case AMDGPU::OPERAND_REG_IMM_FP16:
2206	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	2206	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
2207	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	2207	case AMDGPU::OPERAND_REG_INLINE_C_INT16:
2208	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	2208	case AMDGPU::OPERAND_REG_INLINE_C_FP16:
2209	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	2209	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
2210	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	2210	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
2211	if (isSafeTruncation(Val, 16) &&	2211	if (isSafeTruncation(Val, 16) &&
2212	AMDGPU::isInlinableLiteral16(static_cast(Val),	2212	AMDGPU::isInlinableLiteral16(static_cast(Val),
2213	AsmParser->hasInv2PiInlineImm())) {	2213	AsmParser->hasInv2PiInlineImm())) {
2214	Inst.addOperand(MCOperand::createImm(Val));	2214	Inst.addOperand(MCOperand::createImm(Val));
2215	setImmKindConst();	2215	setImmKindConst();
2216	return;	2216	return;
2217	}	2217	}
2218		2218
2219	Inst.addOperand(MCOperand::createImm(Val & 0xffff));	2219	Inst.addOperand(MCOperand::createImm(Val & 0xffff));
2220	setImmKindLiteral();	2220	setImmKindLiteral();
2221	return;	2221	return;
2222		2222
2223	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	2223	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
2224	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	2224	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
2225	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	2225	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
2226	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {	2226	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {
2227	assert(isSafeTruncation(Val, 16));	2227	assert(isSafeTruncation(Val, 16));
2228	assert(AMDGPU::isInlinableLiteral16(static_cast(Val),	2228	assert(AMDGPU::isInlinableLiteral16(static_cast(Val),
2229	AsmParser->hasInv2PiInlineImm()));	2229	AsmParser->hasInv2PiInlineImm()));
2230		2230
2231	Inst.addOperand(MCOperand::createImm(Val));	2231	Inst.addOperand(MCOperand::createImm(Val));
2232	return;	2232	return;
2233	}	2233	}
2234	case AMDGPU::OPERAND_KIMM32:	2234	case AMDGPU::OPERAND_KIMM32:
2235	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));	2235	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));
2236	setImmKindMandatoryLiteral();	2236	setImmKindMandatoryLiteral();
2237	return;	2237	return;
2238	case AMDGPU::OPERAND_KIMM16:	2238	case AMDGPU::OPERAND_KIMM16:
2239	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));	2239	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));
2240	setImmKindMandatoryLiteral();	2240	setImmKindMandatoryLiteral();
2241	return;	2241	return;
2242	default:	2242	default:
2243	llvm_unreachable("invalid operand size");	2243	llvm_unreachable("invalid operand size");
2244	}	2244	}
2245	}	2245	}
2246		2246
2247	void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {	2247	void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {
2248	Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));	2248	Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));
2249	}	2249	}
2250		2250
2251	bool AMDGPUOperand::isInlineValue() const {	2251	bool AMDGPUOperand::isInlineValue() const {
2252	return isRegKind() && ::isInlineValue(getReg());	2252	return isRegKind() && ::isInlineValue(getReg());
2253	}	2253	}
2254		2254
2255	//===----------------------------------------------------------------------===//	2255	//===----------------------------------------------------------------------===//
2256	// AsmParser	2256	// AsmParser
2257	//===----------------------------------------------------------------------===//	2257	//===----------------------------------------------------------------------===//
2258		2258
2259	static int getRegClass(RegisterKind Is, unsigned RegWidth) {	2259	static int getRegClass(RegisterKind Is, unsigned RegWidth) {
2260	if (Is == IS_VGPR) {	2260	if (Is == IS_VGPR) {
2261	switch (RegWidth) {	2261	switch (RegWidth) {
2262	default: return -1;	2262	default: return -1;
2263	case 32:	2263	case 32:
2264	return AMDGPU::VGPR_32RegClassID;	2264	return AMDGPU::VGPR_32RegClassID;
2265	case 64:	2265	case 64:
2266	return AMDGPU::VReg_64RegClassID;	2266	return AMDGPU::VReg_64RegClassID;
2267	case 96:	2267	case 96:
2268	return AMDGPU::VReg_96RegClassID;	2268	return AMDGPU::VReg_96RegClassID;
2269	case 128:	2269	case 128:
2270	return AMDGPU::VReg_128RegClassID;	2270	return AMDGPU::VReg_128RegClassID;
2271	case 160:	2271	case 160:
2272	return AMDGPU::VReg_160RegClassID;	2272	return AMDGPU::VReg_160RegClassID;
2273	case 192:	2273	case 192:
2274	return AMDGPU::VReg_192RegClassID;	2274	return AMDGPU::VReg_192RegClassID;
2275	case 224:	2275	case 224:
2276	return AMDGPU::VReg_224RegClassID;	2276	return AMDGPU::VReg_224RegClassID;
2277	case 256:	2277	case 256:
2278	return AMDGPU::VReg_256RegClassID;	2278	return AMDGPU::VReg_256RegClassID;
2279	case 288:	2279	case 288:
2280	return AMDGPU::VReg_288RegClassID;	2280	return AMDGPU::VReg_288RegClassID;
2281	case 320:	2281	case 320:
2282	return AMDGPU::VReg_320RegClassID;	2282	return AMDGPU::VReg_320RegClassID;
2283	case 352:	2283	case 352:
2284	return AMDGPU::VReg_352RegClassID;	2284	return AMDGPU::VReg_352RegClassID;
2285	case 384:	2285	case 384:
2286	return AMDGPU::VReg_384RegClassID;	2286	return AMDGPU::VReg_384RegClassID;
2287	case 512:	2287	case 512:
2288	return AMDGPU::VReg_512RegClassID;	2288	return AMDGPU::VReg_512RegClassID;
2289	case 1024:	2289	case 1024:
2290	return AMDGPU::VReg_1024RegClassID;	2290	return AMDGPU::VReg_1024RegClassID;
2291	}	2291	}
2292	} else if (Is == IS_TTMP) {	2292	} else if (Is == IS_TTMP) {
2293	switch (RegWidth) {	2293	switch (RegWidth) {
2294	default: return -1;	2294	default: return -1;
2295	case 32:	2295	case 32:
2296	return AMDGPU::TTMP_32RegClassID;	2296	return AMDGPU::TTMP_32RegClassID;
2297	case 64:	2297	case 64:
2298	return AMDGPU::TTMP_64RegClassID;	2298	return AMDGPU::TTMP_64RegClassID;
2299	case 128:	2299	case 128:
2300	return AMDGPU::TTMP_128RegClassID;	2300	return AMDGPU::TTMP_128RegClassID;
2301	case 256:	2301	case 256:
2302	return AMDGPU::TTMP_256RegClassID;	2302	return AMDGPU::TTMP_256RegClassID;
2303	case 512:	2303	case 512:
2304	return AMDGPU::TTMP_512RegClassID;	2304	return AMDGPU::TTMP_512RegClassID;
2305	}	2305	}
2306	} else if (Is == IS_SGPR) {	2306	} else if (Is == IS_SGPR) {
2307	switch (RegWidth) {	2307	switch (RegWidth) {
2308	default: return -1;	2308	default: return -1;
2309	case 32:	2309	case 32:
2310	return AMDGPU::SGPR_32RegClassID;	2310	return AMDGPU::SGPR_32RegClassID;
2311	case 64:	2311	case 64:
2312	return AMDGPU::SGPR_64RegClassID;	2312	return AMDGPU::SGPR_64RegClassID;
2313	case 96:	2313	case 96:
2314	return AMDGPU::SGPR_96RegClassID;	2314	return AMDGPU::SGPR_96RegClassID;
2315	case 128:	2315	case 128:
2316	return AMDGPU::SGPR_128RegClassID;	2316	return AMDGPU::SGPR_128RegClassID;
2317	case 160:	2317	case 160:
2318	return AMDGPU::SGPR_160RegClassID;	2318	return AMDGPU::SGPR_160RegClassID;
2319	case 192:	2319	case 192:
2320	return AMDGPU::SGPR_192RegClassID;	2320	return AMDGPU::SGPR_192RegClassID;
2321	case 224:	2321	case 224:
2322	return AMDGPU::SGPR_224RegClassID;	2322	return AMDGPU::SGPR_224RegClassID;
2323	case 256:	2323	case 256:
2324	return AMDGPU::SGPR_256RegClassID;	2324	return AMDGPU::SGPR_256RegClassID;
2325	case 288:	2325	case 288:
2326	return AMDGPU::SGPR_288RegClassID;	2326	return AMDGPU::SGPR_288RegClassID;
2327	case 320:	2327	case 320:
2328	return AMDGPU::SGPR_320RegClassID;	2328	return AMDGPU::SGPR_320RegClassID;
2329	case 352:	2329	case 352:
2330	return AMDGPU::SGPR_352RegClassID;	2330	return AMDGPU::SGPR_352RegClassID;
2331	case 384:	2331	case 384:
2332	return AMDGPU::SGPR_384RegClassID;	2332	return AMDGPU::SGPR_384RegClassID;
2333	case 512:	2333	case 512:
2334	return AMDGPU::SGPR_512RegClassID;	2334	return AMDGPU::SGPR_512RegClassID;
2335	}	2335	}
2336	} else if (Is == IS_AGPR) {	2336	} else if (Is == IS_AGPR) {
2337	switch (RegWidth) {	2337	switch (RegWidth) {
2338	default: return -1;	2338	default: return -1;
2339	case 32:	2339	case 32:
2340	return AMDGPU::AGPR_32RegClassID;	2340	return AMDGPU::AGPR_32RegClassID;
2341	case 64:	2341	case 64:
2342	return AMDGPU::AReg_64RegClassID;	2342	return AMDGPU::AReg_64RegClassID;
2343	case 96:	2343	case 96:
2344	return AMDGPU::AReg_96RegClassID;	2344	return AMDGPU::AReg_96RegClassID;
2345	case 128:	2345	case 128:
2346	return AMDGPU::AReg_128RegClassID;	2346	return AMDGPU::AReg_128RegClassID;
2347	case 160:	2347	case 160:
2348	return AMDGPU::AReg_160RegClassID;	2348	return AMDGPU::AReg_160RegClassID;
2349	case 192:	2349	case 192:
2350	return AMDGPU::AReg_192RegClassID;	2350	return AMDGPU::AReg_192RegClassID;
2351	case 224:	2351	case 224:
2352	return AMDGPU::AReg_224RegClassID;	2352	return AMDGPU::AReg_224RegClassID;
2353	case 256:	2353	case 256:
2354	return AMDGPU::AReg_256RegClassID;	2354	return AMDGPU::AReg_256RegClassID;
2355	case 288:	2355	case 288:
2356	return AMDGPU::AReg_288RegClassID;	2356	return AMDGPU::AReg_288RegClassID;
2357	case 320:	2357	case 320:
2358	return AMDGPU::AReg_320RegClassID;	2358	return AMDGPU::AReg_320RegClassID;
2359	case 352:	2359	case 352:
2360	return AMDGPU::AReg_352RegClassID;	2360	return AMDGPU::AReg_352RegClassID;
2361	case 384:	2361	case 384:
2362	return AMDGPU::AReg_384RegClassID;	2362	return AMDGPU::AReg_384RegClassID;
2363	case 512:	2363	case 512:
2364	return AMDGPU::AReg_512RegClassID;	2364	return AMDGPU::AReg_512RegClassID;
2365	case 1024:	2365	case 1024:
2366	return AMDGPU::AReg_1024RegClassID;	2366	return AMDGPU::AReg_1024RegClassID;
2367	}	2367	}
2368	}	2368	}
2369	return -1;	2369	return -1;
2370	}	2370	}
2371		2371
2372	static unsigned getSpecialRegForName(StringRef RegName) {	2372	static unsigned getSpecialRegForName(StringRef RegName) {
2373	return StringSwitch(RegName)	2373	return StringSwitch(RegName)
2374	.Case("exec", AMDGPU::EXEC)	2374	.Case("exec", AMDGPU::EXEC)
2375	.Case("vcc", AMDGPU::VCC)	2375	.Case("vcc", AMDGPU::VCC)
2376	.Case("flat_scratch", AMDGPU::FLAT_SCR)	2376	.Case("flat_scratch", AMDGPU::FLAT_SCR)
2377	.Case("xnack_mask", AMDGPU::XNACK_MASK)	2377	.Case("xnack_mask", AMDGPU::XNACK_MASK)
2378	.Case("shared_base", AMDGPU::SRC_SHARED_BASE)	2378	.Case("shared_base", AMDGPU::SRC_SHARED_BASE)
2379	.Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)	2379	.Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)
2380	.Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT)	2380	.Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT)
2381	.Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)	2381	.Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)
2382	.Case("private_base", AMDGPU::SRC_PRIVATE_BASE)	2382	.Case("private_base", AMDGPU::SRC_PRIVATE_BASE)
2383	.Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)	2383	.Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)
2384	.Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	2384	.Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT)
2385	.Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	2385	.Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)
2386	.Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	2386	.Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)
2387	.Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	2387	.Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)
2388	.Case("lds_direct", AMDGPU::LDS_DIRECT)	2388	.Case("lds_direct", AMDGPU::LDS_DIRECT)
2389	.Case("src_lds_direct", AMDGPU::LDS_DIRECT)	2389	.Case("src_lds_direct", AMDGPU::LDS_DIRECT)
2390	.Case("m0", AMDGPU::M0)	2390	.Case("m0", AMDGPU::M0)
2391	.Case("vccz", AMDGPU::SRC_VCCZ)	2391	.Case("vccz", AMDGPU::SRC_VCCZ)
2392	.Case("src_vccz", AMDGPU::SRC_VCCZ)	2392	.Case("src_vccz", AMDGPU::SRC_VCCZ)
2393	.Case("execz", AMDGPU::SRC_EXECZ)	2393	.Case("execz", AMDGPU::SRC_EXECZ)
2394	.Case("src_execz", AMDGPU::SRC_EXECZ)	2394	.Case("src_execz", AMDGPU::SRC_EXECZ)
2395	.Case("scc", AMDGPU::SRC_SCC)	2395	.Case("scc", AMDGPU::SRC_SCC)
2396	.Case("src_scc", AMDGPU::SRC_SCC)	2396	.Case("src_scc", AMDGPU::SRC_SCC)
2397	.Case("tba", AMDGPU::TBA)	2397	.Case("tba", AMDGPU::TBA)
2398	.Case("tma", AMDGPU::TMA)	2398	.Case("tma", AMDGPU::TMA)
2399	.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)	2399	.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
2400	.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)	2400	.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
2401	.Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)	2401	.Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)
2402	.Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)	2402	.Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)
2403	.Case("vcc_lo", AMDGPU::VCC_LO)	2403	.Case("vcc_lo", AMDGPU::VCC_LO)
2404	.Case("vcc_hi", AMDGPU::VCC_HI)	2404	.Case("vcc_hi", AMDGPU::VCC_HI)
2405	.Case("exec_lo", AMDGPU::EXEC_LO)	2405	.Case("exec_lo", AMDGPU::EXEC_LO)
2406	.Case("exec_hi", AMDGPU::EXEC_HI)	2406	.Case("exec_hi", AMDGPU::EXEC_HI)
2407	.Case("tma_lo", AMDGPU::TMA_LO)	2407	.Case("tma_lo", AMDGPU::TMA_LO)
2408	.Case("tma_hi", AMDGPU::TMA_HI)	2408	.Case("tma_hi", AMDGPU::TMA_HI)
2409	.Case("tba_lo", AMDGPU::TBA_LO)	2409	.Case("tba_lo", AMDGPU::TBA_LO)
2410	.Case("tba_hi", AMDGPU::TBA_HI)	2410	.Case("tba_hi", AMDGPU::TBA_HI)
2411	.Case("pc", AMDGPU::PC_REG)	2411	.Case("pc", AMDGPU::PC_REG)
2412	.Case("null", AMDGPU::SGPR_NULL)	2412	.Case("null", AMDGPU::SGPR_NULL)
2413	.Default(AMDGPU::NoRegister);	2413	.Default(AMDGPU::NoRegister);
2414	}	2414	}
2415		2415
2416	bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	2416	bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,
2417	SMLoc &EndLoc, bool RestoreOnFailure) {	2417	SMLoc &EndLoc, bool RestoreOnFailure) {
2418	auto R = parseRegister();	2418	auto R = parseRegister();
2419	if (!R) return true;	2419	if (!R) return true;
2420	assert(R->isReg());	2420	assert(R->isReg());
2421	RegNo = R->getReg();	2421	RegNo = R->getReg();
2422	StartLoc = R->getStartLoc();	2422	StartLoc = R->getStartLoc();
2423	EndLoc = R->getEndLoc();	2423	EndLoc = R->getEndLoc();
2424	return false;	2424	return false;
2425	}	2425	}
2426		2426
2427	bool AMDGPUAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	2427	bool AMDGPUAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,
2428	SMLoc &EndLoc) {	2428	SMLoc &EndLoc) {
2429	return ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/false);	2429	return ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/false);
2430	}	2430	}
2431		2431
2432	OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(MCRegister &RegNo,	2432	OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(MCRegister &RegNo,
2433	SMLoc &StartLoc,	2433	SMLoc &StartLoc,
2434	SMLoc &EndLoc) {	2434	SMLoc &EndLoc) {
2435	bool Result =	2435	bool Result =
2436	ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/true);	2436	ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/true);
2437	bool PendingErrors = getParser().hasPendingError();	2437	bool PendingErrors = getParser().hasPendingError();
2438	getParser().clearPendingErrors();	2438	getParser().clearPendingErrors();
2439	if (PendingErrors)	2439	if (PendingErrors)
2440	return MatchOperand_ParseFail;	2440	return MatchOperand_ParseFail;
2441	if (Result)	2441	if (Result)
2442	return MatchOperand_NoMatch;	2442	return MatchOperand_NoMatch;
2443	return MatchOperand_Success;	2443	return MatchOperand_Success;
2444	}	2444	}
2445		2445
2446	bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,	2446	bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,
2447	RegisterKind RegKind, unsigned Reg1,	2447	RegisterKind RegKind, unsigned Reg1,
2448	SMLoc Loc) {	2448	SMLoc Loc) {
2449	switch (RegKind) {	2449	switch (RegKind) {
2450	case IS_SPECIAL:	2450	case IS_SPECIAL:
2451	if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {	2451	if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {
2452	Reg = AMDGPU::EXEC;	2452	Reg = AMDGPU::EXEC;
2453	RegWidth = 64;	2453	RegWidth = 64;
2454	return true;	2454	return true;
2455	}	2455	}
2456	if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {	2456	if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {
2457	Reg = AMDGPU::FLAT_SCR;	2457	Reg = AMDGPU::FLAT_SCR;
2458	RegWidth = 64;	2458	RegWidth = 64;
2459	return true;	2459	return true;
2460	}	2460	}
2461	if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {	2461	if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {
2462	Reg = AMDGPU::XNACK_MASK;	2462	Reg = AMDGPU::XNACK_MASK;
2463	RegWidth = 64;	2463	RegWidth = 64;
2464	return true;	2464	return true;
2465	}	2465	}
2466	if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {	2466	if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {
2467	Reg = AMDGPU::VCC;	2467	Reg = AMDGPU::VCC;
2468	RegWidth = 64;	2468	RegWidth = 64;
2469	return true;	2469	return true;
2470	}	2470	}
2471	if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {	2471	if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {
2472	Reg = AMDGPU::TBA;	2472	Reg = AMDGPU::TBA;
2473	RegWidth = 64;	2473	RegWidth = 64;
2474	return true;	2474	return true;
2475	}	2475	}
2476	if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {	2476	if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {
2477	Reg = AMDGPU::TMA;	2477	Reg = AMDGPU::TMA;
2478	RegWidth = 64;	2478	RegWidth = 64;
2479	return true;	2479	return true;
2480	}	2480	}
2481	Error(Loc, "register does not fit in the list");	2481	Error(Loc, "register does not fit in the list");
2482	return false;	2482	return false;
2483	case IS_VGPR:	2483	case IS_VGPR:
2484	case IS_SGPR:	2484	case IS_SGPR:
2485	case IS_AGPR:	2485	case IS_AGPR:
2486	case IS_TTMP:	2486	case IS_TTMP:
2487	if (Reg1 != Reg + RegWidth / 32) {	2487	if (Reg1 != Reg + RegWidth / 32) {
2488	Error(Loc, "registers in a list must have consecutive indices");	2488	Error(Loc, "registers in a list must have consecutive indices");
2489	return false;	2489	return false;
2490	}	2490	}
2491	RegWidth += 32;	2491	RegWidth += 32;
2492	return true;	2492	return true;
2493	default:	2493	default:
2494	llvm_unreachable("unexpected register kind");	2494	llvm_unreachable("unexpected register kind");
2495	}	2495	}
2496	}	2496	}
2497		2497
2498	struct RegInfo {	2498	struct RegInfo {
2499	StringLiteral Name;	2499	StringLiteral Name;
2500	RegisterKind Kind;	2500	RegisterKind Kind;
2501	};	2501	};
2502		2502
2503	static constexpr RegInfo RegularRegisters[] = {	2503	static constexpr RegInfo RegularRegisters[] = {
2504	{{"v"}, IS_VGPR},	2504	{{"v"}, IS_VGPR},
2505	{{"s"}, IS_SGPR},	2505	{{"s"}, IS_SGPR},
2506	{{"ttmp"}, IS_TTMP},	2506	{{"ttmp"}, IS_TTMP},
2507	{{"acc"}, IS_AGPR},	2507	{{"acc"}, IS_AGPR},
2508	{{"a"}, IS_AGPR},	2508	{{"a"}, IS_AGPR},
2509	};	2509	};
2510		2510
2511	static bool isRegularReg(RegisterKind Kind) {	2511	static bool isRegularReg(RegisterKind Kind) {
2512	return Kind == IS_VGPR \|\|	2512	return Kind == IS_VGPR \|\|
2513	Kind == IS_SGPR \|\|	2513	Kind == IS_SGPR \|\|
2514	Kind == IS_TTMP \|\|	2514	Kind == IS_TTMP \|\|
2515	Kind == IS_AGPR;	2515	Kind == IS_AGPR;
2516	}	2516	}
2517		2517
2518	static const RegInfo* getRegularRegInfo(StringRef Str) {	2518	static const RegInfo* getRegularRegInfo(StringRef Str) {
2519	for (const RegInfo &Reg : RegularRegisters)	2519	for (const RegInfo &Reg : RegularRegisters)
2520	if (Str.startswith(Reg.Name))	2520	if (Str.startswith(Reg.Name))
2521	return &Reg;	2521	return &Reg;
2522	return nullptr;	2522	return nullptr;
2523	}	2523	}
2524		2524
2525	static bool getRegNum(StringRef Str, unsigned& Num) {	2525	static bool getRegNum(StringRef Str, unsigned& Num) {
2526	return !Str.getAsInteger(10, Num);	2526	return !Str.getAsInteger(10, Num);
2527	}	2527	}
2528		2528
2529	bool	2529	bool
2530	AMDGPUAsmParser::isRegister(const AsmToken &Token,	2530	AMDGPUAsmParser::isRegister(const AsmToken &Token,
2531	const AsmToken &NextToken) const {	2531	const AsmToken &NextToken) const {
2532		2532
2533	// A list of consecutive registers: [s0,s1,s2,s3]	2533	// A list of consecutive registers: [s0,s1,s2,s3]
2534	if (Token.is(AsmToken::LBrac))	2534	if (Token.is(AsmToken::LBrac))
2535	return true;	2535	return true;
2536		2536
2537	if (!Token.is(AsmToken::Identifier))	2537	if (!Token.is(AsmToken::Identifier))
2538	return false;	2538	return false;
2539		2539
2540	// A single register like s0 or a range of registers like s[0:1]	2540	// A single register like s0 or a range of registers like s[0:1]
2541		2541
2542	StringRef Str = Token.getString();	2542	StringRef Str = Token.getString();
2543	const RegInfo *Reg = getRegularRegInfo(Str);	2543	const RegInfo *Reg = getRegularRegInfo(Str);
2544	if (Reg) {	2544	if (Reg) {
2545	StringRef RegName = Reg->Name;	2545	StringRef RegName = Reg->Name;
2546	StringRef RegSuffix = Str.substr(RegName.size());	2546	StringRef RegSuffix = Str.substr(RegName.size());
2547	if (!RegSuffix.empty()) {	2547	if (!RegSuffix.empty()) {
2548	unsigned Num;	2548	unsigned Num;
2549	// A single register with an index: rXX	2549	// A single register with an index: rXX
2550	if (getRegNum(RegSuffix, Num))	2550	if (getRegNum(RegSuffix, Num))
2551	return true;	2551	return true;
2552	} else {	2552	} else {
2553	// A range of registers: r[XX:YY].	2553	// A range of registers: r[XX:YY].
2554	if (NextToken.is(AsmToken::LBrac))	2554	if (NextToken.is(AsmToken::LBrac))
2555	return true;	2555	return true;
2556	}	2556	}
2557	}	2557	}
2558		2558
2559	return getSpecialRegForName(Str) != AMDGPU::NoRegister;	2559	return getSpecialRegForName(Str) != AMDGPU::NoRegister;
2560	}	2560	}
2561		2561
2562	bool	2562	bool
2563	AMDGPUAsmParser::isRegister()	2563	AMDGPUAsmParser::isRegister()
2564	{	2564	{
2565	return isRegister(getToken(), peekToken());	2565	return isRegister(getToken(), peekToken());
2566	}	2566	}
2567		2567
2568	unsigned	2568	unsigned
2569	AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,	2569	AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,
2570	unsigned RegNum,	2570	unsigned RegNum,
2571	unsigned RegWidth,	2571	unsigned RegWidth,
2572	SMLoc Loc) {	2572	SMLoc Loc) {
2573		2573
2574	assert(isRegularReg(RegKind));	2574	assert(isRegularReg(RegKind));
2575		2575
2576	unsigned AlignSize = 1;	2576	unsigned AlignSize = 1;
2577	if (RegKind == IS_SGPR \|\| RegKind == IS_TTMP) {	2577	if (RegKind == IS_SGPR \|\| RegKind == IS_TTMP) {
2578	// SGPR and TTMP registers must be aligned.	2578	// SGPR and TTMP registers must be aligned.
2579	// Max required alignment is 4 dwords.	2579	// Max required alignment is 4 dwords.
2580	AlignSize = std::min(RegWidth / 32, 4u);	2580	AlignSize = std::min(RegWidth / 32, 4u);
2581	}	2581	}
2582		2582
2583	if (RegNum % AlignSize != 0) {	2583	if (RegNum % AlignSize != 0) {
2584	Error(Loc, "invalid register alignment");	2584	Error(Loc, "invalid register alignment");
2585	return AMDGPU::NoRegister;	2585	return AMDGPU::NoRegister;
2586	}	2586	}
2587		2587
2588	unsigned RegIdx = RegNum / AlignSize;	2588	unsigned RegIdx = RegNum / AlignSize;
2589	int RCID = getRegClass(RegKind, RegWidth);	2589	int RCID = getRegClass(RegKind, RegWidth);
2590	if (RCID == -1) {	2590	if (RCID == -1) {
2591	Error(Loc, "invalid or unsupported register size");	2591	Error(Loc, "invalid or unsupported register size");
2592	return AMDGPU::NoRegister;	2592	return AMDGPU::NoRegister;
2593	}	2593	}
2594		2594
2595	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	2595	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
2596	const MCRegisterClass RC = TRI->getRegClass(RCID);	2596	const MCRegisterClass RC = TRI->getRegClass(RCID);
2597	if (RegIdx >= RC.getNumRegs()) {	2597	if (RegIdx >= RC.getNumRegs()) {
2598	Error(Loc, "register index is out of range");	2598	Error(Loc, "register index is out of range");
2599	return AMDGPU::NoRegister;	2599	return AMDGPU::NoRegister;
2600	}	2600	}
2601		2601
2602	return RC.getRegister(RegIdx);	2602	return RC.getRegister(RegIdx);
2603	}	2603	}
2604		2604
2605	bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {	2605	bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {
2606	int64_t RegLo, RegHi;	2606	int64_t RegLo, RegHi;
2607	if (!skipToken(AsmToken::LBrac, "missing register index"))	2607	if (!skipToken(AsmToken::LBrac, "missing register index"))
2608	return false;	2608	return false;
2609		2609
2610	SMLoc FirstIdxLoc = getLoc();	2610	SMLoc FirstIdxLoc = getLoc();
2611	SMLoc SecondIdxLoc;	2611	SMLoc SecondIdxLoc;
2612		2612
2613	if (!parseExpr(RegLo))	2613	if (!parseExpr(RegLo))
2614	return false;	2614	return false;
2615		2615
2616	if (trySkipToken(AsmToken::Colon)) {	2616	if (trySkipToken(AsmToken::Colon)) {
2617	SecondIdxLoc = getLoc();	2617	SecondIdxLoc = getLoc();
2618	if (!parseExpr(RegHi))	2618	if (!parseExpr(RegHi))
2619	return false;	2619	return false;
2620	} else {	2620	} else {
2621	RegHi = RegLo;	2621	RegHi = RegLo;
2622	}	2622	}
2623		2623
2624	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	2624	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
2625	return false;	2625	return false;
2626		2626
2627	if (!isUInt<32>(RegLo)) {	2627	if (!isUInt<32>(RegLo)) {
2628	Error(FirstIdxLoc, "invalid register index");	2628	Error(FirstIdxLoc, "invalid register index");
2629	return false;	2629	return false;
2630	}	2630	}
2631		2631
2632	if (!isUInt<32>(RegHi)) {	2632	if (!isUInt<32>(RegHi)) {
2633	Error(SecondIdxLoc, "invalid register index");	2633	Error(SecondIdxLoc, "invalid register index");
2634	return false;	2634	return false;
2635	}	2635	}
2636		2636
2637	if (RegLo > RegHi) {	2637	if (RegLo > RegHi) {
2638	Error(FirstIdxLoc, "first register index should not exceed second index");	2638	Error(FirstIdxLoc, "first register index should not exceed second index");
2639	return false;	2639	return false;
2640	}	2640	}
2641		2641
2642	Num = static_cast(RegLo);	2642	Num = static_cast(RegLo);
2643	RegWidth = 32 * ((RegHi - RegLo) + 1);	2643	RegWidth = 32 * ((RegHi - RegLo) + 1);
2644	return true;	2644	return true;
2645	}	2645	}
2646		2646
2647	unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,	2647	unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,
2648	unsigned &RegNum, unsigned &RegWidth,	2648	unsigned &RegNum, unsigned &RegWidth,
2649	SmallVectorImpl &Tokens) {	2649	SmallVectorImpl &Tokens) {
2650	assert(isToken(AsmToken::Identifier));	2650	assert(isToken(AsmToken::Identifier));
2651	unsigned Reg = getSpecialRegForName(getTokenStr());	2651	unsigned Reg = getSpecialRegForName(getTokenStr());
2652	if (Reg) {	2652	if (Reg) {
2653	RegNum = 0;	2653	RegNum = 0;
2654	RegWidth = 32;	2654	RegWidth = 32;
2655	RegKind = IS_SPECIAL;	2655	RegKind = IS_SPECIAL;
2656	Tokens.push_back(getToken());	2656	Tokens.push_back(getToken());
2657	lex(); // skip register name	2657	lex(); // skip register name
2658	}	2658	}
2659	return Reg;	2659	return Reg;
2660	}	2660	}
2661		2661
2662	unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,	2662	unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,
2663	unsigned &RegNum, unsigned &RegWidth,	2663	unsigned &RegNum, unsigned &RegWidth,
2664	SmallVectorImpl &Tokens) {	2664	SmallVectorImpl &Tokens) {
2665	assert(isToken(AsmToken::Identifier));	2665	assert(isToken(AsmToken::Identifier));
2666	StringRef RegName = getTokenStr();	2666	StringRef RegName = getTokenStr();
2667	auto Loc = getLoc();	2667	auto Loc = getLoc();
2668		2668
2669	const RegInfo *RI = getRegularRegInfo(RegName);	2669	const RegInfo *RI = getRegularRegInfo(RegName);
2670	if (!RI) {	2670	if (!RI) {
2671	Error(Loc, "invalid register name");	2671	Error(Loc, "invalid register name");
2672	return AMDGPU::NoRegister;	2672	return AMDGPU::NoRegister;
2673	}	2673	}
2674		2674
2675	Tokens.push_back(getToken());	2675	Tokens.push_back(getToken());
2676	lex(); // skip register name	2676	lex(); // skip register name
2677		2677
2678	RegKind = RI->Kind;	2678	RegKind = RI->Kind;
2679	StringRef RegSuffix = RegName.substr(RI->Name.size());	2679	StringRef RegSuffix = RegName.substr(RI->Name.size());
2680	if (!RegSuffix.empty()) {	2680	if (!RegSuffix.empty()) {
2681	// Single 32-bit register: vXX.	2681	// Single 32-bit register: vXX.
2682	if (!getRegNum(RegSuffix, RegNum)) {	2682	if (!getRegNum(RegSuffix, RegNum)) {
2683	Error(Loc, "invalid register index");	2683	Error(Loc, "invalid register index");
2684	return AMDGPU::NoRegister;	2684	return AMDGPU::NoRegister;
2685	}	2685	}
2686	RegWidth = 32;	2686	RegWidth = 32;
2687	} else {	2687	} else {
2688	// Range of registers: v[XX:YY]. ":YY" is optional.	2688	// Range of registers: v[XX:YY]. ":YY" is optional.
2689	if (!ParseRegRange(RegNum, RegWidth))	2689	if (!ParseRegRange(RegNum, RegWidth))
2690	return AMDGPU::NoRegister;	2690	return AMDGPU::NoRegister;
2691	}	2691	}
2692		2692
2693	return getRegularReg(RegKind, RegNum, RegWidth, Loc);	2693	return getRegularReg(RegKind, RegNum, RegWidth, Loc);
2694	}	2694	}
2695		2695
2696	unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	2696	unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,
2697	unsigned &RegWidth,	2697	unsigned &RegWidth,
2698	SmallVectorImpl &Tokens) {	2698	SmallVectorImpl &Tokens) {
2699	unsigned Reg = AMDGPU::NoRegister;	2699	unsigned Reg = AMDGPU::NoRegister;
2700	auto ListLoc = getLoc();	2700	auto ListLoc = getLoc();
2701		2701
2702	if (!skipToken(AsmToken::LBrac,	2702	if (!skipToken(AsmToken::LBrac,
2703	"expected a register or a list of registers")) {	2703	"expected a register or a list of registers")) {
2704	return AMDGPU::NoRegister;	2704	return AMDGPU::NoRegister;
2705	}	2705	}
2706		2706
2707	// List of consecutive registers, e.g.: [s0,s1,s2,s3]	2707	// List of consecutive registers, e.g.: [s0,s1,s2,s3]
2708		2708
2709	auto Loc = getLoc();	2709	auto Loc = getLoc();
2710	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))	2710	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))
2711	return AMDGPU::NoRegister;	2711	return AMDGPU::NoRegister;
2712	if (RegWidth != 32) {	2712	if (RegWidth != 32) {
2713	Error(Loc, "expected a single 32-bit register");	2713	Error(Loc, "expected a single 32-bit register");
2714	return AMDGPU::NoRegister;	2714	return AMDGPU::NoRegister;
2715	}	2715	}
2716		2716
2717	for (; trySkipToken(AsmToken::Comma); ) {	2717	for (; trySkipToken(AsmToken::Comma); ) {
2718	RegisterKind NextRegKind;	2718	RegisterKind NextRegKind;
2719	unsigned NextReg, NextRegNum, NextRegWidth;	2719	unsigned NextReg, NextRegNum, NextRegWidth;
2720	Loc = getLoc();	2720	Loc = getLoc();
2721		2721
2722	if (!ParseAMDGPURegister(NextRegKind, NextReg,	2722	if (!ParseAMDGPURegister(NextRegKind, NextReg,
2723	NextRegNum, NextRegWidth,	2723	NextRegNum, NextRegWidth,
2724	Tokens)) {	2724	Tokens)) {
2725	return AMDGPU::NoRegister;	2725	return AMDGPU::NoRegister;
2726	}	2726	}
2727	if (NextRegWidth != 32) {	2727	if (NextRegWidth != 32) {
2728	Error(Loc, "expected a single 32-bit register");	2728	Error(Loc, "expected a single 32-bit register");
2729	return AMDGPU::NoRegister;	2729	return AMDGPU::NoRegister;
2730	}	2730	}
2731	if (NextRegKind != RegKind) {	2731	if (NextRegKind != RegKind) {
2732	Error(Loc, "registers in a list must be of the same kind");	2732	Error(Loc, "registers in a list must be of the same kind");
2733	return AMDGPU::NoRegister;	2733	return AMDGPU::NoRegister;
2734	}	2734	}
2735	if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))	2735	if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))
2736	return AMDGPU::NoRegister;	2736	return AMDGPU::NoRegister;
2737	}	2737	}
2738		2738
2739	if (!skipToken(AsmToken::RBrac,	2739	if (!skipToken(AsmToken::RBrac,
2740	"expected a comma or a closing square bracket")) {	2740	"expected a comma or a closing square bracket")) {
2741	return AMDGPU::NoRegister;	2741	return AMDGPU::NoRegister;
2742	}	2742	}
2743		2743
2744	if (isRegularReg(RegKind))	2744	if (isRegularReg(RegKind))
2745	Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);	2745	Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);
2746		2746
2747	return Reg;	2747	return Reg;
2748	}	2748	}
2749		2749
2750	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	2750	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
2751	unsigned &RegNum, unsigned &RegWidth,	2751	unsigned &RegNum, unsigned &RegWidth,
2752	SmallVectorImpl &Tokens) {	2752	SmallVectorImpl &Tokens) {
2753	auto Loc = getLoc();	2753	auto Loc = getLoc();
2754	Reg = AMDGPU::NoRegister;	2754	Reg = AMDGPU::NoRegister;
2755		2755
2756	if (isToken(AsmToken::Identifier)) {	2756	if (isToken(AsmToken::Identifier)) {
2757	Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);	2757	Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);
2758	if (Reg == AMDGPU::NoRegister)	2758	if (Reg == AMDGPU::NoRegister)
2759	Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);	2759	Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);
2760	} else {	2760	} else {
2761	Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);	2761	Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);
2762	}	2762	}
2763		2763
2764	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	2764	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
2765	if (Reg == AMDGPU::NoRegister) {	2765	if (Reg == AMDGPU::NoRegister) {
2766	assert(Parser.hasPendingError());	2766	assert(Parser.hasPendingError());
2767	return false;	2767	return false;
2768	}	2768	}
2769		2769
2770	if (!subtargetHasRegister(*TRI, Reg)) {	2770	if (!subtargetHasRegister(*TRI, Reg)) {
2771	if (Reg == AMDGPU::SGPR_NULL) {	2771	if (Reg == AMDGPU::SGPR_NULL) {
2772	Error(Loc, "'null' operand is not supported on this GPU");	2772	Error(Loc, "'null' operand is not supported on this GPU");
2773	} else {	2773	} else {
2774	Error(Loc, "register not available on this GPU");	2774	Error(Loc, "register not available on this GPU");
2775	}	2775	}
2776	return false;	2776	return false;
2777	}	2777	}
2778		2778
2779	return true;	2779	return true;
2780	}	2780	}
2781		2781
2782	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	2782	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,
2783	unsigned &RegNum, unsigned &RegWidth,	2783	unsigned &RegNum, unsigned &RegWidth,
2784	bool RestoreOnFailure /=false/) {	2784	bool RestoreOnFailure /=false/) {
2785	Reg = AMDGPU::NoRegister;	2785	Reg = AMDGPU::NoRegister;
2786		2786
2787	SmallVector Tokens;	2787	SmallVector Tokens;
2788	if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {	2788	if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {
2789	if (RestoreOnFailure) {	2789	if (RestoreOnFailure) {
2790	while (!Tokens.empty()) {	2790	while (!Tokens.empty()) {
2791	getLexer().UnLex(Tokens.pop_back_val());	2791	getLexer().UnLex(Tokens.pop_back_val());
2792	}	2792	}
2793	}	2793	}
2794	return true;	2794	return true;
2795	}	2795	}
2796	return false;	2796	return false;
2797	}	2797	}
2798		2798
2799	std::optional	2799	std::optional
2800	AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {	2800	AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {
2801	switch (RegKind) {	2801	switch (RegKind) {
2802	case IS_VGPR:	2802	case IS_VGPR:
2803	return StringRef(".amdgcn.next_free_vgpr");	2803	return StringRef(".amdgcn.next_free_vgpr");
2804	case IS_SGPR:	2804	case IS_SGPR:
2805	return StringRef(".amdgcn.next_free_sgpr");	2805	return StringRef(".amdgcn.next_free_sgpr");
2806	default:	2806	default:
2807	return std::nullopt;	2807	return std::nullopt;
2808	}	2808	}
2809	}	2809	}
2810		2810
2811	void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {	2811	void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {
2812	auto SymbolName = getGprCountSymbolName(RegKind);	2812	auto SymbolName = getGprCountSymbolName(RegKind);
2813	assert(SymbolName && "initializing invalid register kind");	2813	assert(SymbolName && "initializing invalid register kind");
2814	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	2814	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);
2815	Sym->setVariableValue(MCConstantExpr::create(0, getContext()));	2815	Sym->setVariableValue(MCConstantExpr::create(0, getContext()));
2816	}	2816	}
2817		2817
2818	bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,	2818	bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,
2819	unsigned DwordRegIndex,	2819	unsigned DwordRegIndex,
2820	unsigned RegWidth) {	2820	unsigned RegWidth) {
2821	// Symbols are only defined for GCN targets	2821	// Symbols are only defined for GCN targets
2822	if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)	2822	if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)
2823	return true;	2823	return true;
2824		2824
2825	auto SymbolName = getGprCountSymbolName(RegKind);	2825	auto SymbolName = getGprCountSymbolName(RegKind);
2826	if (!SymbolName)	2826	if (!SymbolName)
2827	return true;	2827	return true;
2828	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	2828	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);
2829		2829
2830	int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;	2830	int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;
2831	int64_t OldCount;	2831	int64_t OldCount;
2832		2832
2833	if (!Sym->isVariable())	2833	if (!Sym->isVariable())
2834	return !Error(getLoc(),	2834	return !Error(getLoc(),
2835	".amdgcn.next_free_{v,s}gpr symbols must be variable");	2835	".amdgcn.next_free_{v,s}gpr symbols must be variable");
2836	if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))	2836	if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))
2837	return !Error(	2837	return !Error(
2838	getLoc(),	2838	getLoc(),
2839	".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");	2839	".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");
2840		2840
2841	if (OldCount <= NewMax)	2841	if (OldCount <= NewMax)
2842	Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));	2842	Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));
2843		2843
2844	return true;	2844	return true;
2845	}	2845	}
2846		2846
2847	std::unique_ptr	2847	std::unique_ptr
2848	AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {	2848	AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {
2849	const auto &Tok = getToken();	2849	const auto &Tok = getToken();
2850	SMLoc StartLoc = Tok.getLoc();	2850	SMLoc StartLoc = Tok.getLoc();
2851	SMLoc EndLoc = Tok.getEndLoc();	2851	SMLoc EndLoc = Tok.getEndLoc();
2852	RegisterKind RegKind;	2852	RegisterKind RegKind;
2853	unsigned Reg, RegNum, RegWidth;	2853	unsigned Reg, RegNum, RegWidth;
2854		2854
2855	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {	2855	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {
2856	return nullptr;	2856	return nullptr;
2857	}	2857	}
2858	if (isHsaAbiVersion3AndAbove(&getSTI())) {	2858	if (isHsaAbiVersion3AndAbove(&getSTI())) {
2859	if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))	2859	if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))
2860	return nullptr;	2860	return nullptr;
2861	} else	2861	} else
2862	KernelScope.usesRegister(RegKind, RegNum, RegWidth);	2862	KernelScope.usesRegister(RegKind, RegNum, RegWidth);
2863	return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);	2863	return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);
2864	}	2864	}
2865		2865
2866	ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,	2866	ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,
2867	bool HasSP3AbsModifier) {	2867	bool HasSP3AbsModifier) {
2868	// TODO: add syntactic sugar for 1/(2*PI)	2868	// TODO: add syntactic sugar for 1/(2*PI)
2869		2869
2870	if (isRegister())	2870	if (isRegister())
2871	return ParseStatus::NoMatch;	2871	return ParseStatus::NoMatch;
2872	assert(!isModifier());	2872	assert(!isModifier());
2873		2873
2874	const auto& Tok = getToken();	2874	const auto& Tok = getToken();
2875	const auto& NextTok = peekToken();	2875	const auto& NextTok = peekToken();
2876	bool IsReal = Tok.is(AsmToken::Real);	2876	bool IsReal = Tok.is(AsmToken::Real);
2877	SMLoc S = getLoc();	2877	SMLoc S = getLoc();
2878	bool Negate = false;	2878	bool Negate = false;
2879		2879
2880	if (!IsReal && Tok.is(AsmToken::Minus) && NextTok.is(AsmToken::Real)) {	2880	if (!IsReal && Tok.is(AsmToken::Minus) && NextTok.is(AsmToken::Real)) {
2881	lex();	2881	lex();
2882	IsReal = true;	2882	IsReal = true;
2883	Negate = true;	2883	Negate = true;
2884	}	2884	}
2885		2885
2886	if (IsReal) {	2886	if (IsReal) {
2887	// Floating-point expressions are not supported.	2887	// Floating-point expressions are not supported.
2888	// Can only allow floating-point literals with an	2888	// Can only allow floating-point literals with an
2889	// optional sign.	2889	// optional sign.
2890		2890
2891	StringRef Num = getTokenStr();	2891	StringRef Num = getTokenStr();
2892	lex();	2892	lex();
2893		2893
2894	APFloat RealVal(APFloat::IEEEdouble());	2894	APFloat RealVal(APFloat::IEEEdouble());
2895	auto roundMode = APFloat::rmNearestTiesToEven;	2895	auto roundMode = APFloat::rmNearestTiesToEven;
2896	if (errorToBool(RealVal.convertFromString(Num, roundMode).takeError()))	2896	if (errorToBool(RealVal.convertFromString(Num, roundMode).takeError()))
2897	return ParseStatus::Failure;	2897	return ParseStatus::Failure;
2898	if (Negate)	2898	if (Negate)
2899	RealVal.changeSign();	2899	RealVal.changeSign();
2900		2900
2901	Operands.push_back(	2901	Operands.push_back(
2902	AMDGPUOperand::CreateImm(this, RealVal.bitcastToAPInt().getZExtValue(), S,	2902	AMDGPUOperand::CreateImm(this, RealVal.bitcastToAPInt().getZExtValue(), S,
2903	AMDGPUOperand::ImmTyNone, true));	2903	AMDGPUOperand::ImmTyNone, true));
2904		2904
2905	return ParseStatus::Success;	2905	return ParseStatus::Success;
2906		2906
2907	} else {	2907	} else {
2908	int64_t IntVal;	2908	int64_t IntVal;
2909	const MCExpr *Expr;	2909	const MCExpr *Expr;
2910	SMLoc S = getLoc();	2910	SMLoc S = getLoc();
2911		2911
2912	if (HasSP3AbsModifier) {	2912	if (HasSP3AbsModifier) {
2913	// This is a workaround for handling expressions	2913	// This is a workaround for handling expressions
2914	// as arguments of SP3 'abs' modifier, for example:	2914	// as arguments of SP3 'abs' modifier, for example:
2915	// \|1.0\|	2915	// \|1.0\|
2916	// \|-1\|	2916	// \|-1\|
2917	// \|1+x\|	2917	// \|1+x\|
2918	// This syntax is not compatible with syntax of standard	2918	// This syntax is not compatible with syntax of standard
2919	// MC expressions (due to the trailing '\|').	2919	// MC expressions (due to the trailing '\|').
2920	SMLoc EndLoc;	2920	SMLoc EndLoc;
2921	if (getParser().parsePrimaryExpr(Expr, EndLoc, nullptr))	2921	if (getParser().parsePrimaryExpr(Expr, EndLoc, nullptr))
2922	return ParseStatus::Failure;	2922	return ParseStatus::Failure;
2923	} else {	2923	} else {
2924	if (Parser.parseExpression(Expr))	2924	if (Parser.parseExpression(Expr))
2925	return ParseStatus::Failure;	2925	return ParseStatus::Failure;
2926	}	2926	}
2927		2927
2928	if (Expr->evaluateAsAbsolute(IntVal)) {	2928	if (Expr->evaluateAsAbsolute(IntVal)) {
2929	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	2929	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
2930	} else {	2930	} else {
2931	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	2931	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
2932	}	2932	}
2933		2933
2934	return ParseStatus::Success;	2934	return ParseStatus::Success;
2935	}	2935	}
2936		2936
2937	return ParseStatus::NoMatch;	2937	return ParseStatus::NoMatch;
2938	}	2938	}
2939		2939
2940	ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {	2940	ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {
2941	if (!isRegister())	2941	if (!isRegister())
2942	return ParseStatus::NoMatch;	2942	return ParseStatus::NoMatch;
2943		2943
2944	if (auto R = parseRegister()) {	2944	if (auto R = parseRegister()) {
2945	assert(R->isReg());	2945	assert(R->isReg());
2946	Operands.push_back(std::move(R));	2946	Operands.push_back(std::move(R));
2947	return ParseStatus::Success;	2947	return ParseStatus::Success;
2948	}	2948	}
2949	return ParseStatus::Failure;	2949	return ParseStatus::Failure;
2950	}	2950	}
2951		2951
2952	ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,	2952	ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,
2953	bool HasSP3AbsMod) {	2953	bool HasSP3AbsMod) {
2954	ParseStatus Res = parseReg(Operands);	2954	ParseStatus Res = parseReg(Operands);
2955	if (!Res.isNoMatch())	2955	if (!Res.isNoMatch())
2956	return Res;	2956	return Res;
2957	if (isModifier())	2957	if (isModifier())
2958	return ParseStatus::NoMatch;	2958	return ParseStatus::NoMatch;
2959	return parseImm(Operands, HasSP3AbsMod);	2959	return parseImm(Operands, HasSP3AbsMod);
2960	}	2960	}
2961		2961
2962	bool	2962	bool
2963	AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	2963	AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
2964	if (Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::LParen)) {	2964	if (Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::LParen)) {
2965	const auto &str = Token.getString();	2965	const auto &str = Token.getString();
2966	return str == "abs" \|\| str == "neg" \|\| str == "sext";	2966	return str == "abs" \|\| str == "neg" \|\| str == "sext";
2967	}	2967	}
2968	return false;	2968	return false;
2969	}	2969	}
2970		2970
2971	bool	2971	bool
2972	AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {	2972	AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {
2973	return Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::Colon);	2973	return Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::Colon);
2974	}	2974	}
2975		2975
2976	bool	2976	bool
2977	AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	2977	AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
2978	return isNamedOperandModifier(Token, NextToken) \|\| Token.is(AsmToken::Pipe);	2978	return isNamedOperandModifier(Token, NextToken) \|\| Token.is(AsmToken::Pipe);
2979	}	2979	}
2980		2980
2981	bool	2981	bool
2982	AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	2982	AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {
2983	return isRegister(Token, NextToken) \|\| isOperandModifier(Token, NextToken);	2983	return isRegister(Token, NextToken) \|\| isOperandModifier(Token, NextToken);
2984	}	2984	}
2985		2985
2986	// Check if this is an operand modifier or an opcode modifier	2986	// Check if this is an operand modifier or an opcode modifier
2987	// which may look like an expression but it is not. We should	2987	// which may look like an expression but it is not. We should
2988	// avoid parsing these modifiers as expressions. Currently	2988	// avoid parsing these modifiers as expressions. Currently
2989	// recognized sequences are:	2989	// recognized sequences are:
2990	// \|...\|	2990	// \|...\|
2991	// abs(...)	2991	// abs(...)
2992	// neg(...)	2992	// neg(...)
2993	// sext(...)	2993	// sext(...)
2994	// -reg	2994	// -reg
2995	// -\|...\|	2995	// -\|...\|
2996	// -abs(...)	2996	// -abs(...)
2997	// name:...	2997	// name:...
2998	//	2998	//
2999	bool	2999	bool
3000	AMDGPUAsmParser::isModifier() {	3000	AMDGPUAsmParser::isModifier() {
3001		3001
3002	AsmToken Tok = getToken();	3002	AsmToken Tok = getToken();
3003	AsmToken NextToken[2];	3003	AsmToken NextToken[2];
3004	peekTokens(NextToken);	3004	peekTokens(NextToken);
3005		3005
3006	return isOperandModifier(Tok, NextToken[0]) \|\|	3006	return isOperandModifier(Tok, NextToken[0]) \|\|
3007	(Tok.is(AsmToken::Minus) && isRegOrOperandModifier(NextToken[0], NextToken[1])) \|\|	3007	(Tok.is(AsmToken::Minus) && isRegOrOperandModifier(NextToken[0], NextToken[1])) \|\|
3008	isOpcodeModifierWithVal(Tok, NextToken[0]);	3008	isOpcodeModifierWithVal(Tok, NextToken[0]);
3009	}	3009	}
3010		3010
3011	// Check if the current token is an SP3 'neg' modifier.	3011	// Check if the current token is an SP3 'neg' modifier.
3012	// Currently this modifier is allowed in the following context:	3012	// Currently this modifier is allowed in the following context:
3013	//	3013	//
3014	// 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".	3014	// 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".
3015	// 2. Before an 'abs' modifier: -abs(...)	3015	// 2. Before an 'abs' modifier: -abs(...)
3016	// 3. Before an SP3 'abs' modifier: -\|...\|	3016	// 3. Before an SP3 'abs' modifier: -\|...\|
3017	//	3017	//
3018	// In all other cases "-" is handled as a part	3018	// In all other cases "-" is handled as a part
3019	// of an expression that follows the sign.	3019	// of an expression that follows the sign.
3020	//	3020	//
3021	// Note: When "-" is followed by an integer literal,	3021	// Note: When "-" is followed by an integer literal,
3022	// this is interpreted as integer negation rather	3022	// this is interpreted as integer negation rather
3023	// than a floating-point NEG modifier applied to N.	3023	// than a floating-point NEG modifier applied to N.
3024	// Beside being contr-intuitive, such use of floating-point	3024	// Beside being contr-intuitive, such use of floating-point
3025	// NEG modifier would have resulted in different meaning	3025	// NEG modifier would have resulted in different meaning
3026	// of integer literals used with VOP1/2/C and VOP3,	3026	// of integer literals used with VOP1/2/C and VOP3,
3027	// for example:	3027	// for example:
3028	// v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF	3028	// v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF
3029	// v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001	3029	// v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001
3030	// Negative fp literals with preceding "-" are	3030	// Negative fp literals with preceding "-" are
3031	// handled likewise for uniformity	3031	// handled likewise for uniformity
3032	//	3032	//
3033	bool	3033	bool
3034	AMDGPUAsmParser::parseSP3NegModifier() {	3034	AMDGPUAsmParser::parseSP3NegModifier() {
3035		3035
3036	AsmToken NextToken[2];	3036	AsmToken NextToken[2];
3037	peekTokens(NextToken);	3037	peekTokens(NextToken);
3038		3038
3039	if (isToken(AsmToken::Minus) &&	3039	if (isToken(AsmToken::Minus) &&
3040	(isRegister(NextToken[0], NextToken[1]) \|\|	3040	(isRegister(NextToken[0], NextToken[1]) \|\|
3041	NextToken[0].is(AsmToken::Pipe) \|\|	3041	NextToken[0].is(AsmToken::Pipe) \|\|
3042	isId(NextToken[0], "abs"))) {	3042	isId(NextToken[0], "abs"))) {
3043	lex();	3043	lex();
3044	return true;	3044	return true;
3045	}	3045	}
3046		3046
3047	return false;	3047	return false;
3048	}	3048	}
3049		3049
3050	ParseStatus	3050	ParseStatus
3051	AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,	3051	AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,
3052	bool AllowImm) {	3052	bool AllowImm) {
3053	bool Neg, SP3Neg;	3053	bool Neg, SP3Neg;
3054	bool Abs, SP3Abs;	3054	bool Abs, SP3Abs;
3055	SMLoc Loc;	3055	SMLoc Loc;
3056		3056
3057	// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.	3057	// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.
3058	if (isToken(AsmToken::Minus) && peekToken().is(AsmToken::Minus))	3058	if (isToken(AsmToken::Minus) && peekToken().is(AsmToken::Minus))
3059	return Error(getLoc(), "invalid syntax, expected 'neg' modifier");	3059	return Error(getLoc(), "invalid syntax, expected 'neg' modifier");
3060		3060
3061	SP3Neg = parseSP3NegModifier();	3061	SP3Neg = parseSP3NegModifier();
3062		3062
3063	Loc = getLoc();	3063	Loc = getLoc();
3064	Neg = trySkipId("neg");	3064	Neg = trySkipId("neg");
3065	if (Neg && SP3Neg)	3065	if (Neg && SP3Neg)
3066	return Error(Loc, "expected register or immediate");	3066	return Error(Loc, "expected register or immediate");
3067	if (Neg && !skipToken(AsmToken::LParen, "expected left paren after neg"))	3067	if (Neg && !skipToken(AsmToken::LParen, "expected left paren after neg"))
3068	return ParseStatus::Failure;	3068	return ParseStatus::Failure;
3069		3069
3070	Abs = trySkipId("abs");	3070	Abs = trySkipId("abs");
3071	if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))	3071	if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))
3072	return ParseStatus::Failure;	3072	return ParseStatus::Failure;
3073		3073
3074	Loc = getLoc();	3074	Loc = getLoc();
3075	SP3Abs = trySkipToken(AsmToken::Pipe);	3075	SP3Abs = trySkipToken(AsmToken::Pipe);
3076	if (Abs && SP3Abs)	3076	if (Abs && SP3Abs)
3077	return Error(Loc, "expected register or immediate");	3077	return Error(Loc, "expected register or immediate");
3078		3078
3079	ParseStatus Res;	3079	ParseStatus Res;
3080	if (AllowImm) {	3080	if (AllowImm) {
3081	Res = parseRegOrImm(Operands, SP3Abs);	3081	Res = parseRegOrImm(Operands, SP3Abs);
3082	} else {	3082	} else {
3083	Res = parseReg(Operands);	3083	Res = parseReg(Operands);
3084	}	3084	}
3085	if (!Res.isSuccess())	3085	if (!Res.isSuccess())
3086	return (SP3Neg \|\| Neg \|\| SP3Abs \|\| Abs) ? ParseStatus::Failure : Res;	3086	return (SP3Neg \|\| Neg \|\| SP3Abs \|\| Abs) ? ParseStatus::Failure : Res;
3087		3087
3088	if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))	3088	if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))
3089	return ParseStatus::Failure;	3089	return ParseStatus::Failure;
3090	if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))	3090	if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))
3091	return ParseStatus::Failure;	3091	return ParseStatus::Failure;
3092	if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))	3092	if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))
3093	return ParseStatus::Failure;	3093	return ParseStatus::Failure;
3094		3094
3095	AMDGPUOperand::Modifiers Mods;	3095	AMDGPUOperand::Modifiers Mods;
3096	Mods.Abs = Abs \|\| SP3Abs;	3096	Mods.Abs = Abs \|\| SP3Abs;
3097	Mods.Neg = Neg \|\| SP3Neg;	3097	Mods.Neg = Neg \|\| SP3Neg;
3098		3098
3099	if (Mods.hasFPModifiers()) {	3099	if (Mods.hasFPModifiers()) {
3100	AMDGPUOperand &Op = static_cast(*Operands.back());	3100	AMDGPUOperand &Op = static_cast(*Operands.back());
3101	if (Op.isExpr())	3101	if (Op.isExpr())
3102	return Error(Op.getStartLoc(), "expected an absolute expression");	3102	return Error(Op.getStartLoc(), "expected an absolute expression");
3103	Op.setModifiers(Mods);	3103	Op.setModifiers(Mods);
3104	}	3104	}
3105	return ParseStatus::Success;	3105	return ParseStatus::Success;
3106	}	3106	}
3107		3107
3108	ParseStatus	3108	ParseStatus
3109	AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,	3109	AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,
3110	bool AllowImm) {	3110	bool AllowImm) {
3111	bool Sext = trySkipId("sext");	3111	bool Sext = trySkipId("sext");
3112	if (Sext && !skipToken(AsmToken::LParen, "expected left paren after sext"))	3112	if (Sext && !skipToken(AsmToken::LParen, "expected left paren after sext"))
3113	return ParseStatus::Failure;	3113	return ParseStatus::Failure;
3114		3114
3115	ParseStatus Res;	3115	ParseStatus Res;
3116	if (AllowImm) {	3116	if (AllowImm) {
3117	Res = parseRegOrImm(Operands);	3117	Res = parseRegOrImm(Operands);
3118	} else {	3118	} else {
3119	Res = parseReg(Operands);	3119	Res = parseReg(Operands);
3120	}	3120	}
3121	if (!Res.isSuccess())	3121	if (!Res.isSuccess())
3122	return Sext ? ParseStatus::Failure : Res;	3122	return Sext ? ParseStatus::Failure : Res;
3123		3123
3124	if (Sext && !skipToken(AsmToken::RParen, "expected closing parentheses"))	3124	if (Sext && !skipToken(AsmToken::RParen, "expected closing parentheses"))
3125	return ParseStatus::Failure;	3125	return ParseStatus::Failure;
3126		3126
3127	AMDGPUOperand::Modifiers Mods;	3127	AMDGPUOperand::Modifiers Mods;
3128	Mods.Sext = Sext;	3128	Mods.Sext = Sext;
3129		3129
3130	if (Mods.hasIntModifiers()) {	3130	if (Mods.hasIntModifiers()) {
3131	AMDGPUOperand &Op = static_cast(*Operands.back());	3131	AMDGPUOperand &Op = static_cast(*Operands.back());
3132	if (Op.isExpr())	3132	if (Op.isExpr())
3133	return Error(Op.getStartLoc(), "expected an absolute expression");	3133	return Error(Op.getStartLoc(), "expected an absolute expression");
3134	Op.setModifiers(Mods);	3134	Op.setModifiers(Mods);
3135	}	3135	}
3136		3136
3137	return ParseStatus::Success;	3137	return ParseStatus::Success;
3138	}	3138	}
3139		3139
3140	ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {	3140	ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {
3141	return parseRegOrImmWithFPInputMods(Operands, false);	3141	return parseRegOrImmWithFPInputMods(Operands, false);
3142	}	3142	}
3143		3143
3144	ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {	3144	ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {
3145	return parseRegOrImmWithIntInputMods(Operands, false);	3145	return parseRegOrImmWithIntInputMods(Operands, false);
3146	}	3146	}
3147		3147
3148	ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {	3148	ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {
3149	auto Loc = getLoc();	3149	auto Loc = getLoc();
3150	if (trySkipId("off")) {	3150	if (trySkipId("off")) {
3151	Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,	3151	Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,
3152	AMDGPUOperand::ImmTyOff, false));	3152	AMDGPUOperand::ImmTyOff, false));
3153	return ParseStatus::Success;	3153	return ParseStatus::Success;
3154	}	3154	}
3155		3155
3156	if (!isRegister())	3156	if (!isRegister())
3157	return ParseStatus::NoMatch;	3157	return ParseStatus::NoMatch;
3158		3158
3159	std::unique_ptr Reg = parseRegister();	3159	std::unique_ptr Reg = parseRegister();
3160	if (Reg) {	3160	if (Reg) {
3161	Operands.push_back(std::move(Reg));	3161	Operands.push_back(std::move(Reg));
3162	return ParseStatus::Success;	3162	return ParseStatus::Success;
3163	}	3163	}
3164		3164
3165	return ParseStatus::Failure;	3165	return ParseStatus::Failure;
3166	}	3166	}
3167		3167
3168	unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {	3168	unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
3169	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	3169	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
3170		3170
3171	if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) \|\|	3171	if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) \|\|
3172	(getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) \|\|	3172	(getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) \|\|
3173	(isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) \|\|	3173	(isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) \|\|
3174	(isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )	3174	(isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )
3175	return Match_InvalidOperand;	3175	return Match_InvalidOperand;
3176		3176
3177	if ((TSFlags & SIInstrFlags::VOP3) &&	3177	if ((TSFlags & SIInstrFlags::VOP3) &&
3178	(TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&	3178	(TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&
3179	getForcedEncodingSize() != 64)	3179	getForcedEncodingSize() != 64)
3180	return Match_PreferE32;	3180	return Match_PreferE32;
3181		3181
3182	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	3182	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|
3183	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	3183	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
3184	// v_mac_f32/16 allow only dst_sel == DWORD;	3184	// v_mac_f32/16 allow only dst_sel == DWORD;
3185	auto OpNum =	3185	auto OpNum =
3186	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);	3186	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);
3187	const auto &Op = Inst.getOperand(OpNum);	3187	const auto &Op = Inst.getOperand(OpNum);
3188	if (!Op.isImm() \|\| Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {	3188	if (!Op.isImm() \|\| Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {
3189	return Match_InvalidOperand;	3189	return Match_InvalidOperand;
3190	}	3190	}
3191	}	3191	}
3192		3192
3193	return Match_Success;	3193	return Match_Success;
3194	}	3194	}
3195		3195
3196	static ArrayRef getAllVariants() {	3196	static ArrayRef getAllVariants() {
3197	static const unsigned Variants[] = {	3197	static const unsigned Variants[] = {
3198	AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,	3198	AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,
3199	AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9,	3199	AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9,
3200	AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP	3200	AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP
3201	};	3201	};
3202		3202
3203	return ArrayRef(Variants);	3203	return ArrayRef(Variants);
3204	}	3204	}
3205		3205
3206	// What asm variants we should check	3206	// What asm variants we should check
3207	ArrayRef AMDGPUAsmParser::getMatchedVariants() const {	3207	ArrayRef AMDGPUAsmParser::getMatchedVariants() const {
3208	if (isForcedDPP() && isForcedVOP3()) {	3208	if (isForcedDPP() && isForcedVOP3()) {
3209	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3_DPP};	3209	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3_DPP};
3210	return ArrayRef(Variants);	3210	return ArrayRef(Variants);
3211	}	3211	}
3212	if (getForcedEncodingSize() == 32) {	3212	if (getForcedEncodingSize() == 32) {
3213	static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};	3213	static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};
3214	return ArrayRef(Variants);	3214	return ArrayRef(Variants);
3215	}	3215	}
3216		3216
3217	if (isForcedVOP3()) {	3217	if (isForcedVOP3()) {
3218	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};	3218	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};
3219	return ArrayRef(Variants);	3219	return ArrayRef(Variants);
3220	}	3220	}
3221		3221
3222	if (isForcedSDWA()) {	3222	if (isForcedSDWA()) {
3223	static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,	3223	static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,
3224	AMDGPUAsmVariants::SDWA9};	3224	AMDGPUAsmVariants::SDWA9};
3225	return ArrayRef(Variants);	3225	return ArrayRef(Variants);
3226	}	3226	}
3227		3227
3228	if (isForcedDPP()) {	3228	if (isForcedDPP()) {
3229	static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};	3229	static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};
3230	return ArrayRef(Variants);	3230	return ArrayRef(Variants);
3231	}	3231	}
3232		3232
3233	return getAllVariants();	3233	return getAllVariants();
3234	}	3234	}
3235		3235
3236	StringRef AMDGPUAsmParser::getMatchedVariantName() const {	3236	StringRef AMDGPUAsmParser::getMatchedVariantName() const {
3237	if (isForcedDPP() && isForcedVOP3())	3237	if (isForcedDPP() && isForcedVOP3())
3238	return "e64_dpp";	3238	return "e64_dpp";
3239		3239
3240	if (getForcedEncodingSize() == 32)	3240	if (getForcedEncodingSize() == 32)
3241	return "e32";	3241	return "e32";
3242		3242
3243	if (isForcedVOP3())	3243	if (isForcedVOP3())
3244	return "e64";	3244	return "e64";
3245		3245
3246	if (isForcedSDWA())	3246	if (isForcedSDWA())
3247	return "sdwa";	3247	return "sdwa";
3248		3248
3249	if (isForcedDPP())	3249	if (isForcedDPP())
3250	return "dpp";	3250	return "dpp";
3251		3251
3252	return "";	3252	return "";
3253	}	3253	}
3254		3254
3255	unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {	3255	unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {
3256	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	3256	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3257	for (MCPhysReg Reg : Desc.implicit_uses()) {	3257	for (MCPhysReg Reg : Desc.implicit_uses()) {
3258	switch (Reg) {	3258	switch (Reg) {
3259	case AMDGPU::FLAT_SCR:	3259	case AMDGPU::FLAT_SCR:
3260	case AMDGPU::VCC:	3260	case AMDGPU::VCC:
3261	case AMDGPU::VCC_LO:	3261	case AMDGPU::VCC_LO:
3262	case AMDGPU::VCC_HI:	3262	case AMDGPU::VCC_HI:
3263	case AMDGPU::M0:	3263	case AMDGPU::M0:
3264	return Reg;	3264	return Reg;
3265	default:	3265	default:
3266	break;	3266	break;
3267	}	3267	}
3268	}	3268	}
3269	return AMDGPU::NoRegister;	3269	return AMDGPU::NoRegister;
3270	}	3270	}
3271		3271
3272	// NB: This code is correct only when used to check constant	3272	// NB: This code is correct only when used to check constant
3273	// bus limitations because GFX7 support no f16 inline constants.	3273	// bus limitations because GFX7 support no f16 inline constants.
3274	// Note that there are no cases when a GFX7 opcode violates	3274	// Note that there are no cases when a GFX7 opcode violates
3275	// constant bus limitations due to the use of an f16 constant.	3275	// constant bus limitations due to the use of an f16 constant.
3276	bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,	3276	bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,
3277	unsigned OpIdx) const {	3277	unsigned OpIdx) const {
3278	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	3278	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
3279		3279
3280	if (!AMDGPU::isSISrcOperand(Desc, OpIdx) \|\|	3280	if (!AMDGPU::isSISrcOperand(Desc, OpIdx) \|\|
3281	AMDGPU::isKImmOperand(Desc, OpIdx)) {	3281	AMDGPU::isKImmOperand(Desc, OpIdx)) {
3282	return false;	3282	return false;
3283	}	3283	}
3284		3284
3285	const MCOperand &MO = Inst.getOperand(OpIdx);	3285	const MCOperand &MO = Inst.getOperand(OpIdx);
3286		3286
3287	int64_t Val = MO.getImm();	3287	int64_t Val = MO.getImm();
3288	auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);	3288	auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);
3289		3289
3290	switch (OpSize) { // expected operand size	3290	switch (OpSize) { // expected operand size
3291	case 8:	3291	case 8:
3292	return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());	3292	return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());
3293	case 4:	3293	case 4:
3294	return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());	3294	return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());
3295	case 2: {	3295	case 2: {
3296	const unsigned OperandType = Desc.operands()[OpIdx].OperandType;	3296	const unsigned OperandType = Desc.operands()[OpIdx].OperandType;
3297	if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 \|\|	3297	if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 \|\|
3298	OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 \|\|	3298	OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 \|\|
3299	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16)	3299	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16)
3300	return AMDGPU::isInlinableIntLiteral(Val);	3300	return AMDGPU::isInlinableIntLiteral(Val);
3301		3301
3302	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 \|\|	3302	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 \|\|
3303	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 \|\|	3303	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 \|\|
3304	OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16)	3304	OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16)
3305	return AMDGPU::isInlinableIntLiteralV216(Val);	3305	return AMDGPU::isInlinableIntLiteralV216(Val);
3306		3306
3307	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 \|\|	3307	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 \|\|
3308	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 \|\|	3308	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 \|\|
3309	OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)	3309	OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)
3310	return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());	3310	return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());
3311		3311
3312	return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());	3312	return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());
3313	}	3313	}
3314	default:	3314	default:
3315	llvm_unreachable("invalid operand size");	3315	llvm_unreachable("invalid operand size");
3316	}	3316	}
3317	}	3317	}
3318		3318
3319	unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {	3319	unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {
3320	if (!isGFX10Plus())	3320	if (!isGFX10Plus())
3321	return 1;	3321	return 1;
3322		3322
3323	switch (Opcode) {	3323	switch (Opcode) {
3324	// 64-bit shift instructions can use only one scalar value input	3324	// 64-bit shift instructions can use only one scalar value input
3325	case AMDGPU::V_LSHLREV_B64_e64:	3325	case AMDGPU::V_LSHLREV_B64_e64:
3326	case AMDGPU::V_LSHLREV_B64_gfx10:	3326	case AMDGPU::V_LSHLREV_B64_gfx10:
3327	case AMDGPU::V_LSHLREV_B64_e64_gfx11:	3327	case AMDGPU::V_LSHLREV_B64_e64_gfx11:
3328	case AMDGPU::V_LSHRREV_B64_e64:	3328	case AMDGPU::V_LSHRREV_B64_e64:
3329	case AMDGPU::V_LSHRREV_B64_gfx10:	3329	case AMDGPU::V_LSHRREV_B64_gfx10:
3330	case AMDGPU::V_LSHRREV_B64_e64_gfx11:	3330	case AMDGPU::V_LSHRREV_B64_e64_gfx11:
3331	case AMDGPU::V_ASHRREV_I64_e64:	3331	case AMDGPU::V_ASHRREV_I64_e64:
3332	case AMDGPU::V_ASHRREV_I64_gfx10:	3332	case AMDGPU::V_ASHRREV_I64_gfx10:
3333	case AMDGPU::V_ASHRREV_I64_e64_gfx11:	3333	case AMDGPU::V_ASHRREV_I64_e64_gfx11:
3334	case AMDGPU::V_LSHL_B64_e64:	3334	case AMDGPU::V_LSHL_B64_e64:
3335	case AMDGPU::V_LSHR_B64_e64:	3335	case AMDGPU::V_LSHR_B64_e64:
3336	case AMDGPU::V_ASHR_I64_e64:	3336	case AMDGPU::V_ASHR_I64_e64:
3337	return 1;	3337	return 1;
3338	default:	3338	default:
3339	return 2;	3339	return 2;
3340	}	3340	}
3341	}	3341	}
3342		3342
3343	constexpr unsigned MAX_SRC_OPERANDS_NUM = 6;	3343	constexpr unsigned MAX_SRC_OPERANDS_NUM = 6;
3344	using OperandIndices = SmallVector;	3344	using OperandIndices = SmallVector;
3345		3345
3346	// Get regular operand indices in the same order as specified	3346	// Get regular operand indices in the same order as specified
3347	// in the instruction (but append mandatory literals to the end).	3347	// in the instruction (but append mandatory literals to the end).
3348	static OperandIndices getSrcOperandIndices(unsigned Opcode,	3348	static OperandIndices getSrcOperandIndices(unsigned Opcode,
3349	bool AddMandatoryLiterals = false) {	3349	bool AddMandatoryLiterals = false) {
3350		3350
3351	int16_t ImmIdx =	3351	int16_t ImmIdx =
3352	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;	3352	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;
3353		3353
3354	if (isVOPD(Opcode)) {	3354	if (isVOPD(Opcode)) {
3355	int16_t ImmDeferredIdx =	3355	int16_t ImmDeferredIdx =
3356	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred)	3356	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred)
3357	: -1;	3357	: -1;
3358		3358
3359	return {getNamedOperandIdx(Opcode, OpName::src0X),	3359	return {getNamedOperandIdx(Opcode, OpName::src0X),
3360	getNamedOperandIdx(Opcode, OpName::vsrc1X),	3360	getNamedOperandIdx(Opcode, OpName::vsrc1X),
3361	getNamedOperandIdx(Opcode, OpName::src0Y),	3361	getNamedOperandIdx(Opcode, OpName::src0Y),
3362	getNamedOperandIdx(Opcode, OpName::vsrc1Y),	3362	getNamedOperandIdx(Opcode, OpName::vsrc1Y),
3363	ImmDeferredIdx,	3363	ImmDeferredIdx,
3364	ImmIdx};	3364	ImmIdx};
3365	}	3365	}
3366		3366
3367	return {getNamedOperandIdx(Opcode, OpName::src0),	3367	return {getNamedOperandIdx(Opcode, OpName::src0),
3368	getNamedOperandIdx(Opcode, OpName::src1),	3368	getNamedOperandIdx(Opcode, OpName::src1),
3369	getNamedOperandIdx(Opcode, OpName::src2), ImmIdx};	3369	getNamedOperandIdx(Opcode, OpName::src2), ImmIdx};
3370	}	3370	}
3371		3371
3372	bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {	3372	bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
3373	const MCOperand &MO = Inst.getOperand(OpIdx);	3373	const MCOperand &MO = Inst.getOperand(OpIdx);
3374	if (MO.isImm()) {	3374	if (MO.isImm()) {
3375	return !isInlineConstant(Inst, OpIdx);	3375	return !isInlineConstant(Inst, OpIdx);
3376	} else if (MO.isReg()) {	3376	} else if (MO.isReg()) {
3377	auto Reg = MO.getReg();	3377	auto Reg = MO.getReg();
3378	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	3378	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
3379	auto PReg = mc2PseudoReg(Reg);	3379	auto PReg = mc2PseudoReg(Reg);
3380	return isSGPR(PReg, TRI) && PReg != SGPR_NULL;	3380	return isSGPR(PReg, TRI) && PReg != SGPR_NULL;
3381	} else {	3381	} else {
3382	return true;	3382	return true;
3383	}	3383	}
3384	}	3384	}
3385		3385
3386	bool AMDGPUAsmParser::validateConstantBusLimitations(	3386	bool AMDGPUAsmParser::validateConstantBusLimitations(
3387	const MCInst &Inst, const OperandVector &Operands) {	3387	const MCInst &Inst, const OperandVector &Operands) {
3388	const unsigned Opcode = Inst.getOpcode();	3388	const unsigned Opcode = Inst.getOpcode();
3389	const MCInstrDesc &Desc = MII.get(Opcode);	3389	const MCInstrDesc &Desc = MII.get(Opcode);
3390	unsigned LastSGPR = AMDGPU::NoRegister;	3390	unsigned LastSGPR = AMDGPU::NoRegister;
3391	unsigned ConstantBusUseCount = 0;	3391	unsigned ConstantBusUseCount = 0;
3392	unsigned NumLiterals = 0;	3392	unsigned NumLiterals = 0;
3393	unsigned LiteralSize;	3393	unsigned LiteralSize;
3394		3394
3395	if (!(Desc.TSFlags &	3395	if (!(Desc.TSFlags &
3396	(SIInstrFlags::VOPC \| SIInstrFlags::VOP1 \| SIInstrFlags::VOP2 \|	3396	(SIInstrFlags::VOPC \| SIInstrFlags::VOP1 \| SIInstrFlags::VOP2 \|
3397	SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P \| SIInstrFlags::SDWA)) &&	3397	SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P \| SIInstrFlags::SDWA)) &&
3398	!isVOPD(Opcode))	3398	!isVOPD(Opcode))
3399	return true;	3399	return true;
3400		3400
3401	// Check special imm operands (used by madmk, etc)	3401	// Check special imm operands (used by madmk, etc)
3402	if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {	3402	if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {
3403	++NumLiterals;	3403	++NumLiterals;
3404	LiteralSize = 4;	3404	LiteralSize = 4;
3405	}	3405	}
3406		3406
3407	SmallDenseSet SGPRsUsed;	3407	SmallDenseSet SGPRsUsed;
3408	unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);	3408	unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);
3409	if (SGPRUsed != AMDGPU::NoRegister) {	3409	if (SGPRUsed != AMDGPU::NoRegister) {
3410	SGPRsUsed.insert(SGPRUsed);	3410	SGPRsUsed.insert(SGPRUsed);
3411	++ConstantBusUseCount;	3411	++ConstantBusUseCount;
3412	}	3412	}
3413		3413
3414	OperandIndices OpIndices = getSrcOperandIndices(Opcode);	3414	OperandIndices OpIndices = getSrcOperandIndices(Opcode);
3415		3415
3416	for (int OpIdx : OpIndices) {	3416	for (int OpIdx : OpIndices) {
3417	if (OpIdx == -1)	3417	if (OpIdx == -1)
3418	continue;	3418	continue;
3419		3419
3420	const MCOperand &MO = Inst.getOperand(OpIdx);	3420	const MCOperand &MO = Inst.getOperand(OpIdx);
3421	if (usesConstantBus(Inst, OpIdx)) {	3421	if (usesConstantBus(Inst, OpIdx)) {
3422	if (MO.isReg()) {	3422	if (MO.isReg()) {
3423	LastSGPR = mc2PseudoReg(MO.getReg());	3423	LastSGPR = mc2PseudoReg(MO.getReg());
3424	// Pairs of registers with a partial intersections like these	3424	// Pairs of registers with a partial intersections like these
3425	// s0, s[0:1]	3425	// s0, s[0:1]
3426	// flat_scratch_lo, flat_scratch	3426	// flat_scratch_lo, flat_scratch
3427	// flat_scratch_lo, flat_scratch_hi	3427	// flat_scratch_lo, flat_scratch_hi
3428	// are theoretically valid but they are disabled anyway.	3428	// are theoretically valid but they are disabled anyway.
3429	// Note that this code mimics SIInstrInfo::verifyInstruction	3429	// Note that this code mimics SIInstrInfo::verifyInstruction
3430	if (SGPRsUsed.insert(LastSGPR).second) {	3430	if (SGPRsUsed.insert(LastSGPR).second) {
3431	++ConstantBusUseCount;	3431	++ConstantBusUseCount;
3432	}	3432	}
3433	} else { // Expression or a literal	3433	} else { // Expression or a literal
3434		3434
3435	if (Desc.operands()[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)	3435	if (Desc.operands()[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)
3436	continue; // special operand like VINTERP attr_chan	3436	continue; // special operand like VINTERP attr_chan
3437		3437
3438	// An instruction may use only one literal.	3438	// An instruction may use only one literal.
3439	// This has been validated on the previous step.	3439	// This has been validated on the previous step.
3440	// See validateVOPLiteral.	3440	// See validateVOPLiteral.
3441	// This literal may be used as more than one operand.	3441	// This literal may be used as more than one operand.
3442	// If all these operands are of the same size,	3442	// If all these operands are of the same size,
3443	// this literal counts as one scalar value.	3443	// this literal counts as one scalar value.
3444	// Otherwise it counts as 2 scalar values.	3444	// Otherwise it counts as 2 scalar values.
3445	// See "GFX10 Shader Programming", section 3.6.2.3.	3445	// See "GFX10 Shader Programming", section 3.6.2.3.
3446		3446
3447	unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);	3447	unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);
3448	if (Size < 4)	3448	if (Size < 4)
3449	Size = 4;	3449	Size = 4;
3450		3450
3451	if (NumLiterals == 0) {	3451	if (NumLiterals == 0) {
3452	NumLiterals = 1;	3452	NumLiterals = 1;
3453	LiteralSize = Size;	3453	LiteralSize = Size;
3454	} else if (LiteralSize != Size) {	3454	} else if (LiteralSize != Size) {
3455	NumLiterals = 2;	3455	NumLiterals = 2;
3456	}	3456	}
3457	}	3457	}
3458	}	3458	}
3459	}	3459	}
3460	ConstantBusUseCount += NumLiterals;	3460	ConstantBusUseCount += NumLiterals;
3461		3461
3462	if (ConstantBusUseCount <= getConstantBusLimit(Opcode))	3462	if (ConstantBusUseCount <= getConstantBusLimit(Opcode))
3463	return true;	3463	return true;
3464		3464
3465	SMLoc LitLoc = getLitLoc(Operands);	3465	SMLoc LitLoc = getLitLoc(Operands);
3466	SMLoc RegLoc = getRegLoc(LastSGPR, Operands);	3466	SMLoc RegLoc = getRegLoc(LastSGPR, Operands);
3467	SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;	3467	SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;
3468	Error(Loc, "invalid operand (violates constant bus restrictions)");	3468	Error(Loc, "invalid operand (violates constant bus restrictions)");
3469	return false;	3469	return false;
3470	}	3470	}
3471		3471
3472	bool AMDGPUAsmParser::validateVOPDRegBankConstraints(	3472	bool AMDGPUAsmParser::validateVOPDRegBankConstraints(
3473	const MCInst &Inst, const OperandVector &Operands) {	3473	const MCInst &Inst, const OperandVector &Operands) {
3474		3474
3475	const unsigned Opcode = Inst.getOpcode();	3475	const unsigned Opcode = Inst.getOpcode();
3476	if (!isVOPD(Opcode))	3476	if (!isVOPD(Opcode))
3477	return true;	3477	return true;
3478		3478
3479	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	3479	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
3480		3480
3481	auto getVRegIdx = [&](unsigned, unsigned OperandIdx) {	3481	auto getVRegIdx = [&](unsigned, unsigned OperandIdx) {
3482	const MCOperand &Opr = Inst.getOperand(OperandIdx);	3482	const MCOperand &Opr = Inst.getOperand(OperandIdx);
3483	return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI))	3483	return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI))
3484	? Opr.getReg()	3484	? Opr.getReg()
3485	: MCRegister::NoRegister;	3485	: MCRegister::NoRegister;
3486	};	3486	};
3487		3487
3488	const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);	3488	const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);
3489	auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(getVRegIdx);	3489	auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(getVRegIdx);
3490	if (!InvalidCompOprIdx)	3490	if (!InvalidCompOprIdx)
3491	return true;	3491	return true;
3492		3492
3493	auto CompOprIdx = *InvalidCompOprIdx;	3493	auto CompOprIdx = *InvalidCompOprIdx;
3494	auto ParsedIdx =	3494	auto ParsedIdx =
3495	std::max(InstInfo[VOPD::X].getIndexInParsedOperands(CompOprIdx),	3495	std::max(InstInfo[VOPD::X].getIndexInParsedOperands(CompOprIdx),
3496	InstInfo[VOPD::Y].getIndexInParsedOperands(CompOprIdx));	3496	InstInfo[VOPD::Y].getIndexInParsedOperands(CompOprIdx));
3497	assert(ParsedIdx > 0 && ParsedIdx < Operands.size());	3497	assert(ParsedIdx > 0 && ParsedIdx < Operands.size());
3498		3498
3499	auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();	3499	auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();
3500	if (CompOprIdx == VOPD::Component::DST) {	3500	if (CompOprIdx == VOPD::Component::DST) {
3501	Error(Loc, "one dst register must be even and the other odd");	3501	Error(Loc, "one dst register must be even and the other odd");
3502	} else {	3502	} else {
3503	auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM;	3503	auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM;
3504	Error(Loc, Twine("src") + Twine(CompSrcIdx) +	3504	Error(Loc, Twine("src") + Twine(CompSrcIdx) +
3505	" operands must use different VGPR banks");	3505	" operands must use different VGPR banks");
3506	}	3506	}
3507		3507
3508	return false;	3508	return false;
3509	}	3509	}
3510		3510
3511	bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {	3511	bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {
3512		3512
3513	const unsigned Opc = Inst.getOpcode();	3513	const unsigned Opc = Inst.getOpcode();
3514	const MCInstrDesc &Desc = MII.get(Opc);	3514	const MCInstrDesc &Desc = MII.get(Opc);
3515		3515
3516	if ((Desc.TSFlags & SIInstrFlags::IntClamp) != 0 && !hasIntClamp()) {	3516	if ((Desc.TSFlags & SIInstrFlags::IntClamp) != 0 && !hasIntClamp()) {
3517	int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);	3517	int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);
3518	assert(ClampIdx != -1);	3518	assert(ClampIdx != -1);
3519	return Inst.getOperand(ClampIdx).getImm() == 0;	3519	return Inst.getOperand(ClampIdx).getImm() == 0;
3520	}	3520	}
3521		3521
3522	return true;	3522	return true;
3523	}	3523	}
3524		3524
3525	bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,	3525	bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,
3526	const SMLoc &IDLoc) {	3526	const SMLoc &IDLoc) {
3527		3527
3528	const unsigned Opc = Inst.getOpcode();	3528	const unsigned Opc = Inst.getOpcode();
3529	const MCInstrDesc &Desc = MII.get(Opc);	3529	const MCInstrDesc &Desc = MII.get(Opc);
3530		3530
3531	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	3531	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)
3532	return true;	3532	return true;
3533		3533
3534	int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);	3534	int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);
3535	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	3535	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);
3536	int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);	3536	int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);
3537		3537
3538	assert(VDataIdx != -1);	3538	assert(VDataIdx != -1);
3539		3539
3540	if ((DMaskIdx == -1 \|\| TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray	3540	if ((DMaskIdx == -1 \|\| TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray
3541	return true;	3541	return true;
3542		3542
3543	unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);	3543	unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);
3544	unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;	3544	unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;
3545	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	3545	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;
3546	if (DMask == 0)	3546	if (DMask == 0)
3547	DMask = 1;	3547	DMask = 1;
3548		3548
3549	bool IsPackedD16 = false;	3549	bool IsPackedD16 = false;
3550	unsigned DataSize =	3550	unsigned DataSize =
3551	(Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask);	3551	(Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask);
3552	if (hasPackedD16()) {	3552	if (hasPackedD16()) {
3553	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	3553	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);
3554	IsPackedD16 = D16Idx >= 0;	3554	IsPackedD16 = D16Idx >= 0;
3555	if (IsPackedD16 && Inst.getOperand(D16Idx).getImm())	3555	if (IsPackedD16 && Inst.getOperand(D16Idx).getImm())
3556	DataSize = (DataSize + 1) / 2;	3556	DataSize = (DataSize + 1) / 2;
3557	}	3557	}
3558		3558
3559	if ((VDataSize / 4) == DataSize + TFESize)	3559	if ((VDataSize / 4) == DataSize + TFESize)
3560	return true;	3560	return true;
3561		3561
3562	StringRef Modifiers;	3562	StringRef Modifiers;
3563	if (isGFX90A())	3563	if (isGFX90A())
3564	Modifiers = IsPackedD16 ? "dmask and d16" : "dmask";	3564	Modifiers = IsPackedD16 ? "dmask and d16" : "dmask";
3565	else	3565	else
3566	Modifiers = IsPackedD16 ? "dmask, d16 and tfe" : "dmask and tfe";	3566	Modifiers = IsPackedD16 ? "dmask, d16 and tfe" : "dmask and tfe";
3567		3567
3568	Error(IDLoc, Twine("image data size does not match ") + Modifiers);	3568	Error(IDLoc, Twine("image data size does not match ") + Modifiers);
3569	return false;	3569	return false;
3570	}	3570	}
3571		3571
3572	bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,	3572	bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,
3573	const SMLoc &IDLoc) {	3573	const SMLoc &IDLoc) {
3574	const unsigned Opc = Inst.getOpcode();	3574	const unsigned Opc = Inst.getOpcode();
3575	const MCInstrDesc &Desc = MII.get(Opc);	3575	const MCInstrDesc &Desc = MII.get(Opc);
3576		3576
3577	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 \|\| !isGFX10Plus())	3577	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 \|\| !isGFX10Plus())
3578	return true;	3578	return true;
3579		3579
3580	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	3580	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);
3581		3581
3582	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	3582	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3583	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	3583	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3584	int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);	3584	int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);
3585	int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);	3585	int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);
3586	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	3586	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
3587	int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);	3587	int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);
3588		3588
3589	assert(VAddr0Idx != -1);	3589	assert(VAddr0Idx != -1);
3590	assert(SrsrcIdx != -1);	3590	assert(SrsrcIdx != -1);
3591	assert(SrsrcIdx > VAddr0Idx);	3591	assert(SrsrcIdx > VAddr0Idx);
3592		3592
3593	bool IsA16 = Inst.getOperand(A16Idx).getImm();	3593	bool IsA16 = Inst.getOperand(A16Idx).getImm();
3594	if (BaseOpcode->BVH) {	3594	if (BaseOpcode->BVH) {
3595	if (IsA16 == BaseOpcode->A16)	3595	if (IsA16 == BaseOpcode->A16)
3596	return true;	3596	return true;
3597	Error(IDLoc, "image address size does not match a16");	3597	Error(IDLoc, "image address size does not match a16");
3598	return false;	3598	return false;
3599	}	3599	}
3600		3600
3601	unsigned Dim = Inst.getOperand(DimIdx).getImm();	3601	unsigned Dim = Inst.getOperand(DimIdx).getImm();
3602	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	3602	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
3603	bool IsNSA = SrsrcIdx - VAddr0Idx > 1;	3603	bool IsNSA = SrsrcIdx - VAddr0Idx > 1;
3604	unsigned ActualAddrSize =	3604	unsigned ActualAddrSize =
3605	IsNSA ? SrsrcIdx - VAddr0Idx	3605	IsNSA ? SrsrcIdx - VAddr0Idx
3606	: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;	3606	: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;
3607		3607
3608	unsigned ExpectedAddrSize =	3608	unsigned ExpectedAddrSize =
3609	AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());	3609	AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());
3610		3610
3611	if (IsNSA) {	3611	if (IsNSA) {
3612	if (hasPartialNSAEncoding() && ExpectedAddrSize > getNSAMaxSize()) {	3612	if (hasPartialNSAEncoding() && ExpectedAddrSize > getNSAMaxSize()) {
3613	int VAddrLastIdx = SrsrcIdx - 1;	3613	int VAddrLastIdx = SrsrcIdx - 1;
3614	unsigned VAddrLastSize =	3614	unsigned VAddrLastSize =
3615	AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;	3615	AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;
3616		3616
3617	ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;	3617	ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;
3618	}	3618	}
3619	} else {	3619	} else {
3620	if (ExpectedAddrSize > 12)	3620	if (ExpectedAddrSize > 12)
3621	ExpectedAddrSize = 16;	3621	ExpectedAddrSize = 16;
3622		3622
3623	// Allow oversized 8 VGPR vaddr when only 5/6/7 VGPRs are required.	3623	// Allow oversized 8 VGPR vaddr when only 5/6/7 VGPRs are required.
3624	// This provides backward compatibility for assembly created	3624	// This provides backward compatibility for assembly created
3625	// before 160b/192b/224b types were directly supported.	3625	// before 160b/192b/224b types were directly supported.
3626	if (ActualAddrSize == 8 && (ExpectedAddrSize >= 5 && ExpectedAddrSize <= 7))	3626	if (ActualAddrSize == 8 && (ExpectedAddrSize >= 5 && ExpectedAddrSize <= 7))
3627	return true;	3627	return true;
3628	}	3628	}
3629		3629
3630	if (ActualAddrSize == ExpectedAddrSize)	3630	if (ActualAddrSize == ExpectedAddrSize)
3631	return true;	3631	return true;
3632		3632
3633	Error(IDLoc, "image address size does not match dim and a16");	3633	Error(IDLoc, "image address size does not match dim and a16");
3634	return false;	3634	return false;
3635	}	3635	}
3636		3636
3637	bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {	3637	bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {
3638		3638
3639	const unsigned Opc = Inst.getOpcode();	3639	const unsigned Opc = Inst.getOpcode();
3640	const MCInstrDesc &Desc = MII.get(Opc);	3640	const MCInstrDesc &Desc = MII.get(Opc);
3641		3641
3642	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	3642	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)
3643	return true;	3643	return true;
3644	if (!Desc.mayLoad() \|\| !Desc.mayStore())	3644	if (!Desc.mayLoad() \|\| !Desc.mayStore())
3645	return true; // Not atomic	3645	return true; // Not atomic
3646		3646
3647	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	3647	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);
3648	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	3648	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;
3649		3649
3650	// This is an incomplete check because image_atomic_cmpswap	3650	// This is an incomplete check because image_atomic_cmpswap
3651	// may only use 0x3 and 0xf while other atomic operations	3651	// may only use 0x3 and 0xf while other atomic operations
3652	// may use 0x1 and 0x3. However these limitations are	3652	// may use 0x1 and 0x3. However these limitations are
3653	// verified when we check that dmask matches dst size.	3653	// verified when we check that dmask matches dst size.
3654	return DMask == 0x1 \|\| DMask == 0x3 \|\| DMask == 0xf;	3654	return DMask == 0x1 \|\| DMask == 0x3 \|\| DMask == 0xf;
3655	}	3655	}
3656		3656
3657	bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {	3657	bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {
3658		3658
3659	const unsigned Opc = Inst.getOpcode();	3659	const unsigned Opc = Inst.getOpcode();
3660	const MCInstrDesc &Desc = MII.get(Opc);	3660	const MCInstrDesc &Desc = MII.get(Opc);
3661		3661
3662	if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0)	3662	if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0)
3663	return true;	3663	return true;
3664		3664
3665	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	3665	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);
3666	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	3666	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;
3667		3667
3668	// GATHER4 instructions use dmask in a different fashion compared to	3668	// GATHER4 instructions use dmask in a different fashion compared to
3669	// other MIMG instructions. The only useful DMASK values are	3669	// other MIMG instructions. The only useful DMASK values are
3670	// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns	3670	// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns
3671	// (red,red,red,red) etc.) The ISA document doesn't mention	3671	// (red,red,red,red) etc.) The ISA document doesn't mention
3672	// this.	3672	// this.
3673	return DMask == 0x1 \|\| DMask == 0x2 \|\| DMask == 0x4 \|\| DMask == 0x8;	3673	return DMask == 0x1 \|\| DMask == 0x2 \|\| DMask == 0x4 \|\| DMask == 0x8;
3674	}	3674	}
3675		3675
3676	bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {	3676	bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {
3677	const unsigned Opc = Inst.getOpcode();	3677	const unsigned Opc = Inst.getOpcode();
3678	const MCInstrDesc &Desc = MII.get(Opc);	3678	const MCInstrDesc &Desc = MII.get(Opc);
3679		3679
3680	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	3680	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)
3681	return true;	3681	return true;
3682		3682
3683	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	3683	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);
3684	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	3684	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =
3685	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	3685	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);
3686		3686
3687	if (!BaseOpcode->MSAA)	3687	if (!BaseOpcode->MSAA)
3688	return true;	3688	return true;
3689		3689
3690	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	3690	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);
3691	assert(DimIdx != -1);	3691	assert(DimIdx != -1);
3692		3692
3693	unsigned Dim = Inst.getOperand(DimIdx).getImm();	3693	unsigned Dim = Inst.getOperand(DimIdx).getImm();
3694	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	3694	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);
3695		3695
3696	return DimInfo->MSAA;	3696	return DimInfo->MSAA;
3697	}	3697	}
3698		3698
3699	static bool IsMovrelsSDWAOpcode(const unsigned Opcode)	3699	static bool IsMovrelsSDWAOpcode(const unsigned Opcode)
3700	{	3700	{
3701	switch (Opcode) {	3701	switch (Opcode) {
3702	case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:	3702	case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:
3703	case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:	3703	case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:
3704	case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:	3704	case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:
3705	return true;	3705	return true;
3706	default:	3706	default:
3707	return false;	3707	return false;
3708	}	3708	}
3709	}	3709	}
3710		3710
3711	// movrels* opcodes should only allow VGPRS as src0.	3711	// movrels* opcodes should only allow VGPRS as src0.
3712	// This is specified in .td description for vop1/vop3,	3712	// This is specified in .td description for vop1/vop3,
3713	// but sdwa is handled differently. See isSDWAOperand.	3713	// but sdwa is handled differently. See isSDWAOperand.
3714	bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,	3714	bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,
3715	const OperandVector &Operands) {	3715	const OperandVector &Operands) {
3716		3716
3717	const unsigned Opc = Inst.getOpcode();	3717	const unsigned Opc = Inst.getOpcode();
3718	const MCInstrDesc &Desc = MII.get(Opc);	3718	const MCInstrDesc &Desc = MII.get(Opc);
3719		3719
3720	if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 \|\| !IsMovrelsSDWAOpcode(Opc))	3720	if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 \|\| !IsMovrelsSDWAOpcode(Opc))
3721	return true;	3721	return true;
3722		3722
3723	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	3723	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3724	assert(Src0Idx != -1);	3724	assert(Src0Idx != -1);
3725		3725
3726	SMLoc ErrLoc;	3726	SMLoc ErrLoc;
3727	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	3727	const MCOperand &Src0 = Inst.getOperand(Src0Idx);
3728	if (Src0.isReg()) {	3728	if (Src0.isReg()) {
3729	auto Reg = mc2PseudoReg(Src0.getReg());	3729	auto Reg = mc2PseudoReg(Src0.getReg());
3730	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	3730	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
3731	if (!isSGPR(Reg, TRI))	3731	if (!isSGPR(Reg, TRI))
3732	return true;	3732	return true;
3733	ErrLoc = getRegLoc(Reg, Operands);	3733	ErrLoc = getRegLoc(Reg, Operands);
3734	} else {	3734	} else {
3735	ErrLoc = getConstLoc(Operands);	3735	ErrLoc = getConstLoc(Operands);
3736	}	3736	}
3737		3737
3738	Error(ErrLoc, "source operand must be a VGPR");	3738	Error(ErrLoc, "source operand must be a VGPR");
3739	return false;	3739	return false;
3740	}	3740	}
3741		3741
3742	bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,	3742	bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,
3743	const OperandVector &Operands) {	3743	const OperandVector &Operands) {
3744		3744
3745	const unsigned Opc = Inst.getOpcode();	3745	const unsigned Opc = Inst.getOpcode();
3746		3746
3747	if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)	3747	if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)
3748	return true;	3748	return true;
3749		3749
3750	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	3750	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
3751	assert(Src0Idx != -1);	3751	assert(Src0Idx != -1);
3752		3752
3753	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	3753	const MCOperand &Src0 = Inst.getOperand(Src0Idx);
3754	if (!Src0.isReg())	3754	if (!Src0.isReg())
3755	return true;	3755	return true;
3756		3756
3757	auto Reg = mc2PseudoReg(Src0.getReg());	3757	auto Reg = mc2PseudoReg(Src0.getReg());
3758	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	3758	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
3759	if (!isGFX90A() && isSGPR(Reg, TRI)) {	3759	if (!isGFX90A() && isSGPR(Reg, TRI)) {
3760	Error(getRegLoc(Reg, Operands),	3760	Error(getRegLoc(Reg, Operands),
3761	"source operand must be either a VGPR or an inline constant");	3761	"source operand must be either a VGPR or an inline constant");
3762	return false;	3762	return false;
3763	}	3763	}
3764		3764
3765	return true;	3765	return true;
3766	}	3766	}
3767		3767
3768	bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,	3768	bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,
3769	const OperandVector &Operands) {	3769	const OperandVector &Operands) {
3770	unsigned Opcode = Inst.getOpcode();	3770	unsigned Opcode = Inst.getOpcode();
3771	const MCInstrDesc &Desc = MII.get(Opcode);	3771	const MCInstrDesc &Desc = MII.get(Opcode);
3772		3772
3773	if (!(Desc.TSFlags & SIInstrFlags::IsMAI) \|\|	3773	if (!(Desc.TSFlags & SIInstrFlags::IsMAI) \|\|
3774	!getFeatureBits()[FeatureMFMAInlineLiteralBug])	3774	!getFeatureBits()[FeatureMFMAInlineLiteralBug])
3775	return true;	3775	return true;
3776		3776
3777	const int Src2Idx = getNamedOperandIdx(Opcode, OpName::src2);	3777	const int Src2Idx = getNamedOperandIdx(Opcode, OpName::src2);
3778	if (Src2Idx == -1)	3778	if (Src2Idx == -1)
3779	return true;	3779	return true;
3780		3780
3781	if (Inst.getOperand(Src2Idx).isImm() && isInlineConstant(Inst, Src2Idx)) {	3781	if (Inst.getOperand(Src2Idx).isImm() && isInlineConstant(Inst, Src2Idx)) {
3782	Error(getConstLoc(Operands),	3782	Error(getConstLoc(Operands),
3783	"inline constants are not allowed for this operand");	3783	"inline constants are not allowed for this operand");
3784	return false;	3784	return false;
3785	}	3785	}
3786		3786
3787	return true;	3787	return true;
3788	}	3788	}
3789		3789
3790	bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,	3790	bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,
3791	const OperandVector &Operands) {	3791	const OperandVector &Operands) {
3792	const unsigned Opc = Inst.getOpcode();	3792	const unsigned Opc = Inst.getOpcode();
3793	const MCInstrDesc &Desc = MII.get(Opc);	3793	const MCInstrDesc &Desc = MII.get(Opc);
3794		3794
3795	if ((Desc.TSFlags & SIInstrFlags::IsMAI) == 0)	3795	if ((Desc.TSFlags & SIInstrFlags::IsMAI) == 0)
3796	return true;	3796	return true;
3797		3797
3798	const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);	3798	const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
3799	if (Src2Idx == -1)	3799	if (Src2Idx == -1)
3800	return true;	3800	return true;
3801		3801
3802	const MCOperand &Src2 = Inst.getOperand(Src2Idx);	3802	const MCOperand &Src2 = Inst.getOperand(Src2Idx);
3803	if (!Src2.isReg())	3803	if (!Src2.isReg())
3804	return true;	3804	return true;
3805		3805
3806	MCRegister Src2Reg = Src2.getReg();	3806	MCRegister Src2Reg = Src2.getReg();
3807	MCRegister DstReg = Inst.getOperand(0).getReg();	3807	MCRegister DstReg = Inst.getOperand(0).getReg();
3808	if (Src2Reg == DstReg)	3808	if (Src2Reg == DstReg)
3809	return true;	3809	return true;
3810		3810
3811	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	3811	const MCRegisterInfo *TRI = getContext().getRegisterInfo();
3812	if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)	3812	if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)
3813	return true;	3813	return true;
3814		3814
3815	if (TRI->regsOverlap(Src2Reg, DstReg)) {	3815	if (TRI->regsOverlap(Src2Reg, DstReg)) {
3816	Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),	3816	Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),
3817	"source 2 operand must not partially overlap with dst");	3817	"source 2 operand must not partially overlap with dst");
3818	return false;	3818	return false;
3819	}	3819	}
3820		3820
3821	return true;	3821	return true;
3822	}	3822	}
3823		3823
3824	bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {	3824	bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {
3825	switch (Inst.getOpcode()) {	3825	switch (Inst.getOpcode()) {
3826	default:	3826	default:
3827	return true;	3827	return true;
3828	case V_DIV_SCALE_F32_gfx6_gfx7:	3828	case V_DIV_SCALE_F32_gfx6_gfx7:
3829	case V_DIV_SCALE_F32_vi:	3829	case V_DIV_SCALE_F32_vi:
3830	case V_DIV_SCALE_F32_gfx10:	3830	case V_DIV_SCALE_F32_gfx10:
3831	case V_DIV_SCALE_F64_gfx6_gfx7:	3831	case V_DIV_SCALE_F64_gfx6_gfx7:
3832	case V_DIV_SCALE_F64_vi:	3832	case V_DIV_SCALE_F64_vi:
3833	case V_DIV_SCALE_F64_gfx10:	3833	case V_DIV_SCALE_F64_gfx10:
3834	break;	3834	break;
3835	}	3835	}
3836		3836
3837	// TODO: Check that src0 = src1 or src2.	3837	// TODO: Check that src0 = src1 or src2.
3838		3838
3839	for (auto Name : {AMDGPU::OpName::src0_modifiers,	3839	for (auto Name : {AMDGPU::OpName::src0_modifiers,
3840	AMDGPU::OpName::src2_modifiers,	3840	AMDGPU::OpName::src2_modifiers,
3841	AMDGPU::OpName::src2_modifiers}) {	3841	AMDGPU::OpName::src2_modifiers}) {
3842	if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))	3842	if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))
3843	.getImm() &	3843	.getImm() &
3844	SISrcMods::ABS) {	3844	SISrcMods::ABS) {
3845	return false;	3845	return false;
3846	}	3846	}
3847	}	3847	}
3848		3848
3849	return true;	3849	return true;
3850	}	3850	}
3851		3851
3852	bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {	3852	bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {
3853		3853
3854	const unsigned Opc = Inst.getOpcode();	3854	const unsigned Opc = Inst.getOpcode();
3855	const MCInstrDesc &Desc = MII.get(Opc);	3855	const MCInstrDesc &Desc = MII.get(Opc);
3856		3856
3857	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	3857	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)
3858	return true;	3858	return true;
3859		3859
3860	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	3860	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);
3861	if (D16Idx >= 0 && Inst.getOperand(D16Idx).getImm()) {	3861	if (D16Idx >= 0 && Inst.getOperand(D16Idx).getImm()) {
3862	if (isCI() \|\| isSI())	3862	if (isCI() \|\| isSI())
3863	return false;	3863	return false;
3864	}	3864	}
3865		3865
3866	return true;	3866	return true;
3867	}	3867	}
3868		3868
3869	static bool IsRevOpcode(const unsigned Opcode)	3869	static bool IsRevOpcode(const unsigned Opcode)
3870	{	3870	{
3871	switch (Opcode) {	3871	switch (Opcode) {
3872	case AMDGPU::V_SUBREV_F32_e32:	3872	case AMDGPU::V_SUBREV_F32_e32:
3873	case AMDGPU::V_SUBREV_F32_e64:	3873	case AMDGPU::V_SUBREV_F32_e64:
3874	case AMDGPU::V_SUBREV_F32_e32_gfx10:	3874	case AMDGPU::V_SUBREV_F32_e32_gfx10:
3875	case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:	3875	case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:
3876	case AMDGPU::V_SUBREV_F32_e32_vi:	3876	case AMDGPU::V_SUBREV_F32_e32_vi:
3877	case AMDGPU::V_SUBREV_F32_e64_gfx10:	3877	case AMDGPU::V_SUBREV_F32_e64_gfx10:
3878	case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:	3878	case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:
3879	case AMDGPU::V_SUBREV_F32_e64_vi:	3879	case AMDGPU::V_SUBREV_F32_e64_vi:
3880		3880
3881	case AMDGPU::V_SUBREV_CO_U32_e32:	3881	case AMDGPU::V_SUBREV_CO_U32_e32:
3882	case AMDGPU::V_SUBREV_CO_U32_e64:	3882	case AMDGPU::V_SUBREV_CO_U32_e64:
3883	case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:	3883	case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:
3884	case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:	3884	case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:
3885		3885
3886	case AMDGPU::V_SUBBREV_U32_e32:	3886	case AMDGPU::V_SUBBREV_U32_e32:
3887	case AMDGPU::V_SUBBREV_U32_e64:	3887	case AMDGPU::V_SUBBREV_U32_e64:
3888	case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:	3888	case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:
3889	case AMDGPU::V_SUBBREV_U32_e32_vi:	3889	case AMDGPU::V_SUBBREV_U32_e32_vi:
3890	case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:	3890	case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:
3891	case AMDGPU::V_SUBBREV_U32_e64_vi:	3891	case AMDGPU::V_SUBBREV_U32_e64_vi:
3892		3892
3893	case AMDGPU::V_SUBREV_U32_e32:	3893	case AMDGPU::V_SUBREV_U32_e32:
3894	case AMDGPU::V_SUBREV_U32_e64:	3894	case AMDGPU::V_SUBREV_U32_e64:
3895	case AMDGPU::V_SUBREV_U32_e32_gfx9:	3895	case AMDGPU::V_SUBREV_U32_e32_gfx9:
3896	case AMDGPU::V_SUBREV_U32_e32_vi:	3896	case AMDGPU::V_SUBREV_U32_e32_vi:
3897	case AMDGPU::V_SUBREV_U32_e64_gfx9:	3897	case AMDGPU::V_SUBREV_U32_e64_gfx9:
3898	case AMDGPU::V_SUBREV_U32_e64_vi:	3898	case AMDGPU::V_SUBREV_U32_e64_vi:
3899		3899
3900	case AMDGPU::V_SUBREV_F16_e32:	3900	case AMDGPU::V_SUBREV_F16_e32:
3901	case AMDGPU::V_SUBREV_F16_e64:	3901	case AMDGPU::V_SUBREV_F16_e64:
3902	case AMDGPU::V_SUBREV_F16_e32_gfx10:	3902	case AMDGPU::V_SUBREV_F16_e32_gfx10:
3903	case AMDGPU::V_SUBREV_F16_e32_vi:	3903	case AMDGPU::V_SUBREV_F16_e32_vi:
3904	case AMDGPU::V_SUBREV_F16_e64_gfx10:	3904	case AMDGPU::V_SUBREV_F16_e64_gfx10:
3905	case AMDGPU::V_SUBREV_F16_e64_vi:	3905	case AMDGPU::V_SUBREV_F16_e64_vi:
3906		3906
3907	case AMDGPU::V_SUBREV_U16_e32:	3907	case AMDGPU::V_SUBREV_U16_e32:
3908	case AMDGPU::V_SUBREV_U16_e64:	3908	case AMDGPU::V_SUBREV_U16_e64:
3909	case AMDGPU::V_SUBREV_U16_e32_vi:	3909	case AMDGPU::V_SUBREV_U16_e32_vi:
3910	case AMDGPU::V_SUBREV_U16_e64_vi:	3910	case AMDGPU::V_SUBREV_U16_e64_vi:
3911		3911
3912	case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:	3912	case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:
3913	case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:	3913	case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:
3914	case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:	3914	case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:
3915		3915
3916	case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:	3916	case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:
3917	case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:	3917	case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:
3918		3918
3919	case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:	3919	case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:
3920	case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:	3920	case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:
3921		3921
3922	case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:	3922	case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:
3923	case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:	3923	case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:
3924		3924
3925	case AMDGPU::V_LSHRREV_B32_e32:	3925	case AMDGPU::V_LSHRREV_B32_e32:
3926	case AMDGPU::V_LSHRREV_B32_e64:	3926	case AMDGPU::V_LSHRREV_B32_e64:
3927	case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:	3927	case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:
3928	case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:	3928	case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:
3929	case AMDGPU::V_LSHRREV_B32_e32_vi:	3929	case AMDGPU::V_LSHRREV_B32_e32_vi:
3930	case AMDGPU::V_LSHRREV_B32_e64_vi:	3930	case AMDGPU::V_LSHRREV_B32_e64_vi:
3931	case AMDGPU::V_LSHRREV_B32_e32_gfx10:	3931	case AMDGPU::V_LSHRREV_B32_e32_gfx10:
3932	case AMDGPU::V_LSHRREV_B32_e64_gfx10:	3932	case AMDGPU::V_LSHRREV_B32_e64_gfx10:
3933		3933
3934	case AMDGPU::V_ASHRREV_I32_e32:	3934	case AMDGPU::V_ASHRREV_I32_e32:
3935	case AMDGPU::V_ASHRREV_I32_e64:	3935	case AMDGPU::V_ASHRREV_I32_e64:
3936	case AMDGPU::V_ASHRREV_I32_e32_gfx10:	3936	case AMDGPU::V_ASHRREV_I32_e32_gfx10:
3937	case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:	3937	case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:
3938	case AMDGPU::V_ASHRREV_I32_e32_vi:	3938	case AMDGPU::V_ASHRREV_I32_e32_vi:
3939	case AMDGPU::V_ASHRREV_I32_e64_gfx10:	3939	case AMDGPU::V_ASHRREV_I32_e64_gfx10:
3940	case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:	3940	case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:
3941	case AMDGPU::V_ASHRREV_I32_e64_vi:	3941	case AMDGPU::V_ASHRREV_I32_e64_vi:
3942		3942
3943	case AMDGPU::V_LSHLREV_B32_e32:	3943	case AMDGPU::V_LSHLREV_B32_e32:
3944	case AMDGPU::V_LSHLREV_B32_e64:	3944	case AMDGPU::V_LSHLREV_B32_e64:
3945	case AMDGPU::V_LSHLREV_B32_e32_gfx10:	3945	case AMDGPU::V_LSHLREV_B32_e32_gfx10:
3946	case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:	3946	case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:
3947	case AMDGPU::V_LSHLREV_B32_e32_vi:	3947	case AMDGPU::V_LSHLREV_B32_e32_vi:
3948	case AMDGPU::V_LSHLREV_B32_e64_gfx10:	3948	case AMDGPU::V_LSHLREV_B32_e64_gfx10:
3949	case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:	3949	case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:
3950	case AMDGPU::V_LSHLREV_B32_e64_vi:	3950	case AMDGPU::V_LSHLREV_B32_e64_vi:
3951		3951
3952	case AMDGPU::V_LSHLREV_B16_e32:	3952	case AMDGPU::V_LSHLREV_B16_e32:
3953	case AMDGPU::V_LSHLREV_B16_e64:	3953	case AMDGPU::V_LSHLREV_B16_e64:
3954	case AMDGPU::V_LSHLREV_B16_e32_vi:	3954	case AMDGPU::V_LSHLREV_B16_e32_vi:
3955	case AMDGPU::V_LSHLREV_B16_e64_vi:	3955	case AMDGPU::V_LSHLREV_B16_e64_vi:
3956	case AMDGPU::V_LSHLREV_B16_gfx10:	3956	case AMDGPU::V_LSHLREV_B16_gfx10:
3957		3957
3958	case AMDGPU::V_LSHRREV_B16_e32:	3958	case AMDGPU::V_LSHRREV_B16_e32:
3959	case AMDGPU::V_LSHRREV_B16_e64:	3959	case AMDGPU::V_LSHRREV_B16_e64:
3960	case AMDGPU::V_LSHRREV_B16_e32_vi:	3960	case AMDGPU::V_LSHRREV_B16_e32_vi:
3961	case AMDGPU::V_LSHRREV_B16_e64_vi:	3961	case AMDGPU::V_LSHRREV_B16_e64_vi:
3962	case AMDGPU::V_LSHRREV_B16_gfx10:	3962	case AMDGPU::V_LSHRREV_B16_gfx10:
3963		3963
3964	case AMDGPU::V_ASHRREV_I16_e32:	3964	case AMDGPU::V_ASHRREV_I16_e32:
3965	case AMDGPU::V_ASHRREV_I16_e64:	3965	case AMDGPU::V_ASHRREV_I16_e64:
3966	case AMDGPU::V_ASHRREV_I16_e32_vi:	3966	case AMDGPU::V_ASHRREV_I16_e32_vi:
3967	case AMDGPU::V_ASHRREV_I16_e64_vi:	3967	case AMDGPU::V_ASHRREV_I16_e64_vi:
3968	case AMDGPU::V_ASHRREV_I16_gfx10:	3968	case AMDGPU::V_ASHRREV_I16_gfx10:
3969		3969
3970	case AMDGPU::V_LSHLREV_B64_e64:	3970	case AMDGPU::V_LSHLREV_B64_e64:
3971	case AMDGPU::V_LSHLREV_B64_gfx10:	3971	case AMDGPU::V_LSHLREV_B64_gfx10:
3972	case AMDGPU::V_LSHLREV_B64_vi:	3972	case AMDGPU::V_LSHLREV_B64_vi:
3973		3973
3974	case AMDGPU::V_LSHRREV_B64_e64:	3974	case AMDGPU::V_LSHRREV_B64_e64:
3975	case AMDGPU::V_LSHRREV_B64_gfx10:	3975	case AMDGPU::V_LSHRREV_B64_gfx10:
3976	case AMDGPU::V_LSHRREV_B64_vi:	3976	case AMDGPU::V_LSHRREV_B64_vi:
3977		3977
3978	case AMDGPU::V_ASHRREV_I64_e64:	3978	case AMDGPU::V_ASHRREV_I64_e64:
3979	case AMDGPU::V_ASHRREV_I64_gfx10:	3979	case AMDGPU::V_ASHRREV_I64_gfx10:
3980	case AMDGPU::V_ASHRREV_I64_vi:	3980	case AMDGPU::V_ASHRREV_I64_vi:
3981		3981
3982	case AMDGPU::V_PK_LSHLREV_B16:	3982	case AMDGPU::V_PK_LSHLREV_B16:
3983	case AMDGPU::V_PK_LSHLREV_B16_gfx10:	3983	case AMDGPU::V_PK_LSHLREV_B16_gfx10:
3984	case AMDGPU::V_PK_LSHLREV_B16_vi:	3984	case AMDGPU::V_PK_LSHLREV_B16_vi:
3985		3985
3986	case AMDGPU::V_PK_LSHRREV_B16:	3986	case AMDGPU::V_PK_LSHRREV_B16:
3987	case AMDGPU::V_PK_LSHRREV_B16_gfx10:	3987	case AMDGPU::V_PK_LSHRREV_B16_gfx10:
3988	case AMDGPU::V_PK_LSHRREV_B16_vi:	3988	case AMDGPU::V_PK_LSHRREV_B16_vi:
3989	case AMDGPU::V_PK_ASHRREV_I16:	3989	case AMDGPU::V_PK_ASHRREV_I16:
3990	case AMDGPU::V_PK_ASHRREV_I16_gfx10:	3990	case AMDGPU::V_PK_ASHRREV_I16_gfx10:
3991	case AMDGPU::V_PK_ASHRREV_I16_vi:	3991	case AMDGPU::V_PK_ASHRREV_I16_vi:
3992	return true;	3992	return true;
3993	default:	3993	default:
3994	return false;	3994	return false;
3995	}	3995	}
3996	}	3996	}
3997		3997
3998	std::optional	3998	std::optional
3999	AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {	3999	AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {
4000		4000
4001	using namespace SIInstrFlags;	4001	using namespace SIInstrFlags;
4002	const unsigned Opcode = Inst.getOpcode();	4002	const unsigned Opcode = Inst.getOpcode();
4003	const MCInstrDesc &Desc = MII.get(Opcode);	4003	const MCInstrDesc &Desc = MII.get(Opcode);
4004		4004
4005	// lds_direct register is defined so that it can be used	4005	// lds_direct register is defined so that it can be used
4006	// with 9-bit operands only. Ignore encodings which do not accept these.	4006	// with 9-bit operands only. Ignore encodings which do not accept these.
4007	const auto Enc = VOP1 \| VOP2 \| VOP3 \| VOPC \| VOP3P \| SIInstrFlags::SDWA;	4007	const auto Enc = VOP1 \| VOP2 \| VOP3 \| VOPC \| VOP3P \| SIInstrFlags::SDWA;
4008	if ((Desc.TSFlags & Enc) == 0)	4008	if ((Desc.TSFlags & Enc) == 0)
4009	return std::nullopt;	4009	return std::nullopt;
4010		4010
4011	for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {	4011	for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {
4012	auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);	4012	auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);
4013	if (SrcIdx == -1)	4013	if (SrcIdx == -1)
4014	break;	4014	break;
4015	const auto &Src = Inst.getOperand(SrcIdx);	4015	const auto &Src = Inst.getOperand(SrcIdx);
4016	if (Src.isReg() && Src.getReg() == LDS_DIRECT) {	4016	if (Src.isReg() && Src.getReg() == LDS_DIRECT) {
4017		4017
4018	if (isGFX90A() \|\| isGFX11Plus())	4018	if (isGFX90A() \|\| isGFX11Plus())
4019	return StringRef("lds_direct is not supported on this GPU");	4019	return StringRef("lds_direct is not supported on this GPU");
4020		4020
4021	if (IsRevOpcode(Opcode) \|\| (Desc.TSFlags & SIInstrFlags::SDWA))	4021	if (IsRevOpcode(Opcode) \|\| (Desc.TSFlags & SIInstrFlags::SDWA))
4022	return StringRef("lds_direct cannot be used with this instruction");	4022	return StringRef("lds_direct cannot be used with this instruction");
4023		4023
4024	if (SrcName != OpName::src0)	4024	if (SrcName != OpName::src0)
4025	return StringRef("lds_direct may be used as src0 only");	4025	return StringRef("lds_direct may be used as src0 only");
4026	}	4026	}
4027	}	4027	}
4028		4028
4029	return std::nullopt;	4029	return std::nullopt;
4030	}	4030	}
4031		4031
4032	SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {	4032	SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {
4033	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	4033	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4034	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	4034	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4035	if (Op.isFlatOffset())	4035	if (Op.isFlatOffset())
4036	return Op.getStartLoc();	4036	return Op.getStartLoc();
4037	}	4037	}
4038	return getLoc();	4038	return getLoc();
4039	}	4039	}
4040		4040
4041	bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,	4041	bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
4042	const OperandVector &Operands) {	4042	const OperandVector &Operands) {
4043	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	4043	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
4044	if ((TSFlags & SIInstrFlags::FLAT) == 0)	4044	if ((TSFlags & SIInstrFlags::FLAT) == 0)
4045	return true;	4045	return true;
4046		4046
4047	auto Opcode = Inst.getOpcode();	4047	auto Opcode = Inst.getOpcode();
4048	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	4048	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
4049	assert(OpNum != -1);	4049	assert(OpNum != -1);
4050		4050
4051	const auto &Op = Inst.getOperand(OpNum);	4051	const auto &Op = Inst.getOperand(OpNum);
4052	if (!hasFlatOffsets() && Op.getImm() != 0) {	4052	if (!hasFlatOffsets() && Op.getImm() != 0) {
4053	Error(getFlatOffsetLoc(Operands),	4053	Error(getFlatOffsetLoc(Operands),
4054	"flat offset modifier is not supported on this GPU");	4054	"flat offset modifier is not supported on this GPU");
4055	return false;	4055	return false;
4056	}	4056	}
4057		4057
4058	// For FLAT segment the offset must be positive;	4058	// For FLAT segment the offset must be positive;
4059	// MSB is ignored and forced to zero.	4059	// MSB is ignored and forced to zero.
4060	unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI());	4060	unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI());
4061	bool AllowNegative =	4061	bool AllowNegative =
4062	TSFlags & (SIInstrFlags::FlatGlobal \| SIInstrFlags::FlatScratch);	4062	TSFlags & (SIInstrFlags::FlatGlobal \| SIInstrFlags::FlatScratch);
4063	if (!isIntN(OffsetSize, Op.getImm()) \|\| (!AllowNegative && Op.getImm() < 0)) {	4063	if (!isIntN(OffsetSize, Op.getImm()) \|\| (!AllowNegative && Op.getImm() < 0)) {
4064	Error(getFlatOffsetLoc(Operands),	4064	Error(getFlatOffsetLoc(Operands),
4065	Twine("expected a ") +	4065	Twine("expected a ") +
4066	(AllowNegative ? Twine(OffsetSize) + "-bit signed offset"	4066	(AllowNegative ? Twine(OffsetSize) + "-bit signed offset"
4067	: Twine(OffsetSize - 1) + "-bit unsigned offset"));	4067	: Twine(OffsetSize - 1) + "-bit unsigned offset"));
4068	return false;	4068	return false;
4069	}	4069	}
4070		4070
4071	return true;	4071	return true;
4072	}	4072	}
4073		4073
4074	SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {	4074	SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {
4075	// Start with second operand because SMEM Offset cannot be dst or src0.	4075	// Start with second operand because SMEM Offset cannot be dst or src0.
4076	for (unsigned i = 2, e = Operands.size(); i != e; ++i) {	4076	for (unsigned i = 2, e = Operands.size(); i != e; ++i) {
4077	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	4077	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4078	if (Op.isSMEMOffset() \|\| Op.isSMEMOffsetMod())	4078	if (Op.isSMEMOffset() \|\| Op.isSMEMOffsetMod())
4079	return Op.getStartLoc();	4079	return Op.getStartLoc();
4080	}	4080	}
4081	return getLoc();	4081	return getLoc();
4082	}	4082	}
4083		4083
4084	bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,	4084	bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,
4085	const OperandVector &Operands) {	4085	const OperandVector &Operands) {
4086	if (isCI() \|\| isSI())	4086	if (isCI() \|\| isSI())
4087	return true;	4087	return true;
4088		4088
4089	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	4089	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
4090	if ((TSFlags & SIInstrFlags::SMRD) == 0)	4090	if ((TSFlags & SIInstrFlags::SMRD) == 0)
4091	return true;	4091	return true;
4092		4092
4093	auto Opcode = Inst.getOpcode();	4093	auto Opcode = Inst.getOpcode();
4094	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	4094	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);
4095	if (OpNum == -1)	4095	if (OpNum == -1)
4096	return true;	4096	return true;
4097		4097
4098	const auto &Op = Inst.getOperand(OpNum);	4098	const auto &Op = Inst.getOperand(OpNum);
4099	if (!Op.isImm())	4099	if (!Op.isImm())
4100	return true;	4100	return true;
4101		4101
4102	uint64_t Offset = Op.getImm();	4102	uint64_t Offset = Op.getImm();
4103	bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode);	4103	bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode);
4104	if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) \|\|	4104	if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) \|\|
4105	AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer))	4105	AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer))
4106	return true;	4106	return true;
4107		4107
4108	Error(getSMEMOffsetLoc(Operands),	4108	Error(getSMEMOffsetLoc(Operands),
4109	(isVI() \|\| IsBuffer) ? "expected a 20-bit unsigned offset" :	4109	(isVI() \|\| IsBuffer) ? "expected a 20-bit unsigned offset" :
4110	"expected a 21-bit signed offset");	4110	"expected a 21-bit signed offset");
4111		4111
4112	return false;	4112	return false;
4113	}	4113	}
4114		4114
4115	bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {	4115	bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {
4116	unsigned Opcode = Inst.getOpcode();	4116	unsigned Opcode = Inst.getOpcode();
4117	const MCInstrDesc &Desc = MII.get(Opcode);	4117	const MCInstrDesc &Desc = MII.get(Opcode);
4118	if (!(Desc.TSFlags & (SIInstrFlags::SOP2 \| SIInstrFlags::SOPC)))	4118	if (!(Desc.TSFlags & (SIInstrFlags::SOP2 \| SIInstrFlags::SOPC)))
4119	return true;	4119	return true;
4120		4120
4121	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);	4121	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
4122	const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);	4122	const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
4123		4123
4124	const int OpIndices[] = { Src0Idx, Src1Idx };	4124	const int OpIndices[] = { Src0Idx, Src1Idx };
4125		4125
4126	unsigned NumExprs = 0;	4126	unsigned NumExprs = 0;
4127	unsigned NumLiterals = 0;	4127	unsigned NumLiterals = 0;
4128	uint32_t LiteralValue;	4128	uint32_t LiteralValue;
4129		4129
4130	for (int OpIdx : OpIndices) {	4130	for (int OpIdx : OpIndices) {
4131	if (OpIdx == -1) break;	4131	if (OpIdx == -1) break;
4132		4132
4133	const MCOperand &MO = Inst.getOperand(OpIdx);	4133	const MCOperand &MO = Inst.getOperand(OpIdx);
4134	// Exclude special imm operands (like that used by s_set_gpr_idx_on)	4134	// Exclude special imm operands (like that used by s_set_gpr_idx_on)
4135	if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {	4135	if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {
4136	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	4136	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {
4137	uint32_t Value = static_cast(MO.getImm());	4137	uint32_t Value = static_cast(MO.getImm());
4138	if (NumLiterals == 0 \|\| LiteralValue != Value) {	4138	if (NumLiterals == 0 \|\| LiteralValue != Value) {
4139	LiteralValue = Value;	4139	LiteralValue = Value;
4140	++NumLiterals;	4140	++NumLiterals;
4141	}	4141	}
4142	} else if (MO.isExpr()) {	4142	} else if (MO.isExpr()) {
4143	++NumExprs;	4143	++NumExprs;
4144	}	4144	}
4145	}	4145	}
4146	}	4146	}
4147		4147
4148	return NumLiterals + NumExprs <= 1;	4148	return NumLiterals + NumExprs <= 1;
4149	}	4149	}
4150		4150
4151	bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {	4151	bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {
4152	const unsigned Opc = Inst.getOpcode();	4152	const unsigned Opc = Inst.getOpcode();
4153	if (isPermlane16(Opc)) {	4153	if (isPermlane16(Opc)) {
4154	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	4154	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
4155	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	4155	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
4156		4156
4157	if (OpSel & ~3)	4157	if (OpSel & ~3)
4158	return false;	4158	return false;
4159	}	4159	}
4160		4160
4161	uint64_t TSFlags = MII.get(Opc).TSFlags;	4161	uint64_t TSFlags = MII.get(Opc).TSFlags;
4162		4162
4163	if (isGFX940() && (TSFlags & SIInstrFlags::IsDOT)) {	4163	if (isGFX940() && (TSFlags & SIInstrFlags::IsDOT)) {
4164	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	4164	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
4165	if (OpSelIdx != -1) {	4165	if (OpSelIdx != -1) {
4166	if (Inst.getOperand(OpSelIdx).getImm() != 0)	4166	if (Inst.getOperand(OpSelIdx).getImm() != 0)
4167	return false;	4167	return false;
4168	}	4168	}
4169	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	4169	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
4170	if (OpSelHiIdx != -1) {	4170	if (OpSelHiIdx != -1) {
4171	if (Inst.getOperand(OpSelHiIdx).getImm() != -1)	4171	if (Inst.getOperand(OpSelHiIdx).getImm() != -1)
4172	return false;	4172	return false;
4173	}	4173	}
4174	}	4174	}
4175		4175
4176	// op_sel[0:1] must be 0 for v_dot2_bf16_bf16 and v_dot2_f16_f16 (VOP3 Dot).	4176	// op_sel[0:1] must be 0 for v_dot2_bf16_bf16 and v_dot2_f16_f16 (VOP3 Dot).
4177	if (isGFX11Plus() && (TSFlags & SIInstrFlags::IsDOT) &&	4177	if (isGFX11Plus() && (TSFlags & SIInstrFlags::IsDOT) &&
4178	(TSFlags & SIInstrFlags::VOP3) && !(TSFlags & SIInstrFlags::VOP3P)) {	4178	(TSFlags & SIInstrFlags::VOP3) && !(TSFlags & SIInstrFlags::VOP3P)) {
4179	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	4179	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
4180	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	4180	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
4181	if (OpSel & 3)	4181	if (OpSel & 3)
4182	return false;	4182	return false;
4183	}	4183	}
4184		4184
4185	return true;	4185	return true;
4186	}	4186	}
4187		4187
4188	bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,	4188	bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,
4189	const OperandVector &Operands) {	4189	const OperandVector &Operands) {
4190	const unsigned Opc = Inst.getOpcode();	4190	const unsigned Opc = Inst.getOpcode();
4191	int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl);	4191	int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl);
4192	if (DppCtrlIdx < 0)	4192	if (DppCtrlIdx < 0)
4193	return true;	4193	return true;
4194	unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();	4194	unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();
4195		4195
4196	if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {	4196	if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {
4197	// DPP64 is supported for row_newbcast only.	4197	// DPP64 is supported for row_newbcast only.
4198	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	4198	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
4199	if (Src0Idx >= 0 &&	4199	if (Src0Idx >= 0 &&
4200	getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) {	4200	getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) {
4201	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);	4201	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);
4202	Error(S, "64 bit dpp only supports row_newbcast");	4202	Error(S, "64 bit dpp only supports row_newbcast");
4203	return false;	4203	return false;
4204	}	4204	}
4205	}	4205	}
4206		4206
4207	return true;	4207	return true;
4208	}	4208	}
4209		4209
4210	// Check if VCC register matches wavefront size	4210	// Check if VCC register matches wavefront size
4211	bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {	4211	bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {
4212	auto FB = getFeatureBits();	4212	auto FB = getFeatureBits();
4213	return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) \|\|	4213	return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) \|\|
4214	(FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);	4214	(FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);
4215	}	4215	}
4216		4216
4217	// One unique literal can be used. VOP3 literal is only allowed in GFX10+	4217	// One unique literal can be used. VOP3 literal is only allowed in GFX10+
4218	bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,	4218	bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,
4219	const OperandVector &Operands) {	4219	const OperandVector &Operands) {
4220	unsigned Opcode = Inst.getOpcode();	4220	unsigned Opcode = Inst.getOpcode();
4221	const MCInstrDesc &Desc = MII.get(Opcode);	4221	const MCInstrDesc &Desc = MII.get(Opcode);
4222	bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1;	4222	bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1;
4223	if (!(Desc.TSFlags & (SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P)) &&	4223	if (!(Desc.TSFlags & (SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P)) &&
4224	!HasMandatoryLiteral && !isVOPD(Opcode))	4224	!HasMandatoryLiteral && !isVOPD(Opcode))
4225	return true;	4225	return true;
4226		4226
4227	OperandIndices OpIndices = getSrcOperandIndices(Opcode, HasMandatoryLiteral);	4227	OperandIndices OpIndices = getSrcOperandIndices(Opcode, HasMandatoryLiteral);
4228		4228
4229	unsigned NumExprs = 0;	4229	unsigned NumExprs = 0;
4230	unsigned NumLiterals = 0;	4230	unsigned NumLiterals = 0;
4231	uint32_t LiteralValue;	4231	uint32_t LiteralValue;
4232		4232
4233	for (int OpIdx : OpIndices) {	4233	for (int OpIdx : OpIndices) {
4234	if (OpIdx == -1)	4234	if (OpIdx == -1)
4235	continue;	4235	continue;
4236		4236
4237	const MCOperand &MO = Inst.getOperand(OpIdx);	4237	const MCOperand &MO = Inst.getOperand(OpIdx);
4238	if (!MO.isImm() && !MO.isExpr())	4238	if (!MO.isImm() && !MO.isExpr())
4239	continue;	4239	continue;
4240	if (!isSISrcOperand(Desc, OpIdx))	4240	if (!isSISrcOperand(Desc, OpIdx))
4241	continue;	4241	continue;
4242		4242
4243	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	4243	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {
4244	uint32_t Value = static_cast(MO.getImm());	4244	uint32_t Value = static_cast(MO.getImm());
4245	if (NumLiterals == 0 \|\| LiteralValue != Value) {	4245	if (NumLiterals == 0 \|\| LiteralValue != Value) {
4246	LiteralValue = Value;	4246	LiteralValue = Value;
4247	++NumLiterals;	4247	++NumLiterals;
4248	}	4248	}
4249	} else if (MO.isExpr()) {	4249	} else if (MO.isExpr()) {
4250	++NumExprs;	4250	++NumExprs;
4251	}	4251	}
4252	}	4252	}
4253	NumLiterals += NumExprs;	4253	NumLiterals += NumExprs;
4254		4254
4255	if (!NumLiterals)	4255	if (!NumLiterals)
4256	return true;	4256	return true;
4257		4257
4258	if (!HasMandatoryLiteral && !getFeatureBits()[FeatureVOP3Literal]) {	4258	if (!HasMandatoryLiteral && !getFeatureBits()[FeatureVOP3Literal]) {
4259	Error(getLitLoc(Operands), "literal operands are not supported");	4259	Error(getLitLoc(Operands), "literal operands are not supported");
4260	return false;	4260	return false;
4261	}	4261	}
4262		4262
4263	if (NumLiterals > 1) {	4263	if (NumLiterals > 1) {
4264	Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");	4264	Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");
4265	return false;	4265	return false;
4266	}	4266	}
4267		4267
4268	return true;	4268	return true;
4269	}	4269	}
4270		4270
4271	// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.	4271	// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.
4272	static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,	4272	static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,
4273	const MCRegisterInfo *MRI) {	4273	const MCRegisterInfo *MRI) {
4274	int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);	4274	int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);
4275	if (OpIdx < 0)	4275	if (OpIdx < 0)
4276	return -1;	4276	return -1;
4277		4277
4278	const MCOperand &Op = Inst.getOperand(OpIdx);	4278	const MCOperand &Op = Inst.getOperand(OpIdx);
4279	if (!Op.isReg())	4279	if (!Op.isReg())
4280	return -1;	4280	return -1;
4281		4281
4282	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	4282	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
4283	auto Reg = Sub ? Sub : Op.getReg();	4283	auto Reg = Sub ? Sub : Op.getReg();
4284	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	4284	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
4285	return AGPR32.contains(Reg) ? 1 : 0;	4285	return AGPR32.contains(Reg) ? 1 : 0;
4286	}	4286	}
4287		4287
4288	bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {	4288	bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {
4289	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	4289	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
4290	if ((TSFlags & (SIInstrFlags::FLAT \| SIInstrFlags::MUBUF \|	4290	if ((TSFlags & (SIInstrFlags::FLAT \| SIInstrFlags::MUBUF \|
4291	SIInstrFlags::MTBUF \| SIInstrFlags::MIMG \|	4291	SIInstrFlags::MTBUF \| SIInstrFlags::MIMG \|
4292	SIInstrFlags::DS)) == 0)	4292	SIInstrFlags::DS)) == 0)
4293	return true;	4293	return true;
4294		4294
4295	uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0	4295	uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
4296	: AMDGPU::OpName::vdata;	4296	: AMDGPU::OpName::vdata;
4297		4297
4298	const MCRegisterInfo *MRI = getMRI();	4298	const MCRegisterInfo *MRI = getMRI();
4299	int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);	4299	int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);
4300	int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);	4300	int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);
4301		4301
4302	if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {	4302	if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {
4303	int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);	4303	int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);
4304	if (Data2Areg >= 0 && Data2Areg != DataAreg)	4304	if (Data2Areg >= 0 && Data2Areg != DataAreg)
4305	return false;	4305	return false;
4306	}	4306	}
4307		4307
4308	auto FB = getFeatureBits();	4308	auto FB = getFeatureBits();
4309	if (FB[AMDGPU::FeatureGFX90AInsts]) {	4309	if (FB[AMDGPU::FeatureGFX90AInsts]) {
4310	if (DataAreg < 0 \|\| DstAreg < 0)	4310	if (DataAreg < 0 \|\| DstAreg < 0)
4311	return true;	4311	return true;
4312	return DstAreg == DataAreg;	4312	return DstAreg == DataAreg;
4313	}	4313	}
4314		4314
4315	return DstAreg < 1 && DataAreg < 1;	4315	return DstAreg < 1 && DataAreg < 1;
4316	}	4316	}
4317		4317
4318	bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {	4318	bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {
4319	auto FB = getFeatureBits();	4319	auto FB = getFeatureBits();
4320	if (!FB[AMDGPU::FeatureGFX90AInsts])	4320	if (!FB[AMDGPU::FeatureGFX90AInsts])
4321	return true;	4321	return true;
4322		4322
4323	const MCRegisterInfo *MRI = getMRI();	4323	const MCRegisterInfo *MRI = getMRI();
4324	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	4324	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
4325	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	4325	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);
4326	for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {	4326	for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {
4327	const MCOperand &Op = Inst.getOperand(I);	4327	const MCOperand &Op = Inst.getOperand(I);
4328	if (!Op.isReg())	4328	if (!Op.isReg())
4329	continue;	4329	continue;
4330		4330
4331	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	4331	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);
4332	if (!Sub)	4332	if (!Sub)
4333	continue;	4333	continue;
4334		4334
4335	if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))	4335	if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))
4336	return false;	4336	return false;
4337	if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))	4337	if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))
4338	return false;	4338	return false;
4339	}	4339	}
4340		4340
4341	return true;	4341	return true;
4342	}	4342	}
4343		4343
4344	SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {	4344	SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {
4345	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	4345	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
4346	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	4346	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
4347	if (Op.isBLGP())	4347	if (Op.isBLGP())
4348	return Op.getStartLoc();	4348	return Op.getStartLoc();
4349	}	4349	}
4350	return SMLoc();	4350	return SMLoc();
4351	}	4351	}
4352		4352
4353	bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,	4353	bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,
4354	const OperandVector &Operands) {	4354	const OperandVector &Operands) {
4355	unsigned Opc = Inst.getOpcode();	4355	unsigned Opc = Inst.getOpcode();
4356	int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp);	4356	int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp);
4357	if (BlgpIdx == -1)	4357	if (BlgpIdx == -1)
4358	return true;	4358	return true;
4359	SMLoc BLGPLoc = getBLGPLoc(Operands);	4359	SMLoc BLGPLoc = getBLGPLoc(Operands);
4360	if (!BLGPLoc.isValid())	4360	if (!BLGPLoc.isValid())
4361	return true;	4361	return true;
4362	bool IsNeg = StringRef(BLGPLoc.getPointer()).startswith("neg:");	4362	bool IsNeg = StringRef(BLGPLoc.getPointer()).startswith("neg:");
4363	auto FB = getFeatureBits();	4363	auto FB = getFeatureBits();
4364	bool UsesNeg = false;	4364	bool UsesNeg = false;
4365	if (FB[AMDGPU::FeatureGFX940Insts]) {	4365	if (FB[AMDGPU::FeatureGFX940Insts]) {
4366	switch (Opc) {	4366	switch (Opc) {
4367	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:	4367	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:
4368	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:	4368	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:
4369	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:	4369	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:
4370	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:	4370	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:
4371	UsesNeg = true;	4371	UsesNeg = true;
4372	}	4372	}
4373	}	4373	}
4374		4374
4375	if (IsNeg == UsesNeg)	4375	if (IsNeg == UsesNeg)
4376	return true;	4376	return true;
4377		4377
4378	Error(BLGPLoc,	4378	Error(BLGPLoc,
4379	UsesNeg ? "invalid modifier: blgp is not supported"	4379	UsesNeg ? "invalid modifier: blgp is not supported"
4380	: "invalid modifier: neg is not supported");	4380	: "invalid modifier: neg is not supported");
4381		4381
4382	return false;	4382	return false;
4383	}	4383	}
4384		4384
4385	bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,	4385	bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,
4386	const OperandVector &Operands) {	4386	const OperandVector &Operands) {
4387	if (!isGFX11Plus())	4387	if (!isGFX11Plus())
4388	return true;	4388	return true;
4389		4389
4390	unsigned Opc = Inst.getOpcode();	4390	unsigned Opc = Inst.getOpcode();
4391	if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 &&	4391	if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 &&
4392	Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 &&	4392	Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 &&
4393	Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 &&	4393	Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 &&
4394	Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11)	4394	Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11)
4395	return true;	4395	return true;
4396		4396
4397	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);	4397	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);
4398	assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());	4398	assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());
4399	auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());	4399	auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());
4400	if (Reg == AMDGPU::SGPR_NULL)	4400	if (Reg == AMDGPU::SGPR_NULL)
4401	return true;	4401	return true;
4402		4402
4403	SMLoc RegLoc = getRegLoc(Reg, Operands);	4403	SMLoc RegLoc = getRegLoc(Reg, Operands);
4404	Error(RegLoc, "src0 must be null");	4404	Error(RegLoc, "src0 must be null");
4405	return false;	4405	return false;
4406	}	4406	}
4407		4407
4408	// gfx90a has an undocumented limitation:	4408	// gfx90a has an undocumented limitation:
4409	// DS_GWS opcodes must use even aligned registers.	4409	// DS_GWS opcodes must use even aligned registers.
4410	bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,	4410	bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,
4411	const OperandVector &Operands) {	4411	const OperandVector &Operands) {
4412	if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])	4412	if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])
4413	return true;	4413	return true;
4414		4414
4415	int Opc = Inst.getOpcode();	4415	int Opc = Inst.getOpcode();
4416	if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&	4416	if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&
4417	Opc != AMDGPU::DS_GWS_SEMA_BR_vi)	4417	Opc != AMDGPU::DS_GWS_SEMA_BR_vi)
4418	return true;	4418	return true;
4419		4419
4420	const MCRegisterInfo *MRI = getMRI();	4420	const MCRegisterInfo *MRI = getMRI();
4421	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	4421	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);
4422	int Data0Pos =	4422	int Data0Pos =
4423	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);	4423	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);
4424	assert(Data0Pos != -1);	4424	assert(Data0Pos != -1);
4425	auto Reg = Inst.getOperand(Data0Pos).getReg();	4425	auto Reg = Inst.getOperand(Data0Pos).getReg();
4426	auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);	4426	auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);
4427	if (RegIdx & 1) {	4427	if (RegIdx & 1) {
4428	SMLoc RegLoc = getRegLoc(Reg, Operands);	4428	SMLoc RegLoc = getRegLoc(Reg, Operands);
4429	Error(RegLoc, "vgpr must be even aligned");	4429	Error(RegLoc, "vgpr must be even aligned");
4430	return false;	4430	return false;
4431	}	4431	}
4432		4432
4433	return true;	4433	return true;
4434	}	4434	}
4435		4435
4436	bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,	4436	bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,
4437	const OperandVector &Operands,	4437	const OperandVector &Operands,
4438	const SMLoc &IDLoc) {	4438	const SMLoc &IDLoc) {
4439	int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),	4439	int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
4440	AMDGPU::OpName::cpol);	4440	AMDGPU::OpName::cpol);
4441	if (CPolPos == -1)	4441	if (CPolPos == -1)
4442	return true;	4442	return true;
4443		4443
4444	unsigned CPol = Inst.getOperand(CPolPos).getImm();	4444	unsigned CPol = Inst.getOperand(CPolPos).getImm();
4445		4445
4446	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	4446	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
4447	if (TSFlags & SIInstrFlags::SMRD) {	4447	if (TSFlags & SIInstrFlags::SMRD) {
4448	if (CPol && (isSI() \|\| isCI())) {	4448	if (CPol && (isSI() \|\| isCI())) {
4449	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	4449	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
4450	Error(S, "cache policy is not supported for SMRD instructions");	4450	Error(S, "cache policy is not supported for SMRD instructions");
4451	return false;	4451	return false;
4452	}	4452	}
4453	if (CPol & ~(AMDGPU::CPol::GLC \| AMDGPU::CPol::DLC)) {	4453	if (CPol & ~(AMDGPU::CPol::GLC \| AMDGPU::CPol::DLC)) {
4454	Error(IDLoc, "invalid cache policy for SMEM instruction");	4454	Error(IDLoc, "invalid cache policy for SMEM instruction");
4455	return false;	4455	return false;
4456	}	4456	}
4457	}	4457	}
4458		4458
4459	if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {	4459	if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {
4460	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	4460	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
4461	StringRef CStr(S.getPointer());	4461	StringRef CStr(S.getPointer());
4462	S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);	4462	S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);
4463	Error(S, "scc is not supported on this GPU");	4463	Error(S, "scc is not supported on this GPU");
4464	return false;	4464	return false;
4465	}	4465	}
4466		4466
4467	if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet \| SIInstrFlags::IsAtomicRet)))	4467	if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet \| SIInstrFlags::IsAtomicRet)))
4468	return true;	4468	return true;
4469		4469
4470	if (TSFlags & SIInstrFlags::IsAtomicRet) {	4470	if (TSFlags & SIInstrFlags::IsAtomicRet) {
4471	if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {	4471	if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {
4472	Error(IDLoc, isGFX940() ? "instruction must use sc0"	4472	Error(IDLoc, isGFX940() ? "instruction must use sc0"
4473	: "instruction must use glc");	4473	: "instruction must use glc");
4474	return false;	4474	return false;
4475	}	4475	}
4476	} else {	4476	} else {
4477	if (CPol & CPol::GLC) {	4477	if (CPol & CPol::GLC) {
4478	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	4478	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);
4479	StringRef CStr(S.getPointer());	4479	StringRef CStr(S.getPointer());
4480	S = SMLoc::getFromPointer(	4480	S = SMLoc::getFromPointer(
4481	&CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]);	4481	&CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]);
4482	Error(S, isGFX940() ? "instruction must not use sc0"	4482	Error(S, isGFX940() ? "instruction must not use sc0"
4483	: "instruction must not use glc");	4483	: "instruction must not use glc");
4484	return false;	4484	return false;
4485	}	4485	}
4486	}	4486	}
4487		4487
4488	return true;	4488	return true;
4489	}	4489	}
4490		4490
4491	bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {	4491	bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {
4492	if (!isGFX11Plus())	4492	if (!isGFX11Plus())
4493	return true;	4493	return true;
4494	for (auto &Operand : Operands) {	4494	for (auto &Operand : Operands) {
4495	if (!Operand->isReg())	4495	if (!Operand->isReg())
4496	continue;	4496	continue;
4497	unsigned Reg = Operand->getReg();	4497	unsigned Reg = Operand->getReg();
4498	if (Reg == SRC_EXECZ \|\| Reg == SRC_VCCZ) {	4498	if (Reg == SRC_EXECZ \|\| Reg == SRC_VCCZ) {
4499	Error(getRegLoc(Reg, Operands),	4499	Error(getRegLoc(Reg, Operands),
4500	"execz and vccz are not supported on this GPU");	4500	"execz and vccz are not supported on this GPU");
4501	return false;	4501	return false;
4502	}	4502	}
4503	}	4503	}
4504	return true;	4504	return true;
4505	}	4505	}
4506		4506
4507	bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,	4507	bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,
4508	const OperandVector &Operands) {	4508	const OperandVector &Operands) {
4509	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	4509	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
4510	if (Desc.mayStore() &&	4510	if (Desc.mayStore() &&
4511	(Desc.TSFlags & (SIInstrFlags::MUBUF \| SIInstrFlags::MTBUF))) {	4511	(Desc.TSFlags & (SIInstrFlags::MUBUF \| SIInstrFlags::MTBUF))) {
4512	SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);	4512	SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);
4513	if (Loc != getInstLoc(Operands)) {	4513	if (Loc != getInstLoc(Operands)) {
4514	Error(Loc, "TFE modifier has no meaning for store instructions");	4514	Error(Loc, "TFE modifier has no meaning for store instructions");
4515	return false;	4515	return false;
4516	}	4516	}
4517	}	4517	}
4518		4518
4519	return true;	4519	return true;
4520	}	4520	}
4521		4521
4522	bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,	4522	bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,
4523	const SMLoc &IDLoc,	4523	const SMLoc &IDLoc,
4524	const OperandVector &Operands) {	4524	const OperandVector &Operands) {
4525	if (auto ErrMsg = validateLdsDirect(Inst)) {	4525	if (auto ErrMsg = validateLdsDirect(Inst)) {
4526	Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);	4526	Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);
4527	return false;	4527	return false;
4528	}	4528	}
4529	if (!validateSOPLiteral(Inst)) {	4529	if (!validateSOPLiteral(Inst)) {
4530	Error(getLitLoc(Operands),	4530	Error(getLitLoc(Operands),
4531	"only one unique literal operand is allowed");	4531	"only one unique literal operand is allowed");
4532	return false;	4532	return false;
4533	}	4533	}
4534	if (!validateVOPLiteral(Inst, Operands)) {	4534	if (!validateVOPLiteral(Inst, Operands)) {
4535	return false;	4535	return false;
4536	}	4536	}
4537	if (!validateConstantBusLimitations(Inst, Operands)) {	4537	if (!validateConstantBusLimitations(Inst, Operands)) {
4538	return false;	4538	return false;
4539	}	4539	}
4540	if (!validateVOPDRegBankConstraints(Inst, Operands)) {	4540	if (!validateVOPDRegBankConstraints(Inst, Operands)) {
4541	return false;	4541	return false;
4542	}	4542	}
4543	if (!validateIntClampSupported(Inst)) {	4543	if (!validateIntClampSupported(Inst)) {
4544	Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),	4544	Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),
4545	"integer clamping is not supported on this GPU");	4545	"integer clamping is not supported on this GPU");
4546	return false;	4546	return false;
4547	}	4547	}
4548	if (!validateOpSel(Inst)) {	4548	if (!validateOpSel(Inst)) {
4549	Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),	4549	Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),
4550	"invalid op_sel operand");	4550	"invalid op_sel operand");
4551	return false;	4551	return false;
4552	}	4552	}
4553	if (!validateDPP(Inst, Operands)) {	4553	if (!validateDPP(Inst, Operands)) {
4554	return false;	4554	return false;
4555	}	4555	}
4556	// For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.	4556	// For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.
4557	if (!validateMIMGD16(Inst)) {	4557	if (!validateMIMGD16(Inst)) {
4558	Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),	4558	Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),
4559	"d16 modifier is not supported on this GPU");	4559	"d16 modifier is not supported on this GPU");
4560	return false;	4560	return false;
4561	}	4561	}
4562	if (!validateMIMGMSAA(Inst)) {	4562	if (!validateMIMGMSAA(Inst)) {
4563	Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),	4563	Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),
4564	"invalid dim; must be MSAA type");	4564	"invalid dim; must be MSAA type");
4565	return false;	4565	return false;
4566	}	4566	}
4567	if (!validateMIMGDataSize(Inst, IDLoc)) {	4567	if (!validateMIMGDataSize(Inst, IDLoc)) {
4568	return false;	4568	return false;
4569	}	4569	}
4570	if (!validateMIMGAddrSize(Inst, IDLoc))	4570	if (!validateMIMGAddrSize(Inst, IDLoc))
4571	return false;	4571	return false;
4572	if (!validateMIMGAtomicDMask(Inst)) {	4572	if (!validateMIMGAtomicDMask(Inst)) {
4573	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	4573	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
4574	"invalid atomic image dmask");	4574	"invalid atomic image dmask");
4575	return false;	4575	return false;
4576	}	4576	}
4577	if (!validateMIMGGatherDMask(Inst)) {	4577	if (!validateMIMGGatherDMask(Inst)) {
4578	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	4578	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),
4579	"invalid image_gather dmask: only one bit must be set");	4579	"invalid image_gather dmask: only one bit must be set");
4580	return false;	4580	return false;
4581	}	4581	}
4582	if (!validateMovrels(Inst, Operands)) {	4582	if (!validateMovrels(Inst, Operands)) {
4583	return false;	4583	return false;
4584	}	4584	}
4585	if (!validateFlatOffset(Inst, Operands)) {	4585	if (!validateFlatOffset(Inst, Operands)) {
4586	return false;	4586	return false;
4587	}	4587	}
4588	if (!validateSMEMOffset(Inst, Operands)) {	4588	if (!validateSMEMOffset(Inst, Operands)) {
4589	return false;	4589	return false;
4590	}	4590	}
4591	if (!validateMAIAccWrite(Inst, Operands)) {	4591	if (!validateMAIAccWrite(Inst, Operands)) {
4592	return false;	4592	return false;
4593	}	4593	}
4594	if (!validateMAISrc2(Inst, Operands)) {	4594	if (!validateMAISrc2(Inst, Operands)) {
4595	return false;	4595	return false;
4596	}	4596	}
4597	if (!validateMFMA(Inst, Operands)) {	4597	if (!validateMFMA(Inst, Operands)) {
4598	return false;	4598	return false;
4599	}	4599	}
4600	if (!validateCoherencyBits(Inst, Operands, IDLoc)) {	4600	if (!validateCoherencyBits(Inst, Operands, IDLoc)) {
4601	return false;	4601	return false;
4602	}	4602	}
4603		4603
4604	if (!validateAGPRLdSt(Inst)) {	4604	if (!validateAGPRLdSt(Inst)) {
4605	Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]	4605	Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]
4606	? "invalid register class: data and dst should be all VGPR or AGPR"	4606	? "invalid register class: data and dst should be all VGPR or AGPR"
4607	: "invalid register class: agpr loads and stores not supported on this GPU"	4607	: "invalid register class: agpr loads and stores not supported on this GPU"
4608	);	4608	);
4609	return false;	4609	return false;
4610	}	4610	}
4611	if (!validateVGPRAlign(Inst)) {	4611	if (!validateVGPRAlign(Inst)) {
4612	Error(IDLoc,	4612	Error(IDLoc,
4613	"invalid register class: vgpr tuples must be 64 bit aligned");	4613	"invalid register class: vgpr tuples must be 64 bit aligned");
4614	return false;	4614	return false;
4615	}	4615	}
4616	if (!validateGWS(Inst, Operands)) {	4616	if (!validateGWS(Inst, Operands)) {
4617	return false;	4617	return false;
4618	}	4618	}
4619		4619
4620	if (!validateBLGP(Inst, Operands)) {	4620	if (!validateBLGP(Inst, Operands)) {
4621	return false;	4621	return false;
4622	}	4622	}
4623		4623
4624	if (!validateDivScale(Inst)) {	4624	if (!validateDivScale(Inst)) {
4625	Error(IDLoc, "ABS not allowed in VOP3B instructions");	4625	Error(IDLoc, "ABS not allowed in VOP3B instructions");
4626	return false;	4626	return false;
4627	}	4627	}
4628	if (!validateWaitCnt(Inst, Operands)) {	4628	if (!validateWaitCnt(Inst, Operands)) {
4629	return false;	4629	return false;
4630	}	4630	}
4631	if (!validateExeczVcczOperands(Operands)) {	4631	if (!validateExeczVcczOperands(Operands)) {
4632	return false;	4632	return false;
4633	}	4633	}
4634	if (!validateTFE(Inst, Operands)) {	4634	if (!validateTFE(Inst, Operands)) {
4635	return false;	4635	return false;
4636	}	4636	}
4637		4637
4638	return true;	4638	return true;
4639	}	4639	}
4640		4640
4641	static std::string AMDGPUMnemonicSpellCheck(StringRef S,	4641	static std::string AMDGPUMnemonicSpellCheck(StringRef S,
4642	const FeatureBitset &FBS,	4642	const FeatureBitset &FBS,
4643	unsigned VariantID = 0);	4643	unsigned VariantID = 0);
4644		4644
4645	static bool AMDGPUCheckMnemonic(StringRef Mnemonic,	4645	static bool AMDGPUCheckMnemonic(StringRef Mnemonic,
4646	const FeatureBitset &AvailableFeatures,	4646	const FeatureBitset &AvailableFeatures,
4647	unsigned VariantID);	4647	unsigned VariantID);
4648		4648
4649	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	4649	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
4650	const FeatureBitset &FBS) {	4650	const FeatureBitset &FBS) {
4651	return isSupportedMnemo(Mnemo, FBS, getAllVariants());	4651	return isSupportedMnemo(Mnemo, FBS, getAllVariants());
4652	}	4652	}
4653		4653
4654	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	4654	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,
4655	const FeatureBitset &FBS,	4655	const FeatureBitset &FBS,
4656	ArrayRef Variants) {	4656	ArrayRef Variants) {
4657	for (auto Variant : Variants) {	4657	for (auto Variant : Variants) {
4658	if (AMDGPUCheckMnemonic(Mnemo, FBS, Variant))	4658	if (AMDGPUCheckMnemonic(Mnemo, FBS, Variant))
4659	return true;	4659	return true;
4660	}	4660	}
4661		4661
4662	return false;	4662	return false;
4663	}	4663	}
4664		4664
4665	bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,	4665	bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,
4666	const SMLoc &IDLoc) {	4666	const SMLoc &IDLoc) {
4667	FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());	4667	FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());
4668		4668
4669	// Check if requested instruction variant is supported.	4669	// Check if requested instruction variant is supported.
4670	if (isSupportedMnemo(Mnemo, FBS, getMatchedVariants()))	4670	if (isSupportedMnemo(Mnemo, FBS, getMatchedVariants()))
4671	return false;	4671	return false;
4672		4672
4673	// This instruction is not supported.	4673	// This instruction is not supported.
4674	// Clear any other pending errors because they are no longer relevant.	4674	// Clear any other pending errors because they are no longer relevant.
4675	getParser().clearPendingErrors();	4675	getParser().clearPendingErrors();
4676		4676
4677	// Requested instruction variant is not supported.	4677	// Requested instruction variant is not supported.
4678	// Check if any other variants are supported.	4678	// Check if any other variants are supported.
4679	StringRef VariantName = getMatchedVariantName();	4679	StringRef VariantName = getMatchedVariantName();
4680	if (!VariantName.empty() && isSupportedMnemo(Mnemo, FBS)) {	4680	if (!VariantName.empty() && isSupportedMnemo(Mnemo, FBS)) {
4681	return Error(IDLoc,	4681	return Error(IDLoc,
4682	Twine(VariantName,	4682	Twine(VariantName,
4683	" variant of this instruction is not supported"));	4683	" variant of this instruction is not supported"));
4684	}	4684	}
4685		4685
4686	// Check if this instruction may be used with a different wavesize.	4686	// Check if this instruction may be used with a different wavesize.
4687	if (isGFX10Plus() && getFeatureBits()[AMDGPU::FeatureWavefrontSize64] &&	4687	if (isGFX10Plus() && getFeatureBits()[AMDGPU::FeatureWavefrontSize64] &&
4688	!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) {	4688	!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) {
4689		4689
4690	FeatureBitset FeaturesWS32 = getFeatureBits();	4690	FeatureBitset FeaturesWS32 = getFeatureBits();
4691	FeaturesWS32.flip(AMDGPU::FeatureWavefrontSize64)	4691	FeaturesWS32.flip(AMDGPU::FeatureWavefrontSize64)
4692	.flip(AMDGPU::FeatureWavefrontSize32);	4692	.flip(AMDGPU::FeatureWavefrontSize32);
4693	FeatureBitset AvailableFeaturesWS32 =	4693	FeatureBitset AvailableFeaturesWS32 =
4694	ComputeAvailableFeatures(FeaturesWS32);	4694	ComputeAvailableFeatures(FeaturesWS32);
4695		4695
4696	if (isSupportedMnemo(Mnemo, AvailableFeaturesWS32, getMatchedVariants()))	4696	if (isSupportedMnemo(Mnemo, AvailableFeaturesWS32, getMatchedVariants()))
4697	return Error(IDLoc, "instruction requires wavesize=32");	4697	return Error(IDLoc, "instruction requires wavesize=32");
4698	}	4698	}
4699		4699
4700	// Finally check if this instruction is supported on any other GPU.	4700	// Finally check if this instruction is supported on any other GPU.
4701	if (isSupportedMnemo(Mnemo, FeatureBitset().set())) {	4701	if (isSupportedMnemo(Mnemo, FeatureBitset().set())) {
4702	return Error(IDLoc, "instruction not supported on this GPU");	4702	return Error(IDLoc, "instruction not supported on this GPU");
4703	}	4703	}
4704		4704
4705	// Instruction not supported on any GPU. Probably a typo.	4705	// Instruction not supported on any GPU. Probably a typo.
4706	std::string Suggestion = AMDGPUMnemonicSpellCheck(Mnemo, FBS);	4706	std::string Suggestion = AMDGPUMnemonicSpellCheck(Mnemo, FBS);
4707	return Error(IDLoc, "invalid instruction" + Suggestion);	4707	return Error(IDLoc, "invalid instruction" + Suggestion);
4708	}	4708	}
4709		4709
4710	static bool isInvalidVOPDY(const OperandVector &Operands,	4710	static bool isInvalidVOPDY(const OperandVector &Operands,
4711	uint64_t InvalidOprIdx) {	4711	uint64_t InvalidOprIdx) {
4712	assert(InvalidOprIdx < Operands.size());	4712	assert(InvalidOprIdx < Operands.size());
4713	const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);	4713	const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);
4714	if (Op.isToken() && InvalidOprIdx > 1) {	4714	if (Op.isToken() && InvalidOprIdx > 1) {
4715	const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);	4715	const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);
4716	return PrevOp.isToken() && PrevOp.getToken() == "::";	4716	return PrevOp.isToken() && PrevOp.getToken() == "::";
4717	}	4717	}
4718	return false;	4718	return false;
4719	}	4719	}
4720		4720
4721	bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	4721	bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
4722	OperandVector &Operands,	4722	OperandVector &Operands,
4723	MCStreamer &Out,	4723	MCStreamer &Out,
4724	uint64_t &ErrorInfo,	4724	uint64_t &ErrorInfo,
4725	bool MatchingInlineAsm) {	4725	bool MatchingInlineAsm) {
4726	MCInst Inst;	4726	MCInst Inst;
4727	unsigned Result = Match_Success;	4727	unsigned Result = Match_Success;
4728	for (auto Variant : getMatchedVariants()) {	4728	for (auto Variant : getMatchedVariants()) {
4729	uint64_t EI;	4729	uint64_t EI;
4730	auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,	4730	auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
4731	Variant);	4731	Variant);
4732	// We order match statuses from least to most specific. We use most specific	4732	// We order match statuses from least to most specific. We use most specific
4733	// status as resulting	4733	// status as resulting
4734	// Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32	4734	// Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32
4735	if ((R == Match_Success) \|\|	4735	if ((R == Match_Success) \|\|
4736	(R == Match_PreferE32) \|\|	4736	(R == Match_PreferE32) \|\|
4737	(R == Match_MissingFeature && Result != Match_PreferE32) \|\|	4737	(R == Match_MissingFeature && Result != Match_PreferE32) \|\|
4738	(R == Match_InvalidOperand && Result != Match_MissingFeature	4738	(R == Match_InvalidOperand && Result != Match_MissingFeature
4739	&& Result != Match_PreferE32) \|\|	4739	&& Result != Match_PreferE32) \|\|
4740	(R == Match_MnemonicFail && Result != Match_InvalidOperand	4740	(R == Match_MnemonicFail && Result != Match_InvalidOperand
4741	&& Result != Match_MissingFeature	4741	&& Result != Match_MissingFeature
4742	&& Result != Match_PreferE32)) {	4742	&& Result != Match_PreferE32)) {
4743	Result = R;	4743	Result = R;
4744	ErrorInfo = EI;	4744	ErrorInfo = EI;
4745	}	4745	}
4746	if (R == Match_Success)	4746	if (R == Match_Success)
4747	break;	4747	break;
4748	}	4748	}
4749		4749
4750	if (Result == Match_Success) {	4750	if (Result == Match_Success) {
4751	if (!validateInstruction(Inst, IDLoc, Operands)) {	4751	if (!validateInstruction(Inst, IDLoc, Operands)) {
4752	return true;	4752	return true;
4753	}	4753	}
4754	Inst.setLoc(IDLoc);	4754	Inst.setLoc(IDLoc);
4755	Out.emitInstruction(Inst, getSTI());	4755	Out.emitInstruction(Inst, getSTI());
4756	return false;	4756	return false;
4757	}	4757	}
4758		4758
4759	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	4759	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
4760	if (checkUnsupportedInstruction(Mnemo, IDLoc)) {	4760	if (checkUnsupportedInstruction(Mnemo, IDLoc)) {
4761	return true;	4761	return true;
4762	}	4762	}
4763		4763
4764	switch (Result) {	4764	switch (Result) {
4765	default: break;	4765	default: break;
4766	case Match_MissingFeature:	4766	case Match_MissingFeature:
4767	// It has been verified that the specified instruction	4767	// It has been verified that the specified instruction
4768	// mnemonic is valid. A match was found but it requires	4768	// mnemonic is valid. A match was found but it requires
4769	// features which are not supported on this GPU.	4769	// features which are not supported on this GPU.
4770	return Error(IDLoc, "operands are not valid for this GPU or mode");	4770	return Error(IDLoc, "operands are not valid for this GPU or mode");
4771		4771
4772	case Match_InvalidOperand: {	4772	case Match_InvalidOperand: {
4773	SMLoc ErrorLoc = IDLoc;	4773	SMLoc ErrorLoc = IDLoc;
4774	if (ErrorInfo != ~0ULL) {	4774	if (ErrorInfo != ~0ULL) {
4775	if (ErrorInfo >= Operands.size()) {	4775	if (ErrorInfo >= Operands.size()) {
4776	return Error(IDLoc, "too few operands for instruction");	4776	return Error(IDLoc, "too few operands for instruction");
4777	}	4777	}
4778	ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();	4778	ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();
4779	if (ErrorLoc == SMLoc())	4779	if (ErrorLoc == SMLoc())
4780	ErrorLoc = IDLoc;	4780	ErrorLoc = IDLoc;
4781		4781
4782	if (isInvalidVOPDY(Operands, ErrorInfo))	4782	if (isInvalidVOPDY(Operands, ErrorInfo))
4783	return Error(ErrorLoc, "invalid VOPDY instruction");	4783	return Error(ErrorLoc, "invalid VOPDY instruction");
4784	}	4784	}
4785	return Error(ErrorLoc, "invalid operand for instruction");	4785	return Error(ErrorLoc, "invalid operand for instruction");
4786	}	4786	}
4787		4787
4788	case Match_PreferE32:	4788	case Match_PreferE32:
4789	return Error(IDLoc, "internal error: instruction without _e64 suffix "	4789	return Error(IDLoc, "internal error: instruction without _e64 suffix "
4790	"should be encoded as e32");	4790	"should be encoded as e32");
4791	case Match_MnemonicFail:	4791	case Match_MnemonicFail:
4792	llvm_unreachable("Invalid instructions should have been handled already");	4792	llvm_unreachable("Invalid instructions should have been handled already");
4793	}	4793	}
4794	llvm_unreachable("Implement any new match types added!");	4794	llvm_unreachable("Implement any new match types added!");
4795	}	4795	}
4796		4796
4797	bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {	4797	bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {
4798	int64_t Tmp = -1;	4798	int64_t Tmp = -1;
4799	if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {	4799	if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {
4800	return true;	4800	return true;
4801	}	4801	}
4802	if (getParser().parseAbsoluteExpression(Tmp)) {	4802	if (getParser().parseAbsoluteExpression(Tmp)) {
4803	return true;	4803	return true;
4804	}	4804	}
4805	Ret = static_cast(Tmp);	4805	Ret = static_cast(Tmp);
4806	return false;	4806	return false;
4807	}	4807	}
4808		4808
4809	bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,	4809	bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,
4810	uint32_t &Minor) {	4810	uint32_t &Minor) {
4811	if (ParseAsAbsoluteExpression(Major))	4811	if (ParseAsAbsoluteExpression(Major))
4812	return TokError("invalid major version");	4812	return TokError("invalid major version");
4813		4813
4814	if (!trySkipToken(AsmToken::Comma))	4814	if (!trySkipToken(AsmToken::Comma))
4815	return TokError("minor version number required, comma expected");	4815	return TokError("minor version number required, comma expected");
4816		4816
4817	if (ParseAsAbsoluteExpression(Minor))	4817	if (ParseAsAbsoluteExpression(Minor))
4818	return TokError("invalid minor version");	4818	return TokError("invalid minor version");
4819		4819
4820	return false;	4820	return false;
4821	}	4821	}
4822		4822
4823	bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {	4823	bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {
4824	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	4824	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
4825	return TokError("directive only supported for amdgcn architecture");	4825	return TokError("directive only supported for amdgcn architecture");
4826		4826
4827	std::string TargetIDDirective;	4827	std::string TargetIDDirective;
4828	SMLoc TargetStart = getTok().getLoc();	4828	SMLoc TargetStart = getTok().getLoc();
4829	if (getParser().parseEscapedString(TargetIDDirective))	4829	if (getParser().parseEscapedString(TargetIDDirective))
4830	return true;	4830	return true;
4831		4831
4832	SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());	4832	SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());
4833	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	4833	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
4834	return getParser().Error(TargetRange.Start,	4834	return getParser().Error(TargetRange.Start,
4835	(Twine(".amdgcn_target directive's target id ") +	4835	(Twine(".amdgcn_target directive's target id ") +
4836	Twine(TargetIDDirective) +	4836	Twine(TargetIDDirective) +
4837	Twine(" does not match the specified target id ") +	4837	Twine(" does not match the specified target id ") +
4838	Twine(getTargetStreamer().getTargetID()->toString())).str());	4838	Twine(getTargetStreamer().getTargetID()->toString())).str());
4839		4839
4840	return false;	4840	return false;
4841	}	4841	}
4842		4842
4843	bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {	4843	bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {
4844	return Error(Range.Start, "value out of range", Range);	4844	return Error(Range.Start, "value out of range", Range);
4845	}	4845	}
4846		4846
4847	bool AMDGPUAsmParser::calculateGPRBlocks(	4847	bool AMDGPUAsmParser::calculateGPRBlocks(
4848	const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,	4848	const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,
4849	bool XNACKUsed, std::optional EnableWavefrontSize32,	4849	bool XNACKUsed, std::optional EnableWavefrontSize32,
4850	unsigned NextFreeVGPR, SMRange VGPRRange, unsigned NextFreeSGPR,	4850	unsigned NextFreeVGPR, SMRange VGPRRange, unsigned NextFreeSGPR,
4851	SMRange SGPRRange, unsigned &VGPRBlocks, unsigned &SGPRBlocks) {	4851	SMRange SGPRRange, unsigned &VGPRBlocks, unsigned &SGPRBlocks) {
4852	// TODO(scott.linder): These calculations are duplicated from	4852	// TODO(scott.linder): These calculations are duplicated from
4853	// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.	4853	// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.
4854	IsaVersion Version = getIsaVersion(getSTI().getCPU());	4854	IsaVersion Version = getIsaVersion(getSTI().getCPU());
4855		4855
4856	unsigned NumVGPRs = NextFreeVGPR;	4856	unsigned NumVGPRs = NextFreeVGPR;
4857	unsigned NumSGPRs = NextFreeSGPR;	4857	unsigned NumSGPRs = NextFreeSGPR;
4858		4858
4859	if (Version.Major >= 10)	4859	if (Version.Major >= 10)
4860	NumSGPRs = 0;	4860	NumSGPRs = 0;
4861	else {	4861	else {
4862	unsigned MaxAddressableNumSGPRs =	4862	unsigned MaxAddressableNumSGPRs =
4863	IsaInfo::getAddressableNumSGPRs(&getSTI());	4863	IsaInfo::getAddressableNumSGPRs(&getSTI());
4864		4864
4865	if (Version.Major >= 8 && !Features.test(FeatureSGPRInitBug) &&	4865	if (Version.Major >= 8 && !Features.test(FeatureSGPRInitBug) &&
4866	NumSGPRs > MaxAddressableNumSGPRs)	4866	NumSGPRs > MaxAddressableNumSGPRs)
4867	return OutOfRangeError(SGPRRange);	4867	return OutOfRangeError(SGPRRange);
4868		4868
4869	NumSGPRs +=	4869	NumSGPRs +=
4870	IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);	4870	IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);
4871		4871
4872	if ((Version.Major <= 7 \|\| Features.test(FeatureSGPRInitBug)) &&	4872	if ((Version.Major <= 7 \|\| Features.test(FeatureSGPRInitBug)) &&
4873	NumSGPRs > MaxAddressableNumSGPRs)	4873	NumSGPRs > MaxAddressableNumSGPRs)
4874	return OutOfRangeError(SGPRRange);	4874	return OutOfRangeError(SGPRRange);
4875		4875
4876	if (Features.test(FeatureSGPRInitBug))	4876	if (Features.test(FeatureSGPRInitBug))
4877	NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;	4877	NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;
4878	}	4878	}
4879		4879
4880	VGPRBlocks =	4880	VGPRBlocks =
4881	IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);	4881	IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);
4882	SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);	4882	SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);
4883		4883
4884	return false;	4884	return false;
4885	}	4885	}
4886		4886
4887	bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {	4887	bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {
4888	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	4888	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)
4889	return TokError("directive only supported for amdgcn architecture");	4889	return TokError("directive only supported for amdgcn architecture");
4890		4890
4891	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)	4891	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)
4892	return TokError("directive only supported for amdhsa OS");	4892	return TokError("directive only supported for amdhsa OS");
4893		4893
4894	StringRef KernelName;	4894	StringRef KernelName;
4895	if (getParser().parseIdentifier(KernelName))	4895	if (getParser().parseIdentifier(KernelName))
4896	return true;	4896	return true;
4897		4897
4898	kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());	4898	kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());
4899		4899
4900	StringSet<> Seen;	4900	StringSet<> Seen;
4901		4901
4902	IsaVersion IVersion = getIsaVersion(getSTI().getCPU());	4902	IsaVersion IVersion = getIsaVersion(getSTI().getCPU());
4903		4903
4904	SMRange VGPRRange;	4904	SMRange VGPRRange;
4905	uint64_t NextFreeVGPR = 0;	4905	uint64_t NextFreeVGPR = 0;
4906	uint64_t AccumOffset = 0;	4906	uint64_t AccumOffset = 0;
4907	uint64_t SharedVGPRCount = 0;	4907	uint64_t SharedVGPRCount = 0;
4908	SMRange SGPRRange;	4908	SMRange SGPRRange;
4909	uint64_t NextFreeSGPR = 0;	4909	uint64_t NextFreeSGPR = 0;
4910		4910
4911	// Count the number of user SGPRs implied from the enabled feature bits.	4911	// Count the number of user SGPRs implied from the enabled feature bits.
4912	unsigned ImpliedUserSGPRCount = 0;	4912	unsigned ImpliedUserSGPRCount = 0;
4913		4913
4914	// Track if the asm explicitly contains the directive for the user SGPR	4914	// Track if the asm explicitly contains the directive for the user SGPR
4915	// count.	4915	// count.
4916	std::optional ExplicitUserSGPRCount;	4916	std::optional ExplicitUserSGPRCount;
4917	bool ReserveVCC = true;	4917	bool ReserveVCC = true;
4918	bool ReserveFlatScr = true;	4918	bool ReserveFlatScr = true;
4919	std::optional EnableWavefrontSize32;	4919	std::optional EnableWavefrontSize32;
4920		4920
4921	while (true) {	4921	while (true) {
4922	while (trySkipToken(AsmToken::EndOfStatement));	4922	while (trySkipToken(AsmToken::EndOfStatement));
4923		4923
4924	StringRef ID;	4924	StringRef ID;
4925	SMRange IDRange = getTok().getLocRange();	4925	SMRange IDRange = getTok().getLocRange();
4926	if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))	4926	if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))
4927	return true;	4927	return true;
4928		4928
4929	if (ID == ".end_amdhsa_kernel")	4929	if (ID == ".end_amdhsa_kernel")
4930	break;	4930	break;
4931		4931
4932	if (!Seen.insert(ID).second)	4932	if (!Seen.insert(ID).second)
4933	return TokError(".amdhsa_ directives cannot be repeated");	4933	return TokError(".amdhsa_ directives cannot be repeated");
4934		4934
4935	SMLoc ValStart = getLoc();	4935	SMLoc ValStart = getLoc();
4936	int64_t IVal;	4936	int64_t IVal;
4937	if (getParser().parseAbsoluteExpression(IVal))	4937	if (getParser().parseAbsoluteExpression(IVal))
4938	return true;	4938	return true;
4939	SMLoc ValEnd = getLoc();	4939	SMLoc ValEnd = getLoc();
4940	SMRange ValRange = SMRange(ValStart, ValEnd);	4940	SMRange ValRange = SMRange(ValStart, ValEnd);
4941		4941
4942	if (IVal < 0)	4942	if (IVal < 0)
4943	return OutOfRangeError(ValRange);	4943	return OutOfRangeError(ValRange);
4944		4944
4945	uint64_t Val = IVal;	4945	uint64_t Val = IVal;
4946		4946
4947	#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE) \	4947	#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE) \
4948	if (!isUInt(VALUE)) \	4948	if (!isUInt(VALUE)) \
4949	return OutOfRangeError(RANGE); \	4949	return OutOfRangeError(RANGE); \
4950	AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);	4950	AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);
4951		4951
4952	if (ID == ".amdhsa_group_segment_fixed_size") {	4952	if (ID == ".amdhsa_group_segment_fixed_size") {
4953	if (!isUInt(Val))	4953	if (!isUInt(Val))
4954	return OutOfRangeError(ValRange);	4954	return OutOfRangeError(ValRange);
4955	KD.group_segment_fixed_size = Val;	4955	KD.group_segment_fixed_size = Val;
4956	} else if (ID == ".amdhsa_private_segment_fixed_size") {	4956	} else if (ID == ".amdhsa_private_segment_fixed_size") {
4957	if (!isUInt(Val))	4957	if (!isUInt(Val))
4958	return OutOfRangeError(ValRange);	4958	return OutOfRangeError(ValRange);
4959	KD.private_segment_fixed_size = Val;	4959	KD.private_segment_fixed_size = Val;
4960	} else if (ID == ".amdhsa_kernarg_size") {	4960	} else if (ID == ".amdhsa_kernarg_size") {
4961	if (!isUInt(Val))	4961	if (!isUInt(Val))
4962	return OutOfRangeError(ValRange);	4962	return OutOfRangeError(ValRange);
4963	KD.kernarg_size = Val;	4963	KD.kernarg_size = Val;
4964	} else if (ID == ".amdhsa_user_sgpr_count") {	4964	} else if (ID == ".amdhsa_user_sgpr_count") {
4965	ExplicitUserSGPRCount = Val;	4965	ExplicitUserSGPRCount = Val;
4966	} else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {	4966	} else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {
4967	if (hasArchitectedFlatScratch())	4967	if (hasArchitectedFlatScratch())
4968	return Error(IDRange.Start,	4968	return Error(IDRange.Start,
4969	"directive is not supported with architected flat scratch",	4969	"directive is not supported with architected flat scratch",
4970	IDRange);	4970	IDRange);
4971	PARSE_BITS_ENTRY(KD.kernel_code_properties,	4971	PARSE_BITS_ENTRY(KD.kernel_code_properties,
4972	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,	4972	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
4973	Val, ValRange);	4973	Val, ValRange);
4974	if (Val)	4974	if (Val)
4975	ImpliedUserSGPRCount += 4;	4975	ImpliedUserSGPRCount += 4;
4976	} else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {	4976	} else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {
4977	PARSE_BITS_ENTRY(KD.kernel_code_properties,	4977	PARSE_BITS_ENTRY(KD.kernel_code_properties,
4978	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,	4978	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,
4979	ValRange);	4979	ValRange);
4980	if (Val)	4980	if (Val)
4981	ImpliedUserSGPRCount += 2;	4981	ImpliedUserSGPRCount += 2;
4982	} else if (ID == ".amdhsa_user_sgpr_queue_ptr") {	4982	} else if (ID == ".amdhsa_user_sgpr_queue_ptr") {
4983	PARSE_BITS_ENTRY(KD.kernel_code_properties,	4983	PARSE_BITS_ENTRY(KD.kernel_code_properties,
4984	KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,	4984	KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,
4985	ValRange);	4985	ValRange);
4986	if (Val)	4986	if (Val)
4987	ImpliedUserSGPRCount += 2;	4987	ImpliedUserSGPRCount += 2;
4988	} else if (ID == ".amdhsa_user_sgpr_kernarg_segment_ptr") {	4988	} else if (ID == ".amdhsa_user_sgpr_kernarg_segment_ptr") {
4989	PARSE_BITS_ENTRY(KD.kernel_code_properties,	4989	PARSE_BITS_ENTRY(KD.kernel_code_properties,
4990	KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,	4990	KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
4991	Val, ValRange);	4991	Val, ValRange);
4992	if (Val)	4992	if (Val)
4993	ImpliedUserSGPRCount += 2;	4993	ImpliedUserSGPRCount += 2;
4994	} else if (ID == ".amdhsa_user_sgpr_dispatch_id") {	4994	} else if (ID == ".amdhsa_user_sgpr_dispatch_id") {
4995	PARSE_BITS_ENTRY(KD.kernel_code_properties,	4995	PARSE_BITS_ENTRY(KD.kernel_code_properties,
4996	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,	4996	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,
4997	ValRange);	4997	ValRange);
4998	if (Val)	4998	if (Val)
4999	ImpliedUserSGPRCount += 2;	4999	ImpliedUserSGPRCount += 2;
5000	} else if (ID == ".amdhsa_user_sgpr_flat_scratch_init") {	5000	} else if (ID == ".amdhsa_user_sgpr_flat_scratch_init") {
5001	if (hasArchitectedFlatScratch())	5001	if (hasArchitectedFlatScratch())
5002	return Error(IDRange.Start,	5002	return Error(IDRange.Start,
5003	"directive is not supported with architected flat scratch",	5003	"directive is not supported with architected flat scratch",
5004	IDRange);	5004	IDRange);
5005	PARSE_BITS_ENTRY(KD.kernel_code_properties,	5005	PARSE_BITS_ENTRY(KD.kernel_code_properties,
5006	KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,	5006	KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,
5007	ValRange);	5007	ValRange);
5008	if (Val)	5008	if (Val)
5009	ImpliedUserSGPRCount += 2;	5009	ImpliedUserSGPRCount += 2;
5010	} else if (ID == ".amdhsa_user_sgpr_private_segment_size") {	5010	} else if (ID == ".amdhsa_user_sgpr_private_segment_size") {
5011	PARSE_BITS_ENTRY(KD.kernel_code_properties,	5011	PARSE_BITS_ENTRY(KD.kernel_code_properties,
5012	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,	5012	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
5013	Val, ValRange);	5013	Val, ValRange);
5014	if (Val)	5014	if (Val)
5015	ImpliedUserSGPRCount += 1;	5015	ImpliedUserSGPRCount += 1;
5016	} else if (ID == ".amdhsa_wavefront_size32") {	5016	} else if (ID == ".amdhsa_wavefront_size32") {
5017	if (IVersion.Major < 10)	5017	if (IVersion.Major < 10)
5018	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	5018	return Error(IDRange.Start, "directive requires gfx10+", IDRange);
5019	EnableWavefrontSize32 = Val;	5019	EnableWavefrontSize32 = Val;
5020	PARSE_BITS_ENTRY(KD.kernel_code_properties,	5020	PARSE_BITS_ENTRY(KD.kernel_code_properties,
5021	KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,	5021	KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
5022	Val, ValRange);	5022	Val, ValRange);
5023	} else if (ID == ".amdhsa_uses_dynamic_stack") {	5023	} else if (ID == ".amdhsa_uses_dynamic_stack") {
5024	PARSE_BITS_ENTRY(KD.kernel_code_properties,	5024	PARSE_BITS_ENTRY(KD.kernel_code_properties,
5025	KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, Val, ValRange);	5025	KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, Val, ValRange);
5026	} else if (ID == ".amdhsa_system_sgpr_private_segment_wavefront_offset") {	5026	} else if (ID == ".amdhsa_system_sgpr_private_segment_wavefront_offset") {
5027	if (hasArchitectedFlatScratch())	5027	if (hasArchitectedFlatScratch())
5028	return Error(IDRange.Start,	5028	return Error(IDRange.Start,
5029	"directive is not supported with architected flat scratch",	5029	"directive is not supported with architected flat scratch",
5030	IDRange);	5030	IDRange);
5031	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5031	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5032	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	5032	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);
5033	} else if (ID == ".amdhsa_enable_private_segment") {	5033	} else if (ID == ".amdhsa_enable_private_segment") {
5034	if (!hasArchitectedFlatScratch())	5034	if (!hasArchitectedFlatScratch())
5035	return Error(	5035	return Error(
5036	IDRange.Start,	5036	IDRange.Start,
5037	"directive is not supported without architected flat scratch",	5037	"directive is not supported without architected flat scratch",
5038	IDRange);	5038	IDRange);
5039	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5039	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5040	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	5040	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);
5041	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_x") {	5041	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_x") {
5042	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5042	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5043	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,	5043	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,
5044	ValRange);	5044	ValRange);
5045	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_y") {	5045	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_y") {
5046	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5046	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5047	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,	5047	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,
5048	ValRange);	5048	ValRange);
5049	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_z") {	5049	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_z") {
5050	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5050	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5051	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,	5051	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,
5052	ValRange);	5052	ValRange);
5053	} else if (ID == ".amdhsa_system_sgpr_workgroup_info") {	5053	} else if (ID == ".amdhsa_system_sgpr_workgroup_info") {
5054	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5054	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5055	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,	5055	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,
5056	ValRange);	5056	ValRange);
5057	} else if (ID == ".amdhsa_system_vgpr_workitem_id") {	5057	} else if (ID == ".amdhsa_system_vgpr_workitem_id") {
5058	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5058	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5059	COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,	5059	COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,
5060	ValRange);	5060	ValRange);
5061	} else if (ID == ".amdhsa_next_free_vgpr") {	5061	} else if (ID == ".amdhsa_next_free_vgpr") {
5062	VGPRRange = ValRange;	5062	VGPRRange = ValRange;
5063	NextFreeVGPR = Val;	5063	NextFreeVGPR = Val;
5064	} else if (ID == ".amdhsa_next_free_sgpr") {	5064	} else if (ID == ".amdhsa_next_free_sgpr") {
5065	SGPRRange = ValRange;	5065	SGPRRange = ValRange;
5066	NextFreeSGPR = Val;	5066	NextFreeSGPR = Val;
5067	} else if (ID == ".amdhsa_accum_offset") {	5067	} else if (ID == ".amdhsa_accum_offset") {
5068	if (!isGFX90A())	5068	if (!isGFX90A())
5069	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	5069	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);
5070	AccumOffset = Val;	5070	AccumOffset = Val;
5071	} else if (ID == ".amdhsa_reserve_vcc") {	5071	} else if (ID == ".amdhsa_reserve_vcc") {
5072	if (!isUInt<1>(Val))	5072	if (!isUInt<1>(Val))
5073	return OutOfRangeError(ValRange);	5073	return OutOfRangeError(ValRange);
5074	ReserveVCC = Val;	5074	ReserveVCC = Val;
5075	} else if (ID == ".amdhsa_reserve_flat_scratch") {	5075	} else if (ID == ".amdhsa_reserve_flat_scratch") {
5076	if (IVersion.Major < 7)	5076	if (IVersion.Major < 7)
5077	return Error(IDRange.Start, "directive requires gfx7+", IDRange);	5077	return Error(IDRange.Start, "directive requires gfx7+", IDRange);
5078	if (hasArchitectedFlatScratch())	5078	if (hasArchitectedFlatScratch())
5079	return Error(IDRange.Start,	5079	return Error(IDRange.Start,
5080	"directive is not supported with architected flat scratch",	5080	"directive is not supported with architected flat scratch",
5081	IDRange);	5081	IDRange);
5082	if (!isUInt<1>(Val))	5082	if (!isUInt<1>(Val))
5083	return OutOfRangeError(ValRange);	5083	return OutOfRangeError(ValRange);
5084	ReserveFlatScr = Val;	5084	ReserveFlatScr = Val;
5085	} else if (ID == ".amdhsa_reserve_xnack_mask") {	5085	} else if (ID == ".amdhsa_reserve_xnack_mask") {
5086	if (IVersion.Major < 8)	5086	if (IVersion.Major < 8)
5087	return Error(IDRange.Start, "directive requires gfx8+", IDRange);	5087	return Error(IDRange.Start, "directive requires gfx8+", IDRange);
5088	if (!isUInt<1>(Val))	5088	if (!isUInt<1>(Val))
5089	return OutOfRangeError(ValRange);	5089	return OutOfRangeError(ValRange);
5090	if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())	5090	if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())
5091	return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",	5091	return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",
5092	IDRange);	5092	IDRange);
5093	} else if (ID == ".amdhsa_float_round_mode_32") {	5093	} else if (ID == ".amdhsa_float_round_mode_32") {
5094	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	5094	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
5095	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);	5095	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);
5096	} else if (ID == ".amdhsa_float_round_mode_16_64") {	5096	} else if (ID == ".amdhsa_float_round_mode_16_64") {
5097	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	5097	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
5098	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);	5098	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);
5099	} else if (ID == ".amdhsa_float_denorm_mode_32") {	5099	} else if (ID == ".amdhsa_float_denorm_mode_32") {
5100	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	5100	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
5101	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);	5101	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);
5102	} else if (ID == ".amdhsa_float_denorm_mode_16_64") {	5102	} else if (ID == ".amdhsa_float_denorm_mode_16_64") {
5103	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	5103	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
5104	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,	5104	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,
5105	ValRange);	5105	ValRange);
5106	} else if (ID == ".amdhsa_dx10_clamp") {	5106	} else if (ID == ".amdhsa_dx10_clamp") {
5107	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	5107	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,
5108	COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);	5108	COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);
5109	} else if (ID == ".amdhsa_ieee_mode") {	5109	} else if (ID == ".amdhsa_ieee_mode") {
5110	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,	5110	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,
5111	Val, ValRange);	5111	Val, ValRange);
5112	} else if (ID == ".amdhsa_fp16_overflow") {	5112	} else if (ID == ".amdhsa_fp16_overflow") {
5113	if (IVersion.Major < 9)	5113	if (IVersion.Major < 9)
5114	return Error(IDRange.Start, "directive requires gfx9+", IDRange);	5114	return Error(IDRange.Start, "directive requires gfx9+", IDRange);
5115	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,	5115	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,
5116	ValRange);	5116	ValRange);
5117	} else if (ID == ".amdhsa_tg_split") {	5117	} else if (ID == ".amdhsa_tg_split") {
5118	if (!isGFX90A())	5118	if (!isGFX90A())
5119	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	5119	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);
5120	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Val,	5120	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Val,
5121	ValRange);	5121	ValRange);
5122	} else if (ID == ".amdhsa_workgroup_processor_mode") {	5122	} else if (ID == ".amdhsa_workgroup_processor_mode") {
5123	if (IVersion.Major < 10)	5123	if (IVersion.Major < 10)
5124	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	5124	return Error(IDRange.Start, "directive requires gfx10+", IDRange);
5125	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,	5125	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,
5126	ValRange);	5126	ValRange);
5127	} else if (ID == ".amdhsa_memory_ordered") {	5127	} else if (ID == ".amdhsa_memory_ordered") {
5128	if (IVersion.Major < 10)	5128	if (IVersion.Major < 10)
5129	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	5129	return Error(IDRange.Start, "directive requires gfx10+", IDRange);
5130	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,	5130	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,
5131	ValRange);	5131	ValRange);
5132	} else if (ID == ".amdhsa_forward_progress") {	5132	} else if (ID == ".amdhsa_forward_progress") {
5133	if (IVersion.Major < 10)	5133	if (IVersion.Major < 10)
5134	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	5134	return Error(IDRange.Start, "directive requires gfx10+", IDRange);
5135	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,	5135	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,
5136	ValRange);	5136	ValRange);
5137	} else if (ID == ".amdhsa_shared_vgpr_count") {	5137	} else if (ID == ".amdhsa_shared_vgpr_count") {
5138	if (IVersion.Major < 10)	5138	if (IVersion.Major < 10)
5139	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	5139	return Error(IDRange.Start, "directive requires gfx10+", IDRange);
5140	SharedVGPRCount = Val;	5140	SharedVGPRCount = Val;
5141	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3,	5141	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3,
5142	COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, Val,	5142	COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, Val,
5143	ValRange);	5143	ValRange);
5144	} else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {	5144	} else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {
5145	PARSE_BITS_ENTRY(	5145	PARSE_BITS_ENTRY(
5146	KD.compute_pgm_rsrc2,	5146	KD.compute_pgm_rsrc2,
5147	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,	5147	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,
5148	ValRange);	5148	ValRange);
5149	} else if (ID == ".amdhsa_exception_fp_denorm_src") {	5149	} else if (ID == ".amdhsa_exception_fp_denorm_src") {
5150	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5150	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5151	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,	5151	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
5152	Val, ValRange);	5152	Val, ValRange);
5153	} else if (ID == ".amdhsa_exception_fp_ieee_div_zero") {	5153	} else if (ID == ".amdhsa_exception_fp_ieee_div_zero") {
5154	PARSE_BITS_ENTRY(	5154	PARSE_BITS_ENTRY(
5155	KD.compute_pgm_rsrc2,	5155	KD.compute_pgm_rsrc2,
5156	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,	5156	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,
5157	ValRange);	5157	ValRange);
5158	} else if (ID == ".amdhsa_exception_fp_ieee_overflow") {	5158	} else if (ID == ".amdhsa_exception_fp_ieee_overflow") {
5159	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5159	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5160	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,	5160	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
5161	Val, ValRange);	5161	Val, ValRange);
5162	} else if (ID == ".amdhsa_exception_fp_ieee_underflow") {	5162	} else if (ID == ".amdhsa_exception_fp_ieee_underflow") {
5163	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5163	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5164	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,	5164	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
5165	Val, ValRange);	5165	Val, ValRange);
5166	} else if (ID == ".amdhsa_exception_fp_ieee_inexact") {	5166	} else if (ID == ".amdhsa_exception_fp_ieee_inexact") {
5167	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5167	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5168	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,	5168	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
5169	Val, ValRange);	5169	Val, ValRange);
5170	} else if (ID == ".amdhsa_exception_int_div_zero") {	5170	} else if (ID == ".amdhsa_exception_int_div_zero") {
5171	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	5171	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,
5172	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,	5172	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
5173	Val, ValRange);	5173	Val, ValRange);
5174	} else {	5174	} else {
5175	return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange);	5175	return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange);
5176	}	5176	}
5177		5177
5178	#undef PARSE_BITS_ENTRY	5178	#undef PARSE_BITS_ENTRY
5179	}	5179	}
5180		5180
5181	if (!Seen.contains(".amdhsa_next_free_vgpr"))	5181	if (!Seen.contains(".amdhsa_next_free_vgpr"))
5182	return TokError(".amdhsa_next_free_vgpr directive is required");	5182	return TokError(".amdhsa_next_free_vgpr directive is required");
5183		5183
5184	if (!Seen.contains(".amdhsa_next_free_sgpr"))	5184	if (!Seen.contains(".amdhsa_next_free_sgpr"))
5185	return TokError(".amdhsa_next_free_sgpr directive is required");	5185	return TokError(".amdhsa_next_free_sgpr directive is required");
5186		5186
5187	unsigned VGPRBlocks;	5187	unsigned VGPRBlocks;
5188	unsigned SGPRBlocks;	5188	unsigned SGPRBlocks;
5189	if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,	5189	if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,
5190	getTargetStreamer().getTargetID()->isXnackOnOrAny(),	5190	getTargetStreamer().getTargetID()->isXnackOnOrAny(),
5191	EnableWavefrontSize32, NextFreeVGPR,	5191	EnableWavefrontSize32, NextFreeVGPR,
5192	VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,	5192	VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,
5193	SGPRBlocks))	5193	SGPRBlocks))
5194	return true;	5194	return true;
5195		5195
5196	if (!isUInt(	5196	if (!isUInt(
5197	VGPRBlocks))	5197	VGPRBlocks))
5198	return OutOfRangeError(VGPRRange);	5198	return OutOfRangeError(VGPRRange);
5199	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	5199	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
5200	COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, VGPRBlocks);	5200	COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, VGPRBlocks);
5201		5201
5202	if (!isUInt(	5202	if (!isUInt(
5203	SGPRBlocks))	5203	SGPRBlocks))
5204	return OutOfRangeError(SGPRRange);	5204	return OutOfRangeError(SGPRRange);
5205	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	5205	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,
5206	COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT,	5206	COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT,
5207	SGPRBlocks);	5207	SGPRBlocks);
5208		5208
5209	if (ExplicitUserSGPRCount && ImpliedUserSGPRCount > *ExplicitUserSGPRCount)	5209	if (ExplicitUserSGPRCount && ImpliedUserSGPRCount > *ExplicitUserSGPRCount)
5210	return TokError("amdgpu_user_sgpr_count smaller than than implied by "	5210	return TokError("amdgpu_user_sgpr_count smaller than than implied by "
5211	"enabled user SGPRs");	5211	"enabled user SGPRs");
5212		5212
5213	unsigned UserSGPRCount =	5213	unsigned UserSGPRCount =
5214	ExplicitUserSGPRCount ? *ExplicitUserSGPRCount : ImpliedUserSGPRCount;	5214	ExplicitUserSGPRCount ? *ExplicitUserSGPRCount : ImpliedUserSGPRCount;
5215		5215
5216	if (!isUInt(UserSGPRCount))	5216	if (!isUInt(UserSGPRCount))
5217	return TokError("too many user SGPRs enabled");	5217	return TokError("too many user SGPRs enabled");
5218	AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,	5218	AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,
5219	UserSGPRCount);	5219	UserSGPRCount);
5220		5220
5221	if (isGFX90A()) {	5221	if (isGFX90A()) {
5222	if (!Seen.contains(".amdhsa_accum_offset"))	5222	if (!Seen.contains(".amdhsa_accum_offset"))
5223	return TokError(".amdhsa_accum_offset directive is required");	5223	return TokError(".amdhsa_accum_offset directive is required");
5224	if (AccumOffset < 4 \|\| AccumOffset > 256 \|\| (AccumOffset & 3))	5224	if (AccumOffset < 4 \|\| AccumOffset > 256 \|\| (AccumOffset & 3))
5225	return TokError("accum_offset should be in range [4..256] in "	5225	return TokError("accum_offset should be in range [4..256] in "
5226	"increments of 4");	5226	"increments of 4");
5227	if (AccumOffset > alignTo(std::max((uint64_t)1, NextFreeVGPR), 4))	5227	if (AccumOffset > alignTo(std::max((uint64_t)1, NextFreeVGPR), 4))
5228	return TokError("accum_offset exceeds total VGPR allocation");	5228	return TokError("accum_offset exceeds total VGPR allocation");
5229	AMDHSA_BITS_SET(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,	5229	AMDHSA_BITS_SET(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,
5230	(AccumOffset / 4 - 1));	5230	(AccumOffset / 4 - 1));
5231	}	5231	}
5232		5232
5233	if (IVersion.Major >= 10) {	5233	if (IVersion.Major >= 10) {
5234	// SharedVGPRCount < 16 checked by PARSE_ENTRY_BITS	5234	// SharedVGPRCount < 16 checked by PARSE_ENTRY_BITS
5235	if (SharedVGPRCount && EnableWavefrontSize32 && *EnableWavefrontSize32) {	5235	if (SharedVGPRCount && EnableWavefrontSize32 && *EnableWavefrontSize32) {
5236	return TokError("shared_vgpr_count directive not valid on "	5236	return TokError("shared_vgpr_count directive not valid on "
5237	"wavefront size 32");	5237	"wavefront size 32");
5238	}	5238	}
5239	if (SharedVGPRCount * 2 + VGPRBlocks > 63) {	5239	if (SharedVGPRCount * 2 + VGPRBlocks > 63) {
5240	return TokError("shared_vgpr_count*2 + "	5240	return TokError("shared_vgpr_count*2 + "
5241	"compute_pgm_rsrc1.GRANULATED_WORKITEM_VGPR_COUNT cannot "	5241	"compute_pgm_rsrc1.GRANULATED_WORKITEM_VGPR_COUNT cannot "
5242	"exceed 63\n");	5242	"exceed 63\n");
5243	}	5243	}
5244	}	5244	}
5245		5245
5246	getTargetStreamer().EmitAmdhsaKernelDescriptor(	5246	getTargetStreamer().EmitAmdhsaKernelDescriptor(
5247	getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,	5247	getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,
5248	ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion());	5248	ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion());
5249	return false;	5249	return false;
5250	}	5250	}
5251		5251
5252	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {	5252	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {
5253	uint32_t Major;	5253	uint32_t Major;
5254	uint32_t Minor;	5254	uint32_t Minor;
5255		5255
5256	if (ParseDirectiveMajorMinor(Major, Minor))	5256	if (ParseDirectiveMajorMinor(Major, Minor))
5257	return true;	5257	return true;
5258		5258
5259	getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);	5259	getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);
5260	return false;	5260	return false;
5261	}	5261	}
5262		5262
5263	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {	5263	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {
5264	uint32_t Major;	5264	uint32_t Major;
5265	uint32_t Minor;	5265	uint32_t Minor;
5266	uint32_t Stepping;	5266	uint32_t Stepping;
5267	StringRef VendorName;	5267	StringRef VendorName;
5268	StringRef ArchName;	5268	StringRef ArchName;
5269		5269
5270	// If this directive has no arguments, then use the ISA version for the	5270	// If this directive has no arguments, then use the ISA version for the
5271	// targeted GPU.	5271	// targeted GPU.
5272	if (isToken(AsmToken::EndOfStatement)) {	5272	if (isToken(AsmToken::EndOfStatement)) {
5273	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	5273	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
5274	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,	5274	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,
5275	ISA.Stepping,	5275	ISA.Stepping,
5276	"AMD", "AMDGPU");	5276	"AMD", "AMDGPU");
5277	return false;	5277	return false;
5278	}	5278	}
5279		5279
5280	if (ParseDirectiveMajorMinor(Major, Minor))	5280	if (ParseDirectiveMajorMinor(Major, Minor))
5281	return true;	5281	return true;
5282		5282
5283	if (!trySkipToken(AsmToken::Comma))	5283	if (!trySkipToken(AsmToken::Comma))
5284	return TokError("stepping version number required, comma expected");	5284	return TokError("stepping version number required, comma expected");
5285		5285
5286	if (ParseAsAbsoluteExpression(Stepping))	5286	if (ParseAsAbsoluteExpression(Stepping))
5287	return TokError("invalid stepping version");	5287	return TokError("invalid stepping version");
5288		5288
5289	if (!trySkipToken(AsmToken::Comma))	5289	if (!trySkipToken(AsmToken::Comma))
5290	return TokError("vendor name required, comma expected");	5290	return TokError("vendor name required, comma expected");
5291		5291
5292	if (!parseString(VendorName, "invalid vendor name"))	5292	if (!parseString(VendorName, "invalid vendor name"))
5293	return true;	5293	return true;
5294		5294
5295	if (!trySkipToken(AsmToken::Comma))	5295	if (!trySkipToken(AsmToken::Comma))
5296	return TokError("arch name required, comma expected");	5296	return TokError("arch name required, comma expected");
5297		5297
5298	if (!parseString(ArchName, "invalid arch name"))	5298	if (!parseString(ArchName, "invalid arch name"))
5299	return true;	5299	return true;
5300		5300
5301	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,	5301	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,
5302	VendorName, ArchName);	5302	VendorName, ArchName);
5303	return false;	5303	return false;
5304	}	5304	}
5305		5305
5306	bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,	5306	bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,
5307	amd_kernel_code_t &Header) {	5307	amd_kernel_code_t &Header) {
5308	// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing	5308	// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing
5309	// assembly for backwards compatibility.	5309	// assembly for backwards compatibility.
5310	if (ID == "max_scratch_backing_memory_byte_size") {	5310	if (ID == "max_scratch_backing_memory_byte_size") {
5311	Parser.eatToEndOfStatement();	5311	Parser.eatToEndOfStatement();
5312	return false;	5312	return false;
5313	}	5313	}
5314		5314
5315	SmallString<40> ErrStr;	5315	SmallString<40> ErrStr;
5316	raw_svector_ostream Err(ErrStr);	5316	raw_svector_ostream Err(ErrStr);
5317	if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {	5317	if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {
5318	return TokError(Err.str());	5318	return TokError(Err.str());
5319	}	5319	}
5320	Lex();	5320	Lex();
5321		5321
5322	if (ID == "enable_wavefront_size32") {	5322	if (ID == "enable_wavefront_size32") {
5323	if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) {	5323	if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) {
5324	if (!isGFX10Plus())	5324	if (!isGFX10Plus())
5325	return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");	5325	return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");
5326	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	5326	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])
5327	return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");	5327	return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");
5328	} else {	5328	} else {
5329	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	5329	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])
5330	return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");	5330	return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");
5331	}	5331	}
5332	}	5332	}
5333		5333
5334	if (ID == "wavefront_size") {	5334	if (ID == "wavefront_size") {
5335	if (Header.wavefront_size == 5) {	5335	if (Header.wavefront_size == 5) {
5336	if (!isGFX10Plus())	5336	if (!isGFX10Plus())
5337	return TokError("wavefront_size=5 is only allowed on GFX10+");	5337	return TokError("wavefront_size=5 is only allowed on GFX10+");
5338	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	5338	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])
5339	return TokError("wavefront_size=5 requires +WavefrontSize32");	5339	return TokError("wavefront_size=5 requires +WavefrontSize32");
5340	} else if (Header.wavefront_size == 6) {	5340	} else if (Header.wavefront_size == 6) {
5341	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	5341	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])
5342	return TokError("wavefront_size=6 requires +WavefrontSize64");	5342	return TokError("wavefront_size=6 requires +WavefrontSize64");
5343	}	5343	}
5344	}	5344	}
5345		5345
5346	if (ID == "enable_wgp_mode") {	5346	if (ID == "enable_wgp_mode") {
5347	if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) &&	5347	if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) &&
5348	!isGFX10Plus())	5348	!isGFX10Plus())
5349	return TokError("enable_wgp_mode=1 is only allowed on GFX10+");	5349	return TokError("enable_wgp_mode=1 is only allowed on GFX10+");
5350	}	5350	}
5351		5351
5352	if (ID == "enable_mem_ordered") {	5352	if (ID == "enable_mem_ordered") {
5353	if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) &&	5353	if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) &&
5354	!isGFX10Plus())	5354	!isGFX10Plus())
5355	return TokError("enable_mem_ordered=1 is only allowed on GFX10+");	5355	return TokError("enable_mem_ordered=1 is only allowed on GFX10+");
5356	}	5356	}
5357		5357
5358	if (ID == "enable_fwd_progress") {	5358	if (ID == "enable_fwd_progress") {
5359	if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) &&	5359	if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) &&
5360	!isGFX10Plus())	5360	!isGFX10Plus())
5361	return TokError("enable_fwd_progress=1 is only allowed on GFX10+");	5361	return TokError("enable_fwd_progress=1 is only allowed on GFX10+");
5362	}	5362	}
5363		5363
5364	return false;	5364	return false;
5365	}	5365	}
5366		5366
5367	bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {	5367	bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
5368	amd_kernel_code_t Header;	5368	amd_kernel_code_t Header;
5369	AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());	5369	AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());
5370		5370
5371	while (true) {	5371	while (true) {
5372	// Lex EndOfStatement. This is in a while loop, because lexing a comment	5372	// Lex EndOfStatement. This is in a while loop, because lexing a comment
5373	// will set the current token to EndOfStatement.	5373	// will set the current token to EndOfStatement.
5374	while(trySkipToken(AsmToken::EndOfStatement));	5374	while(trySkipToken(AsmToken::EndOfStatement));
5375		5375
5376	StringRef ID;	5376	StringRef ID;
5377	if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))	5377	if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))
5378	return true;	5378	return true;
5379		5379
5380	if (ID == ".end_amd_kernel_code_t")	5380	if (ID == ".end_amd_kernel_code_t")
5381	break;	5381	break;
5382		5382
5383	if (ParseAMDKernelCodeTValue(ID, Header))	5383	if (ParseAMDKernelCodeTValue(ID, Header))
5384	return true;	5384	return true;
5385	}	5385	}
5386		5386
5387	getTargetStreamer().EmitAMDKernelCodeT(Header);	5387	getTargetStreamer().EmitAMDKernelCodeT(Header);
5388		5388
5389	return false;	5389	return false;
5390	}	5390	}
5391		5391
5392	bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {	5392	bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {
5393	StringRef KernelName;	5393	StringRef KernelName;
5394	if (!parseId(KernelName, "expected symbol name"))	5394	if (!parseId(KernelName, "expected symbol name"))
5395	return true;	5395	return true;
5396		5396
5397	getTargetStreamer().EmitAMDGPUSymbolType(KernelName,	5397	getTargetStreamer().EmitAMDGPUSymbolType(KernelName,
5398	ELF::STT_AMDGPU_HSA_KERNEL);	5398	ELF::STT_AMDGPU_HSA_KERNEL);
5399		5399
5400	KernelScope.initialize(getContext());	5400	KernelScope.initialize(getContext());
5401	return false;	5401	return false;
5402	}	5402	}
5403		5403
5404	bool AMDGPUAsmParser::ParseDirectiveISAVersion() {	5404	bool AMDGPUAsmParser::ParseDirectiveISAVersion() {
5405	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {	5405	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {
5406	return Error(getLoc(),	5406	return Error(getLoc(),
5407	".amd_amdgpu_isa directive is not available on non-amdgcn "	5407	".amd_amdgpu_isa directive is not available on non-amdgcn "
5408	"architectures");	5408	"architectures");
5409	}	5409	}
5410		5410
5411	auto TargetIDDirective = getLexer().getTok().getStringContents();	5411	auto TargetIDDirective = getLexer().getTok().getStringContents();
5412	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	5412	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)
5413	return Error(getParser().getTok().getLoc(), "target id must match options");	5413	return Error(getParser().getTok().getLoc(), "target id must match options");
5414		5414
5415	getTargetStreamer().EmitISAVersion();	5415	getTargetStreamer().EmitISAVersion();
5416	Lex();	5416	Lex();
5417		5417
5418	return false;	5418	return false;
5419	}	5419	}
5420		5420
5421	bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {	5421	bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {
5422	const char *AssemblerDirectiveBegin;	5422	const char *AssemblerDirectiveBegin;
5423	const char *AssemblerDirectiveEnd;	5423	const char *AssemblerDirectiveEnd;
5424	std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =	5424	std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =
5425	isHsaAbiVersion3AndAbove(&getSTI())	5425	isHsaAbiVersion3AndAbove(&getSTI())
5426	? std::pair(HSAMD::V3::AssemblerDirectiveBegin,	5426	? std::pair(HSAMD::V3::AssemblerDirectiveBegin,
5427	HSAMD::V3::AssemblerDirectiveEnd)	5427	HSAMD::V3::AssemblerDirectiveEnd)
5428	: std::pair(HSAMD::AssemblerDirectiveBegin,	5428	: std::pair(HSAMD::AssemblerDirectiveBegin,
5429	HSAMD::AssemblerDirectiveEnd);	5429	HSAMD::AssemblerDirectiveEnd);
5430		5430
5431	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {	5431	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {
5432	return Error(getLoc(),	5432	return Error(getLoc(),
5433	(Twine(AssemblerDirectiveBegin) + Twine(" directive is "	5433	(Twine(AssemblerDirectiveBegin) + Twine(" directive is "
5434	"not available on non-amdhsa OSes")).str());	5434	"not available on non-amdhsa OSes")).str());
5435	}	5435	}
5436		5436
5437	std::string HSAMetadataString;	5437	std::string HSAMetadataString;
5438	if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,	5438	if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,
5439	HSAMetadataString))	5439	HSAMetadataString))
5440	return true;	5440	return true;
5441		5441
5442	if (isHsaAbiVersion3AndAbove(&getSTI())) {	5442	if (isHsaAbiVersion3AndAbove(&getSTI())) {
5443	if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))	5443	if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))
5444	return Error(getLoc(), "invalid HSA metadata");	5444	return Error(getLoc(), "invalid HSA metadata");
5445	} else {	5445	} else {
5446	if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))	5446	if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))
5447	return Error(getLoc(), "invalid HSA metadata");	5447	return Error(getLoc(), "invalid HSA metadata");
5448	}	5448	}
5449		5449
5450	return false;	5450	return false;
5451	}	5451	}
5452		5452
5453	/// Common code to parse out a block of text (typically YAML) between start and	5453	/// Common code to parse out a block of text (typically YAML) between start and
5454	/// end directives.	5454	/// end directives.
5455	bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,	5455	bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,
5456	const char *AssemblerDirectiveEnd,	5456	const char *AssemblerDirectiveEnd,
5457	std::string &CollectString) {	5457	std::string &CollectString) {
5458		5458
5459	raw_string_ostream CollectStream(CollectString);	5459	raw_string_ostream CollectStream(CollectString);
5460		5460
5461	getLexer().setSkipSpace(false);	5461	getLexer().setSkipSpace(false);
5462		5462
5463	bool FoundEnd = false;	5463	bool FoundEnd = false;
5464	while (!isToken(AsmToken::Eof)) {	5464	while (!isToken(AsmToken::Eof)) {
5465	while (isToken(AsmToken::Space)) {	5465	while (isToken(AsmToken::Space)) {
5466	CollectStream << getTokenStr();	5466	CollectStream << getTokenStr();
5467	Lex();	5467	Lex();
5468	}	5468	}
5469		5469
5470	if (trySkipId(AssemblerDirectiveEnd)) {	5470	if (trySkipId(AssemblerDirectiveEnd)) {
5471	FoundEnd = true;	5471	FoundEnd = true;
5472	break;	5472	break;
5473	}	5473	}
5474		5474
5475	CollectStream << Parser.parseStringToEndOfStatement()	5475	CollectStream << Parser.parseStringToEndOfStatement()
5476	<< getContext().getAsmInfo()->getSeparatorString();	5476	<< getContext().getAsmInfo()->getSeparatorString();
5477		5477
5478	Parser.eatToEndOfStatement();	5478	Parser.eatToEndOfStatement();
5479	}	5479	}
5480		5480
5481	getLexer().setSkipSpace(true);	5481	getLexer().setSkipSpace(true);
5482		5482
5483	if (isToken(AsmToken::Eof) && !FoundEnd) {	5483	if (isToken(AsmToken::Eof) && !FoundEnd) {
5484	return TokError(Twine("expected directive ") +	5484	return TokError(Twine("expected directive ") +
5485	Twine(AssemblerDirectiveEnd) + Twine(" not found"));	5485	Twine(AssemblerDirectiveEnd) + Twine(" not found"));
5486	}	5486	}
5487		5487
5488	CollectStream.flush();	5488	CollectStream.flush();
5489	return false;	5489	return false;
5490	}	5490	}
5491		5491
5492	/// Parse the assembler directive for new MsgPack-format PAL metadata.	5492	/// Parse the assembler directive for new MsgPack-format PAL metadata.
5493	bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {	5493	bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {
5494	std::string String;	5494	std::string String;
5495	if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin,	5495	if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin,
5496	AMDGPU::PALMD::AssemblerDirectiveEnd, String))	5496	AMDGPU::PALMD::AssemblerDirectiveEnd, String))
5497	return true;	5497	return true;
5498		5498
5499	auto PALMetadata = getTargetStreamer().getPALMetadata();	5499	auto PALMetadata = getTargetStreamer().getPALMetadata();
5500	if (!PALMetadata->setFromString(String))	5500	if (!PALMetadata->setFromString(String))
5501	return Error(getLoc(), "invalid PAL metadata");	5501	return Error(getLoc(), "invalid PAL metadata");
5502	return false;	5502	return false;
5503	}	5503	}
5504		5504
5505	/// Parse the assembler directive for old linear-format PAL metadata.	5505	/// Parse the assembler directive for old linear-format PAL metadata.
5506	bool AMDGPUAsmParser::ParseDirectivePALMetadata() {	5506	bool AMDGPUAsmParser::ParseDirectivePALMetadata() {
5507	if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {	5507	if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {
5508	return Error(getLoc(),	5508	return Error(getLoc(),
5509	(Twine(PALMD::AssemblerDirective) + Twine(" directive is "	5509	(Twine(PALMD::AssemblerDirective) + Twine(" directive is "
5510	"not available on non-amdpal OSes")).str());	5510	"not available on non-amdpal OSes")).str());
5511	}	5511	}
5512		5512
5513	auto PALMetadata = getTargetStreamer().getPALMetadata();	5513	auto PALMetadata = getTargetStreamer().getPALMetadata();
5514	PALMetadata->setLegacy();	5514	PALMetadata->setLegacy();
5515	for (;;) {	5515	for (;;) {
5516	uint32_t Key, Value;	5516	uint32_t Key, Value;
5517	if (ParseAsAbsoluteExpression(Key)) {	5517	if (ParseAsAbsoluteExpression(Key)) {
5518	return TokError(Twine("invalid value in ") +	5518	return TokError(Twine("invalid value in ") +
5519	Twine(PALMD::AssemblerDirective));	5519	Twine(PALMD::AssemblerDirective));
5520	}	5520	}
5521	if (!trySkipToken(AsmToken::Comma)) {	5521	if (!trySkipToken(AsmToken::Comma)) {
5522	return TokError(Twine("expected an even number of values in ") +	5522	return TokError(Twine("expected an even number of values in ") +
5523	Twine(PALMD::AssemblerDirective));	5523	Twine(PALMD::AssemblerDirective));
5524	}	5524	}
5525	if (ParseAsAbsoluteExpression(Value)) {	5525	if (ParseAsAbsoluteExpression(Value)) {
5526	return TokError(Twine("invalid value in ") +	5526	return TokError(Twine("invalid value in ") +
5527	Twine(PALMD::AssemblerDirective));	5527	Twine(PALMD::AssemblerDirective));
5528	}	5528	}
5529	PALMetadata->setRegister(Key, Value);	5529	PALMetadata->setRegister(Key, Value);
5530	if (!trySkipToken(AsmToken::Comma))	5530	if (!trySkipToken(AsmToken::Comma))
5531	break;	5531	break;
5532	}	5532	}
5533	return false;	5533	return false;
5534	}	5534	}
5535		5535
5536	/// ParseDirectiveAMDGPULDS	5536	/// ParseDirectiveAMDGPULDS
5537	/// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression]	5537	/// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression]
5538	bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {	5538	bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {
5539	if (getParser().checkForValidSection())	5539	if (getParser().checkForValidSection())
5540	return true;	5540	return true;
5541		5541
5542	StringRef Name;	5542	StringRef Name;
5543	SMLoc NameLoc = getLoc();	5543	SMLoc NameLoc = getLoc();
5544	if (getParser().parseIdentifier(Name))	5544	if (getParser().parseIdentifier(Name))
5545	return TokError("expected identifier in directive");	5545	return TokError("expected identifier in directive");
5546		5546
5547	MCSymbol *Symbol = getContext().getOrCreateSymbol(Name);	5547	MCSymbol *Symbol = getContext().getOrCreateSymbol(Name);
5548	if (getParser().parseComma())	5548	if (getParser().parseComma())
5549	return true;	5549	return true;
5550		5550
5551	unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());	5551	unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());
5552		5552
5553	int64_t Size;	5553	int64_t Size;
5554	SMLoc SizeLoc = getLoc();	5554	SMLoc SizeLoc = getLoc();
5555	if (getParser().parseAbsoluteExpression(Size))	5555	if (getParser().parseAbsoluteExpression(Size))
5556	return true;	5556	return true;
5557	if (Size < 0)	5557	if (Size < 0)
5558	return Error(SizeLoc, "size must be non-negative");	5558	return Error(SizeLoc, "size must be non-negative");
5559	if (Size > LocalMemorySize)	5559	if (Size > LocalMemorySize)
5560	return Error(SizeLoc, "size is too large");	5560	return Error(SizeLoc, "size is too large");
5561		5561
5562	int64_t Alignment = 4;	5562	int64_t Alignment = 4;
5563	if (trySkipToken(AsmToken::Comma)) {	5563	if (trySkipToken(AsmToken::Comma)) {
5564	SMLoc AlignLoc = getLoc();	5564	SMLoc AlignLoc = getLoc();
5565	if (getParser().parseAbsoluteExpression(Alignment))	5565	if (getParser().parseAbsoluteExpression(Alignment))
5566	return true;	5566	return true;
5567	if (Alignment < 0 \|\| !isPowerOf2_64(Alignment))	5567	if (Alignment < 0 \|\| !isPowerOf2_64(Alignment))
5568	return Error(AlignLoc, "alignment must be a power of two");	5568	return Error(AlignLoc, "alignment must be a power of two");
5569		5569
5570	// Alignment larger than the size of LDS is possible in theory, as long	5570	// Alignment larger than the size of LDS is possible in theory, as long
5571	// as the linker manages to place to symbol at address 0, but we do want	5571	// as the linker manages to place to symbol at address 0, but we do want
5572	// to make sure the alignment fits nicely into a 32-bit integer.	5572	// to make sure the alignment fits nicely into a 32-bit integer.
5573	if (Alignment >= 1u << 31)	5573	if (Alignment >= 1u << 31)
5574	return Error(AlignLoc, "alignment is too large");	5574	return Error(AlignLoc, "alignment is too large");
5575	}	5575	}
5576		5576
5577	if (parseEOL())	5577	if (parseEOL())
5578	return true;	5578	return true;
5579		5579
5580	Symbol->redefineIfPossible();	5580	Symbol->redefineIfPossible();
5581	if (!Symbol->isUndefined())	5581	if (!Symbol->isUndefined())
5582	return Error(NameLoc, "invalid symbol redefinition");	5582	return Error(NameLoc, "invalid symbol redefinition");
5583		5583
5584	getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));	5584	getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));
5585	return false;	5585	return false;
5586	}	5586	}
5587		5587
5588	bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {	5588	bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {
5589	StringRef IDVal = DirectiveID.getString();	5589	StringRef IDVal = DirectiveID.getString();
5590		5590
5591	if (isHsaAbiVersion3AndAbove(&getSTI())) {	5591	if (isHsaAbiVersion3AndAbove(&getSTI())) {
5592	if (IDVal == ".amdhsa_kernel")	5592	if (IDVal == ".amdhsa_kernel")
5593	return ParseDirectiveAMDHSAKernel();	5593	return ParseDirectiveAMDHSAKernel();
5594		5594
5595	// TODO: Restructure/combine with PAL metadata directive.	5595	// TODO: Restructure/combine with PAL metadata directive.
5596	if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)	5596	if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)
5597	return ParseDirectiveHSAMetadata();	5597	return ParseDirectiveHSAMetadata();
5598	} else {	5598	} else {
5599	if (IDVal == ".hsa_code_object_version")	5599	if (IDVal == ".hsa_code_object_version")
5600	return ParseDirectiveHSACodeObjectVersion();	5600	return ParseDirectiveHSACodeObjectVersion();
5601		5601
5602	if (IDVal == ".hsa_code_object_isa")	5602	if (IDVal == ".hsa_code_object_isa")
5603	return ParseDirectiveHSACodeObjectISA();	5603	return ParseDirectiveHSACodeObjectISA();
5604		5604
5605	if (IDVal == ".amd_kernel_code_t")	5605	if (IDVal == ".amd_kernel_code_t")
5606	return ParseDirectiveAMDKernelCodeT();	5606	return ParseDirectiveAMDKernelCodeT();
5607		5607
5608	if (IDVal == ".amdgpu_hsa_kernel")	5608	if (IDVal == ".amdgpu_hsa_kernel")
5609	return ParseDirectiveAMDGPUHsaKernel();	5609	return ParseDirectiveAMDGPUHsaKernel();
5610		5610
5611	if (IDVal == ".amd_amdgpu_isa")	5611	if (IDVal == ".amd_amdgpu_isa")
5612	return ParseDirectiveISAVersion();	5612	return ParseDirectiveISAVersion();
5613		5613
5614	if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)	5614	if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)
5615	return ParseDirectiveHSAMetadata();	5615	return ParseDirectiveHSAMetadata();
5616	}	5616	}
5617		5617
5618	if (IDVal == ".amdgcn_target")	5618	if (IDVal == ".amdgcn_target")
5619	return ParseDirectiveAMDGCNTarget();	5619	return ParseDirectiveAMDGCNTarget();
5620		5620
5621	if (IDVal == ".amdgpu_lds")	5621	if (IDVal == ".amdgpu_lds")
5622	return ParseDirectiveAMDGPULDS();	5622	return ParseDirectiveAMDGPULDS();
5623		5623
5624	if (IDVal == PALMD::AssemblerDirectiveBegin)	5624	if (IDVal == PALMD::AssemblerDirectiveBegin)
5625	return ParseDirectivePALMetadataBegin();	5625	return ParseDirectivePALMetadataBegin();
5626		5626
5627	if (IDVal == PALMD::AssemblerDirective)	5627	if (IDVal == PALMD::AssemblerDirective)
5628	return ParseDirectivePALMetadata();	5628	return ParseDirectivePALMetadata();
5629		5629
5630	return true;	5630	return true;
5631	}	5631	}
5632		5632
5633	bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,	5633	bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,
5634	unsigned RegNo) {	5634	unsigned RegNo) {
5635		5635
5636	if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))	5636	if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))
5637	return isGFX9Plus();	5637	return isGFX9Plus();
5638		5638
5639	// GFX10+ has 2 more SGPRs 104 and 105.	5639	// GFX10+ has 2 more SGPRs 104 and 105.
5640	if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))	5640	if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))
5641	return hasSGPR104_SGPR105();	5641	return hasSGPR104_SGPR105();
5642		5642
5643	switch (RegNo) {	5643	switch (RegNo) {
5644	case AMDGPU::SRC_SHARED_BASE_LO:	5644	case AMDGPU::SRC_SHARED_BASE_LO:
5645	case AMDGPU::SRC_SHARED_BASE:	5645	case AMDGPU::SRC_SHARED_BASE:
5646	case AMDGPU::SRC_SHARED_LIMIT_LO:	5646	case AMDGPU::SRC_SHARED_LIMIT_LO:
5647	case AMDGPU::SRC_SHARED_LIMIT:	5647	case AMDGPU::SRC_SHARED_LIMIT:
5648	case AMDGPU::SRC_PRIVATE_BASE_LO:	5648	case AMDGPU::SRC_PRIVATE_BASE_LO:
5649	case AMDGPU::SRC_PRIVATE_BASE:	5649	case AMDGPU::SRC_PRIVATE_BASE:
5650	case AMDGPU::SRC_PRIVATE_LIMIT_LO:	5650	case AMDGPU::SRC_PRIVATE_LIMIT_LO:
5651	case AMDGPU::SRC_PRIVATE_LIMIT:	5651	case AMDGPU::SRC_PRIVATE_LIMIT:
5652	return isGFX9Plus();	5652	return isGFX9Plus();
5653	case AMDGPU::SRC_POPS_EXITING_WAVE_ID:	5653	case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
5654	return isGFX9Plus() && !isGFX11Plus();	5654	return isGFX9Plus() && !isGFX11Plus();
5655	case AMDGPU::TBA:	5655	case AMDGPU::TBA:
5656	case AMDGPU::TBA_LO:	5656	case AMDGPU::TBA_LO:
5657	case AMDGPU::TBA_HI:	5657	case AMDGPU::TBA_HI:
5658	case AMDGPU::TMA:	5658	case AMDGPU::TMA:
5659	case AMDGPU::TMA_LO:	5659	case AMDGPU::TMA_LO:
5660	case AMDGPU::TMA_HI:	5660	case AMDGPU::TMA_HI:
5661	return !isGFX9Plus();	5661	return !isGFX9Plus();
5662	case AMDGPU::XNACK_MASK:	5662	case AMDGPU::XNACK_MASK:
5663	case AMDGPU::XNACK_MASK_LO:	5663	case AMDGPU::XNACK_MASK_LO:
5664	case AMDGPU::XNACK_MASK_HI:	5664	case AMDGPU::XNACK_MASK_HI:
5665	return (isVI() \|\| isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();	5665	return (isVI() \|\| isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();
5666	case AMDGPU::SGPR_NULL:	5666	case AMDGPU::SGPR_NULL:
5667	return isGFX10Plus();	5667	return isGFX10Plus();
5668	default:	5668	default:
5669	break;	5669	break;
5670	}	5670	}
5671		5671
5672	if (isCI())	5672	if (isCI())
5673	return true;	5673	return true;
5674		5674
5675	if (isSI() \|\| isGFX10Plus()) {	5675	if (isSI() \|\| isGFX10Plus()) {
5676	// No flat_scr on SI.	5676	// No flat_scr on SI.
5677	// On GFX10Plus flat scratch is not a valid register operand and can only be	5677	// On GFX10Plus flat scratch is not a valid register operand and can only be
5678	// accessed with s_setreg/s_getreg.	5678	// accessed with s_setreg/s_getreg.
5679	switch (RegNo) {	5679	switch (RegNo) {
5680	case AMDGPU::FLAT_SCR:	5680	case AMDGPU::FLAT_SCR:
5681	case AMDGPU::FLAT_SCR_LO:	5681	case AMDGPU::FLAT_SCR_LO:
5682	case AMDGPU::FLAT_SCR_HI:	5682	case AMDGPU::FLAT_SCR_HI:
5683	return false;	5683	return false;
5684	default:	5684	default:
5685	return true;	5685	return true;
5686	}	5686	}
5687	}	5687	}
5688		5688
5689	// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that	5689	// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that
5690	// SI/CI have.	5690	// SI/CI have.
5691	if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))	5691	if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))
5692	return hasSGPR102_SGPR103();	5692	return hasSGPR102_SGPR103();
5693		5693
5694	return true;	5694	return true;
5695	}	5695	}
5696		5696
5697	ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,	5697	ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,
5698	StringRef Mnemonic,	5698	StringRef Mnemonic,
5699	OperandMode Mode) {	5699	OperandMode Mode) {
5700	ParseStatus Res = parseVOPD(Operands);	5700	ParseStatus Res = parseVOPD(Operands);
5701	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	5701	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))
5702	return Res;	5702	return Res;
5703		5703
5704	// Try to parse with a custom parser	5704	// Try to parse with a custom parser
5705	Res = MatchOperandParserImpl(Operands, Mnemonic);	5705	Res = MatchOperandParserImpl(Operands, Mnemonic);
5706		5706
5707	// If we successfully parsed the operand or if there as an error parsing,	5707	// If we successfully parsed the operand or if there as an error parsing,
5708	// we are done.	5708	// we are done.
5709	//	5709	//
5710	// If we are parsing after we reach EndOfStatement then this means we	5710	// If we are parsing after we reach EndOfStatement then this means we
5711	// are appending default values to the Operands list. This is only done	5711	// are appending default values to the Operands list. This is only done
5712	// by custom parser, so we shouldn't continue on to the generic parsing.	5712	// by custom parser, so we shouldn't continue on to the generic parsing.
5713	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	5713	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))
5714	return Res;	5714	return Res;
5715		5715
5716	SMLoc RBraceLoc;	5716	SMLoc RBraceLoc;
5717	SMLoc LBraceLoc = getLoc();	5717	SMLoc LBraceLoc = getLoc();
5718	if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {	5718	if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {
5719	unsigned Prefix = Operands.size();	5719	unsigned Prefix = Operands.size();
5720		5720
5721	for (;;) {	5721	for (;;) {
5722	auto Loc = getLoc();	5722	auto Loc = getLoc();
5723	Res = parseReg(Operands);	5723	Res = parseReg(Operands);
5724	if (Res.isNoMatch())	5724	if (Res.isNoMatch())
5725	Error(Loc, "expected a register");	5725	Error(Loc, "expected a register");
5726	if (!Res.isSuccess())	5726	if (!Res.isSuccess())
5727	return ParseStatus::Failure;	5727	return ParseStatus::Failure;
5728		5728
5729	RBraceLoc = getLoc();	5729	RBraceLoc = getLoc();
5730	if (trySkipToken(AsmToken::RBrac))	5730	if (trySkipToken(AsmToken::RBrac))
5731	break;	5731	break;
5732		5732
5733	if (!skipToken(AsmToken::Comma,	5733	if (!skipToken(AsmToken::Comma,
5734	"expected a comma or a closing square bracket"))	5734	"expected a comma or a closing square bracket"))
5735	return ParseStatus::Failure;	5735	return ParseStatus::Failure;
5736	}	5736	}
5737		5737
5738	if (Operands.size() - Prefix > 1) {	5738	if (Operands.size() - Prefix > 1) {
5739	Operands.insert(Operands.begin() + Prefix,	5739	Operands.insert(Operands.begin() + Prefix,
5740	AMDGPUOperand::CreateToken(this, "[", LBraceLoc));	5740	AMDGPUOperand::CreateToken(this, "[", LBraceLoc));
5741	Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));	5741	Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));
5742	}	5742	}
5743		5743
5744	return ParseStatus::Success;	5744	return ParseStatus::Success;
5745	}	5745	}
5746		5746
5747	return parseRegOrImm(Operands);	5747	return parseRegOrImm(Operands);
5748	}	5748	}
5749		5749
5750	StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {	5750	StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {
5751	// Clear any forced encodings from the previous instruction.	5751	// Clear any forced encodings from the previous instruction.
5752	setForcedEncodingSize(0);	5752	setForcedEncodingSize(0);
5753	setForcedDPP(false);	5753	setForcedDPP(false);
5754	setForcedSDWA(false);	5754	setForcedSDWA(false);
5755		5755
5756	if (Name.endswith("_e64_dpp")) {	5756	if (Name.endswith("_e64_dpp")) {
5757	setForcedDPP(true);	5757	setForcedDPP(true);
5758	setForcedEncodingSize(64);	5758	setForcedEncodingSize(64);
5759	return Name.substr(0, Name.size() - 8);	5759	return Name.substr(0, Name.size() - 8);
5760	} else if (Name.endswith("_e64")) {	5760	} else if (Name.endswith("_e64")) {
5761	setForcedEncodingSize(64);	5761	setForcedEncodingSize(64);
5762	return Name.substr(0, Name.size() - 4);	5762	return Name.substr(0, Name.size() - 4);
5763	} else if (Name.endswith("_e32")) {	5763	} else if (Name.endswith("_e32")) {
5764	setForcedEncodingSize(32);	5764	setForcedEncodingSize(32);
5765	return Name.substr(0, Name.size() - 4);	5765	return Name.substr(0, Name.size() - 4);
5766	} else if (Name.endswith("_dpp")) {	5766	} else if (Name.endswith("_dpp")) {
5767	setForcedDPP(true);	5767	setForcedDPP(true);
5768	return Name.substr(0, Name.size() - 4);	5768	return Name.substr(0, Name.size() - 4);
5769	} else if (Name.endswith("_sdwa")) {	5769	} else if (Name.endswith("_sdwa")) {
5770	setForcedSDWA(true);	5770	setForcedSDWA(true);
5771	return Name.substr(0, Name.size() - 5);	5771	return Name.substr(0, Name.size() - 5);
5772	}	5772	}
5773	return Name;	5773	return Name;
5774	}	5774	}
5775		5775
5776	static void applyMnemonicAliases(StringRef &Mnemonic,	5776	static void applyMnemonicAliases(StringRef &Mnemonic,
5777	const FeatureBitset &Features,	5777	const FeatureBitset &Features,
5778	unsigned VariantID);	5778	unsigned VariantID);
5779		5779
5780	bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,	5780	bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
5781	StringRef Name,	5781	StringRef Name,
5782	SMLoc NameLoc, OperandVector &Operands) {	5782	SMLoc NameLoc, OperandVector &Operands) {
5783	// Add the instruction mnemonic	5783	// Add the instruction mnemonic
5784	Name = parseMnemonicSuffix(Name);	5784	Name = parseMnemonicSuffix(Name);
5785		5785
5786	// If the target architecture uses MnemonicAlias, call it here to parse	5786	// If the target architecture uses MnemonicAlias, call it here to parse
5787	// operands correctly.	5787	// operands correctly.
5788	applyMnemonicAliases(Name, getAvailableFeatures(), 0);	5788	applyMnemonicAliases(Name, getAvailableFeatures(), 0);
5789		5789
5790	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));	5790	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));
5791		5791
5792	bool IsMIMG = Name.startswith("image_");	5792	bool IsMIMG = Name.startswith("image_");
5793		5793
5794	while (!trySkipToken(AsmToken::EndOfStatement)) {	5794	while (!trySkipToken(AsmToken::EndOfStatement)) {
5795	OperandMode Mode = OperandMode_Default;	5795	OperandMode Mode = OperandMode_Default;
5796	if (IsMIMG && isGFX10Plus() && Operands.size() == 2)	5796	if (IsMIMG && isGFX10Plus() && Operands.size() == 2)
5797	Mode = OperandMode_NSA;	5797	Mode = OperandMode_NSA;
5798	ParseStatus Res = parseOperand(Operands, Name, Mode);	5798	ParseStatus Res = parseOperand(Operands, Name, Mode);
5799		5799
5800	if (!Res.isSuccess()) {	5800	if (!Res.isSuccess()) {
5801	checkUnsupportedInstruction(Name, NameLoc);	5801	checkUnsupportedInstruction(Name, NameLoc);
5802	if (!Parser.hasPendingError()) {	5802	if (!Parser.hasPendingError()) {
5803	// FIXME: use real operand location rather than the current location.	5803	// FIXME: use real operand location rather than the current location.
5804	StringRef Msg = Res.isFailure() ? "failed parsing operand."	5804	StringRef Msg = Res.isFailure() ? "failed parsing operand."
5805	: "not a valid operand.";	5805	: "not a valid operand.";
5806	Error(getLoc(), Msg);	5806	Error(getLoc(), Msg);
5807	}	5807	}
5808	while (!trySkipToken(AsmToken::EndOfStatement)) {	5808	while (!trySkipToken(AsmToken::EndOfStatement)) {
5809	lex();	5809	lex();
5810	}	5810	}
5811	return true;	5811	return true;
5812	}	5812	}
5813		5813
5814	// Eat the comma or space if there is one.	5814	// Eat the comma or space if there is one.
5815	trySkipToken(AsmToken::Comma);	5815	trySkipToken(AsmToken::Comma);
5816	}	5816	}
5817		5817
5818	return false;	5818	return false;
5819	}	5819	}
5820		5820
5821	//===----------------------------------------------------------------------===//	5821	//===----------------------------------------------------------------------===//
5822	// Utility functions	5822	// Utility functions
5823	//===----------------------------------------------------------------------===//	5823	//===----------------------------------------------------------------------===//
5824		5824
5825	ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,	5825	ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,
5826	OperandVector &Operands) {	5826	OperandVector &Operands) {
5827	SMLoc S = getLoc();	5827	SMLoc S = getLoc();
5828	if (!trySkipId(Name))	5828	if (!trySkipId(Name))
5829	return ParseStatus::NoMatch;	5829	return ParseStatus::NoMatch;
5830		5830
5831	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));	5831	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));
5832	return ParseStatus::Success;	5832	return ParseStatus::Success;
5833	}	5833	}
5834		5834
5835	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,	5835	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,
5836	int64_t &IntVal) {	5836	int64_t &IntVal) {
5837		5837
5838	if (!trySkipId(Prefix, AsmToken::Colon))	5838	if (!trySkipId(Prefix, AsmToken::Colon))
5839	return ParseStatus::NoMatch;	5839	return ParseStatus::NoMatch;
5840		5840
5841	return parseExpr(IntVal) ? ParseStatus::Success : ParseStatus::Failure;	5841	return parseExpr(IntVal) ? ParseStatus::Success : ParseStatus::Failure;
5842	}	5842	}
5843		5843
5844	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(	5844	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(
5845	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	5845	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
5846	std::function ConvertResult) {	5846	std::function ConvertResult) {
5847	SMLoc S = getLoc();	5847	SMLoc S = getLoc();
5848	int64_t Value = 0;	5848	int64_t Value = 0;
5849		5849
5850	ParseStatus Res = parseIntWithPrefix(Prefix, Value);	5850	ParseStatus Res = parseIntWithPrefix(Prefix, Value);
5851	if (!Res.isSuccess())	5851	if (!Res.isSuccess())
5852	return Res;	5852	return Res;
5853		5853
5854	if (ConvertResult && !ConvertResult(Value)) {	5854	if (ConvertResult && !ConvertResult(Value)) {
5855	Error(S, "invalid " + StringRef(Prefix) + " value.");	5855	Error(S, "invalid " + StringRef(Prefix) + " value.");
5856	}	5856	}
5857		5857
5858	Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));	5858	Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));
5859	return ParseStatus::Success;	5859	return ParseStatus::Success;
5860	}	5860	}
5861		5861
5862	ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(	5862	ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(
5863	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	5863	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,
5864	bool (*ConvertResult)(int64_t &)) {	5864	bool (*ConvertResult)(int64_t &)) {
5865	SMLoc S = getLoc();	5865	SMLoc S = getLoc();
5866	if (!trySkipId(Prefix, AsmToken::Colon))	5866	if (!trySkipId(Prefix, AsmToken::Colon))
5867	return ParseStatus::NoMatch;	5867	return ParseStatus::NoMatch;
5868		5868
5869	if (!skipToken(AsmToken::LBrac, "expected a left square bracket"))	5869	if (!skipToken(AsmToken::LBrac, "expected a left square bracket"))
5870	return ParseStatus::Failure;	5870	return ParseStatus::Failure;
5871		5871
5872	unsigned Val = 0;	5872	unsigned Val = 0;
5873	const unsigned MaxSize = 4;	5873	const unsigned MaxSize = 4;
5874		5874
5875	// FIXME: How to verify the number of elements matches the number of src	5875	// FIXME: How to verify the number of elements matches the number of src
5876	// operands?	5876	// operands?
5877	for (int I = 0; ; ++I) {	5877	for (int I = 0; ; ++I) {
5878	int64_t Op;	5878	int64_t Op;
5879	SMLoc Loc = getLoc();	5879	SMLoc Loc = getLoc();
5880	if (!parseExpr(Op))	5880	if (!parseExpr(Op))
5881	return ParseStatus::Failure;	5881	return ParseStatus::Failure;
5882		5882
5883	if (Op != 0 && Op != 1)	5883	if (Op != 0 && Op != 1)
5884	return Error(Loc, "invalid " + StringRef(Prefix) + " value.");	5884	return Error(Loc, "invalid " + StringRef(Prefix) + " value.");
5885		5885
5886	Val \|= (Op << I);	5886	Val \|= (Op << I);
5887		5887
5888	if (trySkipToken(AsmToken::RBrac))	5888	if (trySkipToken(AsmToken::RBrac))
5889	break;	5889	break;
5890		5890
5891	if (I + 1 == MaxSize)	5891	if (I + 1 == MaxSize)
5892	return Error(getLoc(), "expected a closing square bracket");	5892	return Error(getLoc(), "expected a closing square bracket");
5893		5893
5894	if (!skipToken(AsmToken::Comma, "expected a comma"))	5894	if (!skipToken(AsmToken::Comma, "expected a comma"))
5895	return ParseStatus::Failure;	5895	return ParseStatus::Failure;
5896	}	5896	}
5897		5897
5898	Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));	5898	Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));
5899	return ParseStatus::Success;	5899	return ParseStatus::Success;
5900	}	5900	}
5901		5901
5902	ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,	5902	ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,
5903	OperandVector &Operands,	5903	OperandVector &Operands,
5904	AMDGPUOperand::ImmTy ImmTy) {	5904	AMDGPUOperand::ImmTy ImmTy) {
5905	int64_t Bit;	5905	int64_t Bit;
5906	SMLoc S = getLoc();	5906	SMLoc S = getLoc();
5907		5907
5908	if (trySkipId(Name)) {	5908	if (trySkipId(Name)) {
5909	Bit = 1;	5909	Bit = 1;
5910	} else if (trySkipId("no", Name)) {	5910	} else if (trySkipId("no", Name)) {
5911	Bit = 0;	5911	Bit = 0;
5912	} else {	5912	} else {
5913	return ParseStatus::NoMatch;	5913	return ParseStatus::NoMatch;
5914	}	5914	}
5915		5915
5916	if (Name == "r128" && !hasMIMG_R128())	5916	if (Name == "r128" && !hasMIMG_R128())
5917	return Error(S, "r128 modifier is not supported on this GPU");	5917	return Error(S, "r128 modifier is not supported on this GPU");
5918	if (Name == "a16" && !hasA16())	5918	if (Name == "a16" && !hasA16())
5919	return Error(S, "a16 modifier is not supported on this GPU");	5919	return Error(S, "a16 modifier is not supported on this GPU");
5920		5920
5921	if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)	5921	if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)
5922	ImmTy = AMDGPUOperand::ImmTyR128A16;	5922	ImmTy = AMDGPUOperand::ImmTyR128A16;
5923		5923
5924	Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));	5924	Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));
5925	return ParseStatus::Success;	5925	return ParseStatus::Success;
5926	}	5926	}
5927		5927
5928	unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,	5928	unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,
5929	bool &Disabling) const {	5929	bool &Disabling) const {
5930	Disabling = Id.consume_front("no");	5930	Disabling = Id.consume_front("no");
5931		5931
5932	if (isGFX940() && !Mnemo.startswith("s_")) {	5932	if (isGFX940() && !Mnemo.startswith("s_")) {
5933	return StringSwitch(Id)	5933	return StringSwitch(Id)
5934	.Case("nt", AMDGPU::CPol::NT)	5934	.Case("nt", AMDGPU::CPol::NT)
5935	.Case("sc0", AMDGPU::CPol::SC0)	5935	.Case("sc0", AMDGPU::CPol::SC0)
5936	.Case("sc1", AMDGPU::CPol::SC1)	5936	.Case("sc1", AMDGPU::CPol::SC1)
5937	.Default(0);	5937	.Default(0);
5938	}	5938	}
5939		5939
5940	return StringSwitch(Id)	5940	return StringSwitch(Id)
5941	.Case("dlc", AMDGPU::CPol::DLC)	5941	.Case("dlc", AMDGPU::CPol::DLC)
5942	.Case("glc", AMDGPU::CPol::GLC)	5942	.Case("glc", AMDGPU::CPol::GLC)
5943	.Case("scc", AMDGPU::CPol::SCC)	5943	.Case("scc", AMDGPU::CPol::SCC)
5944	.Case("slc", AMDGPU::CPol::SLC)	5944	.Case("slc", AMDGPU::CPol::SLC)
5945	.Default(0);	5945	.Default(0);
5946	}	5946	}
5947		5947
5948	ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {	5948	ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {
5949	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	5949	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();
5950	SMLoc OpLoc = getLoc();	5950	SMLoc OpLoc = getLoc();
5951	unsigned Enabled = 0, Seen = 0;	5951	unsigned Enabled = 0, Seen = 0;
5952	for (;;) {	5952	for (;;) {
5953	SMLoc S = getLoc();	5953	SMLoc S = getLoc();
5954	bool Disabling;	5954	bool Disabling;
5955	unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);	5955	unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);
5956	if (!CPol)	5956	if (!CPol)
5957	break;	5957	break;
5958		5958
5959	lex();	5959	lex();
5960		5960
5961	if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)	5961	if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)
5962	return Error(S, "dlc modifier is not supported on this GPU");	5962	return Error(S, "dlc modifier is not supported on this GPU");
5963		5963
5964	if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)	5964	if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)
5965	return Error(S, "scc modifier is not supported on this GPU");	5965	return Error(S, "scc modifier is not supported on this GPU");
5966		5966
5967	if (Seen & CPol)	5967	if (Seen & CPol)
5968	return Error(S, "duplicate cache policy modifier");	5968	return Error(S, "duplicate cache policy modifier");
5969		5969
5970	if (!Disabling)	5970	if (!Disabling)
5971	Enabled \|= CPol;	5971	Enabled \|= CPol;
5972		5972
5973	Seen \|= CPol;	5973	Seen \|= CPol;
5974	}	5974	}
5975		5975
5976	if (!Seen)	5976	if (!Seen)
5977	return ParseStatus::NoMatch;	5977	return ParseStatus::NoMatch;
5978		5978
5979	Operands.push_back(	5979	Operands.push_back(
5980	AMDGPUOperand::CreateImm(this, Enabled, OpLoc, AMDGPUOperand::ImmTyCPol));	5980	AMDGPUOperand::CreateImm(this, Enabled, OpLoc, AMDGPUOperand::ImmTyCPol));
5981	return ParseStatus::Success;	5981	return ParseStatus::Success;
5982	}	5982	}
5983		5983
5984	static void addOptionalImmOperand(	5984	static void addOptionalImmOperand(
5985	MCInst& Inst, const OperandVector& Operands,	5985	MCInst& Inst, const OperandVector& Operands,
5986	AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,	5986	AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,
5987	AMDGPUOperand::ImmTy ImmT,	5987	AMDGPUOperand::ImmTy ImmT,
5988	int64_t Default = 0) {	5988	int64_t Default = 0) {
5989	auto i = OptionalIdx.find(ImmT);	5989	auto i = OptionalIdx.find(ImmT);
5990	if (i != OptionalIdx.end()) {	5990	if (i != OptionalIdx.end()) {
5991	unsigned Idx = i->second;	5991	unsigned Idx = i->second;
5992	((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);	5992	((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);
5993	} else {	5993	} else {
5994	Inst.addOperand(MCOperand::createImm(Default));	5994	Inst.addOperand(MCOperand::createImm(Default));
5995	}	5995	}
5996	}	5996	}
5997		5997
5998	ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,	5998	ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,
5999	StringRef &Value,	5999	StringRef &Value,
6000	SMLoc &StringLoc) {	6000	SMLoc &StringLoc) {
6001	if (!trySkipId(Prefix, AsmToken::Colon))	6001	if (!trySkipId(Prefix, AsmToken::Colon))
6002	return ParseStatus::NoMatch;	6002	return ParseStatus::NoMatch;
6003		6003
6004	StringLoc = getLoc();	6004	StringLoc = getLoc();
6005	return parseId(Value, "expected an identifier") ? ParseStatus::Success	6005	return parseId(Value, "expected an identifier") ? ParseStatus::Success
6006	: ParseStatus::Failure;	6006	: ParseStatus::Failure;
6007	}	6007	}
6008		6008
6009	//===----------------------------------------------------------------------===//	6009	//===----------------------------------------------------------------------===//
6010	// MTBUF format	6010	// MTBUF format
6011	//===----------------------------------------------------------------------===//	6011	//===----------------------------------------------------------------------===//
6012		6012
6013	bool AMDGPUAsmParser::tryParseFmt(const char *Pref,	6013	bool AMDGPUAsmParser::tryParseFmt(const char *Pref,
6014	int64_t MaxVal,	6014	int64_t MaxVal,
6015	int64_t &Fmt) {	6015	int64_t &Fmt) {
6016	int64_t Val;	6016	int64_t Val;
6017	SMLoc Loc = getLoc();	6017	SMLoc Loc = getLoc();
6018		6018
6019	auto Res = parseIntWithPrefix(Pref, Val);	6019	auto Res = parseIntWithPrefix(Pref, Val);
6020	if (Res.isFailure())	6020	if (Res.isFailure())
6021	return false;	6021	return false;
6022	if (Res.isNoMatch())	6022	if (Res.isNoMatch())
6023	return true;	6023	return true;
6024		6024
6025	if (Val < 0 \|\| Val > MaxVal) {	6025	if (Val < 0 \|\| Val > MaxVal) {
6026	Error(Loc, Twine("out of range ", StringRef(Pref)));	6026	Error(Loc, Twine("out of range ", StringRef(Pref)));
6027	return false;	6027	return false;
6028	}	6028	}
6029		6029
6030	Fmt = Val;	6030	Fmt = Val;
6031	return true;	6031	return true;
6032	}	6032	}
6033		6033
6034	// dfmt and nfmt (in a tbuffer instruction) are parsed as one to allow their	6034	// dfmt and nfmt (in a tbuffer instruction) are parsed as one to allow their
6035	// values to live in a joint format operand in the MCInst encoding.	6035	// values to live in a joint format operand in the MCInst encoding.
6036	ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {	6036	ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {
6037	using namespace llvm::AMDGPU::MTBUFFormat;	6037	using namespace llvm::AMDGPU::MTBUFFormat;
6038		6038
6039	int64_t Dfmt = DFMT_UNDEF;	6039	int64_t Dfmt = DFMT_UNDEF;
6040	int64_t Nfmt = NFMT_UNDEF;	6040	int64_t Nfmt = NFMT_UNDEF;
6041		6041
6042	// dfmt and nfmt can appear in either order, and each is optional.	6042	// dfmt and nfmt can appear in either order, and each is optional.
6043	for (int I = 0; I < 2; ++I) {	6043	for (int I = 0; I < 2; ++I) {
6044	if (Dfmt == DFMT_UNDEF && !tryParseFmt("dfmt", DFMT_MAX, Dfmt))	6044	if (Dfmt == DFMT_UNDEF && !tryParseFmt("dfmt", DFMT_MAX, Dfmt))
6045	return ParseStatus::Failure;	6045	return ParseStatus::Failure;
6046		6046
6047	if (Nfmt == NFMT_UNDEF && !tryParseFmt("nfmt", NFMT_MAX, Nfmt))	6047	if (Nfmt == NFMT_UNDEF && !tryParseFmt("nfmt", NFMT_MAX, Nfmt))
6048	return ParseStatus::Failure;	6048	return ParseStatus::Failure;
6049		6049
6050	// Skip optional comma between dfmt/nfmt	6050	// Skip optional comma between dfmt/nfmt
6051	// but guard against 2 commas following each other.	6051	// but guard against 2 commas following each other.
6052	if ((Dfmt == DFMT_UNDEF) != (Nfmt == NFMT_UNDEF) &&	6052	if ((Dfmt == DFMT_UNDEF) != (Nfmt == NFMT_UNDEF) &&
6053	!peekToken().is(AsmToken::Comma)) {	6053	!peekToken().is(AsmToken::Comma)) {
6054	trySkipToken(AsmToken::Comma);	6054	trySkipToken(AsmToken::Comma);
6055	}	6055	}
6056	}	6056	}
6057		6057
6058	if (Dfmt == DFMT_UNDEF && Nfmt == NFMT_UNDEF)	6058	if (Dfmt == DFMT_UNDEF && Nfmt == NFMT_UNDEF)
6059	return ParseStatus::NoMatch;	6059	return ParseStatus::NoMatch;
6060		6060
6061	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	6061	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;
6062	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	6062	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;
6063		6063
6064	Format = encodeDfmtNfmt(Dfmt, Nfmt);	6064	Format = encodeDfmtNfmt(Dfmt, Nfmt);
6065	return ParseStatus::Success;	6065	return ParseStatus::Success;
6066	}	6066	}
6067		6067
6068	ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {	6068	ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {
6069	using namespace llvm::AMDGPU::MTBUFFormat;	6069	using namespace llvm::AMDGPU::MTBUFFormat;
6070		6070
6071	int64_t Fmt = UFMT_UNDEF;	6071	int64_t Fmt = UFMT_UNDEF;
6072		6072
6073	if (!tryParseFmt("format", UFMT_MAX, Fmt))	6073	if (!tryParseFmt("format", UFMT_MAX, Fmt))
6074	return ParseStatus::Failure;	6074	return ParseStatus::Failure;
6075		6075
6076	if (Fmt == UFMT_UNDEF)	6076	if (Fmt == UFMT_UNDEF)
6077	return ParseStatus::NoMatch;	6077	return ParseStatus::NoMatch;
6078		6078
6079	Format = Fmt;	6079	Format = Fmt;
6080	return ParseStatus::Success;	6080	return ParseStatus::Success;
6081	}	6081	}
6082		6082
6083	bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,	6083	bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,
6084	int64_t &Nfmt,	6084	int64_t &Nfmt,
6085	StringRef FormatStr,	6085	StringRef FormatStr,
6086	SMLoc Loc) {	6086	SMLoc Loc) {
6087	using namespace llvm::AMDGPU::MTBUFFormat;	6087	using namespace llvm::AMDGPU::MTBUFFormat;
6088	int64_t Format;	6088	int64_t Format;
6089		6089
6090	Format = getDfmt(FormatStr);	6090	Format = getDfmt(FormatStr);
6091	if (Format != DFMT_UNDEF) {	6091	if (Format != DFMT_UNDEF) {
6092	Dfmt = Format;	6092	Dfmt = Format;
6093	return true;	6093	return true;
6094	}	6094	}
6095		6095
6096	Format = getNfmt(FormatStr, getSTI());	6096	Format = getNfmt(FormatStr, getSTI());
6097	if (Format != NFMT_UNDEF) {	6097	if (Format != NFMT_UNDEF) {
6098	Nfmt = Format;	6098	Nfmt = Format;
6099	return true;	6099	return true;
6100	}	6100	}
6101		6101
6102	Error(Loc, "unsupported format");	6102	Error(Loc, "unsupported format");
6103	return false;	6103	return false;
6104	}	6104	}
6105		6105
6106	ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,	6106	ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,
6107	SMLoc FormatLoc,	6107	SMLoc FormatLoc,
6108	int64_t &Format) {	6108	int64_t &Format) {
6109	using namespace llvm::AMDGPU::MTBUFFormat;	6109	using namespace llvm::AMDGPU::MTBUFFormat;
6110		6110
6111	int64_t Dfmt = DFMT_UNDEF;	6111	int64_t Dfmt = DFMT_UNDEF;
6112	int64_t Nfmt = NFMT_UNDEF;	6112	int64_t Nfmt = NFMT_UNDEF;
6113	if (!matchDfmtNfmt(Dfmt, Nfmt, FormatStr, FormatLoc))	6113	if (!matchDfmtNfmt(Dfmt, Nfmt, FormatStr, FormatLoc))
6114	return ParseStatus::Failure;	6114	return ParseStatus::Failure;
6115		6115
6116	if (trySkipToken(AsmToken::Comma)) {	6116	if (trySkipToken(AsmToken::Comma)) {
6117	StringRef Str;	6117	StringRef Str;
6118	SMLoc Loc = getLoc();	6118	SMLoc Loc = getLoc();
6119	if (!parseId(Str, "expected a format string") \|\|	6119	if (!parseId(Str, "expected a format string") \|\|
6120	!matchDfmtNfmt(Dfmt, Nfmt, Str, Loc))	6120	!matchDfmtNfmt(Dfmt, Nfmt, Str, Loc))
6121	return ParseStatus::Failure;	6121	return ParseStatus::Failure;
6122	if (Dfmt == DFMT_UNDEF)	6122	if (Dfmt == DFMT_UNDEF)
6123	return Error(Loc, "duplicate numeric format");	6123	return Error(Loc, "duplicate numeric format");
6124	if (Nfmt == NFMT_UNDEF)	6124	if (Nfmt == NFMT_UNDEF)
6125	return Error(Loc, "duplicate data format");	6125	return Error(Loc, "duplicate data format");
6126	}	6126	}
6127		6127
6128	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	6128	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;
6129	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	6129	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;
6130		6130
6131	if (isGFX10Plus()) {	6131	if (isGFX10Plus()) {
6132	auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt, getSTI());	6132	auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt, getSTI());
6133	if (Ufmt == UFMT_UNDEF)	6133	if (Ufmt == UFMT_UNDEF)
6134	return Error(FormatLoc, "unsupported format");	6134	return Error(FormatLoc, "unsupported format");
6135	Format = Ufmt;	6135	Format = Ufmt;
6136	} else {	6136	} else {
6137	Format = encodeDfmtNfmt(Dfmt, Nfmt);	6137	Format = encodeDfmtNfmt(Dfmt, Nfmt);
6138	}	6138	}
6139		6139
6140	return ParseStatus::Success;	6140	return ParseStatus::Success;
6141	}	6141	}
6142		6142
6143	ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,	6143	ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,
6144	SMLoc Loc,	6144	SMLoc Loc,
6145	int64_t &Format) {	6145	int64_t &Format) {
6146	using namespace llvm::AMDGPU::MTBUFFormat;	6146	using namespace llvm::AMDGPU::MTBUFFormat;
6147		6147
6148	auto Id = getUnifiedFormat(FormatStr, getSTI());	6148	auto Id = getUnifiedFormat(FormatStr, getSTI());
6149	if (Id == UFMT_UNDEF)	6149	if (Id == UFMT_UNDEF)
6150	return ParseStatus::NoMatch;	6150	return ParseStatus::NoMatch;
6151		6151
6152	if (!isGFX10Plus())	6152	if (!isGFX10Plus())
6153	return Error(Loc, "unified format is not supported on this GPU");	6153	return Error(Loc, "unified format is not supported on this GPU");
6154		6154
6155	Format = Id;	6155	Format = Id;
6156	return ParseStatus::Success;	6156	return ParseStatus::Success;
6157	}	6157	}
6158		6158
6159	ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {	6159	ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {
6160	using namespace llvm::AMDGPU::MTBUFFormat;	6160	using namespace llvm::AMDGPU::MTBUFFormat;
6161	SMLoc Loc = getLoc();	6161	SMLoc Loc = getLoc();
6162		6162
6163	if (!parseExpr(Format))	6163	if (!parseExpr(Format))
6164	return ParseStatus::Failure;	6164	return ParseStatus::Failure;
6165	if (!isValidFormatEncoding(Format, getSTI()))	6165	if (!isValidFormatEncoding(Format, getSTI()))
6166	return Error(Loc, "out of range format");	6166	return Error(Loc, "out of range format");
6167		6167
6168	return ParseStatus::Success;	6168	return ParseStatus::Success;
6169	}	6169	}
6170		6170
6171	ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {	6171	ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {
6172	using namespace llvm::AMDGPU::MTBUFFormat;	6172	using namespace llvm::AMDGPU::MTBUFFormat;
6173		6173
6174	if (!trySkipId("format", AsmToken::Colon))	6174	if (!trySkipId("format", AsmToken::Colon))
6175	return ParseStatus::NoMatch;	6175	return ParseStatus::NoMatch;
6176		6176
6177	if (trySkipToken(AsmToken::LBrac)) {	6177	if (trySkipToken(AsmToken::LBrac)) {
6178	StringRef FormatStr;	6178	StringRef FormatStr;
6179	SMLoc Loc = getLoc();	6179	SMLoc Loc = getLoc();
6180	if (!parseId(FormatStr, "expected a format string"))	6180	if (!parseId(FormatStr, "expected a format string"))
6181	return ParseStatus::Failure;	6181	return ParseStatus::Failure;
6182		6182
6183	auto Res = parseSymbolicUnifiedFormat(FormatStr, Loc, Format);	6183	auto Res = parseSymbolicUnifiedFormat(FormatStr, Loc, Format);
6184	if (Res.isNoMatch())	6184	if (Res.isNoMatch())
6185	Res = parseSymbolicSplitFormat(FormatStr, Loc, Format);	6185	Res = parseSymbolicSplitFormat(FormatStr, Loc, Format);
6186	if (!Res.isSuccess())	6186	if (!Res.isSuccess())
6187	return Res;	6187	return Res;
6188		6188
6189	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	6189	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
6190	return ParseStatus::Failure;	6190	return ParseStatus::Failure;
6191		6191
6192	return ParseStatus::Success;	6192	return ParseStatus::Success;
6193	}	6193	}
6194		6194
6195	return parseNumericFormat(Format);	6195	return parseNumericFormat(Format);
6196	}	6196	}
6197		6197
6198	ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {	6198	ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {
6199	using namespace llvm::AMDGPU::MTBUFFormat;	6199	using namespace llvm::AMDGPU::MTBUFFormat;
6200		6200
6201	int64_t Format = getDefaultFormatEncoding(getSTI());	6201	int64_t Format = getDefaultFormatEncoding(getSTI());
6202	ParseStatus Res;	6202	ParseStatus Res;
6203	SMLoc Loc = getLoc();	6203	SMLoc Loc = getLoc();
6204		6204
6205	// Parse legacy format syntax.	6205	// Parse legacy format syntax.
6206	Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format);	6206	Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format);
6207	if (Res.isFailure())	6207	if (Res.isFailure())
6208	return Res;	6208	return Res;
6209		6209
6210	bool FormatFound = Res.isSuccess();	6210	bool FormatFound = Res.isSuccess();
6211		6211
6212	Operands.push_back(	6212	Operands.push_back(
6213	AMDGPUOperand::CreateImm(this, Format, Loc, AMDGPUOperand::ImmTyFORMAT));	6213	AMDGPUOperand::CreateImm(this, Format, Loc, AMDGPUOperand::ImmTyFORMAT));
6214		6214
6215	if (FormatFound)	6215	if (FormatFound)
6216	trySkipToken(AsmToken::Comma);	6216	trySkipToken(AsmToken::Comma);
6217		6217
6218	if (isToken(AsmToken::EndOfStatement)) {	6218	if (isToken(AsmToken::EndOfStatement)) {
6219	// We are expecting an soffset operand,	6219	// We are expecting an soffset operand,
6220	// but let matcher handle the error.	6220	// but let matcher handle the error.
6221	return ParseStatus::Success;	6221	return ParseStatus::Success;
6222	}	6222	}
6223		6223
6224	// Parse soffset.	6224	// Parse soffset.
6225	Res = parseRegOrImm(Operands);	6225	Res = parseRegOrImm(Operands);
6226	if (!Res.isSuccess())	6226	if (!Res.isSuccess())
6227	return Res;	6227	return Res;
6228		6228
6229	trySkipToken(AsmToken::Comma);	6229	trySkipToken(AsmToken::Comma);
6230		6230
6231	if (!FormatFound) {	6231	if (!FormatFound) {
6232	Res = parseSymbolicOrNumericFormat(Format);	6232	Res = parseSymbolicOrNumericFormat(Format);
6233	if (Res.isFailure())	6233	if (Res.isFailure())
6234	return Res;	6234	return Res;
6235	if (Res.isSuccess()) {	6235	if (Res.isSuccess()) {
6236	auto Size = Operands.size();	6236	auto Size = Operands.size();
6237	AMDGPUOperand &Op = static_cast(*Operands[Size - 2]);	6237	AMDGPUOperand &Op = static_cast(*Operands[Size - 2]);
6238	assert(Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyFORMAT);	6238	assert(Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyFORMAT);
6239	Op.setImm(Format);	6239	Op.setImm(Format);
6240	}	6240	}
6241	return ParseStatus::Success;	6241	return ParseStatus::Success;
6242	}	6242	}
6243		6243
6244	if (isId("format") && peekToken().is(AsmToken::Colon))	6244	if (isId("format") && peekToken().is(AsmToken::Colon))
6245	return Error(getLoc(), "duplicate format");	6245	return Error(getLoc(), "duplicate format");
6246	return ParseStatus::Success;	6246	return ParseStatus::Success;
6247	}	6247	}
6248		6248
6249	ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {	6249	ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {
6250	ParseStatus Res =	6250	ParseStatus Res =
6251	parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);	6251	parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);
6252	if (Res.isNoMatch()) {	6252	if (Res.isNoMatch()) {
6253	Res = parseIntWithPrefix("inst_offset", Operands,	6253	Res = parseIntWithPrefix("inst_offset", Operands,
6254	AMDGPUOperand::ImmTyInstOffset);	6254	AMDGPUOperand::ImmTyInstOffset);
6255	}	6255	}
6256	return Res;	6256	return Res;
6257	}	6257	}
6258		6258
6259	ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {	6259	ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {
6260	ParseStatus Res =	6260	ParseStatus Res =
6261	parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);	6261	parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);
6262	if (Res.isNoMatch())	6262	if (Res.isNoMatch())
6263	Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);	6263	Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);
6264	return Res;	6264	return Res;
6265	}	6265	}
6266		6266
6267	ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {	6267	ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {
6268	ParseStatus Res =	6268	ParseStatus Res =
6269	parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);	6269	parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);
6270	if (Res.isNoMatch()) {	6270	if (Res.isNoMatch()) {
6271	Res =	6271	Res =
6272	parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);	6272	parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);
6273	}	6273	}
6274	return Res;	6274	return Res;
6275	}	6275	}
6276		6276
6277	//===----------------------------------------------------------------------===//	6277	//===----------------------------------------------------------------------===//
6278	// Exp	6278	// Exp
6279	//===----------------------------------------------------------------------===//	6279	//===----------------------------------------------------------------------===//
6280		6280
6281	void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {	6281	void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
6282	OptionalImmIndexMap OptionalIdx;	6282	OptionalImmIndexMap OptionalIdx;
6283		6283
6284	unsigned OperandIdx[4];	6284	unsigned OperandIdx[4];
6285	unsigned EnMask = 0;	6285	unsigned EnMask = 0;
6286	int SrcIdx = 0;	6286	int SrcIdx = 0;
6287		6287
6288	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	6288	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
6289	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	6289	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
6290		6290
6291	// Add the register arguments	6291	// Add the register arguments
6292	if (Op.isReg()) {	6292	if (Op.isReg()) {
6293	assert(SrcIdx < 4);	6293	assert(SrcIdx < 4);
6294	OperandIdx[SrcIdx] = Inst.size();	6294	OperandIdx[SrcIdx] = Inst.size();
6295	Op.addRegOperands(Inst, 1);	6295	Op.addRegOperands(Inst, 1);
6296	++SrcIdx;	6296	++SrcIdx;
6297	continue;	6297	continue;
6298	}	6298	}
6299		6299
6300	if (Op.isOff()) {	6300	if (Op.isOff()) {
6301	assert(SrcIdx < 4);	6301	assert(SrcIdx < 4);
6302	OperandIdx[SrcIdx] = Inst.size();	6302	OperandIdx[SrcIdx] = Inst.size();
6303	Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));	6303	Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));
6304	++SrcIdx;	6304	++SrcIdx;
6305	continue;	6305	continue;
6306	}	6306	}
6307		6307
6308	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {	6308	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {
6309	Op.addImmOperands(Inst, 1);	6309	Op.addImmOperands(Inst, 1);
6310	continue;	6310	continue;
6311	}	6311	}
6312		6312
6313	if (Op.isToken() && (Op.getToken() == "done" \|\| Op.getToken() == "row_en"))	6313	if (Op.isToken() && (Op.getToken() == "done" \|\| Op.getToken() == "row_en"))
6314	continue;	6314	continue;
6315		6315
6316	// Handle optional arguments	6316	// Handle optional arguments
6317	OptionalIdx[Op.getImmTy()] = i;	6317	OptionalIdx[Op.getImmTy()] = i;
6318	}	6318	}
6319		6319
6320	assert(SrcIdx == 4);	6320	assert(SrcIdx == 4);
6321		6321
6322	bool Compr = false;	6322	bool Compr = false;
6323	if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {	6323	if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {
6324	Compr = true;	6324	Compr = true;
6325	Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);	6325	Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);
6326	Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);	6326	Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
6327	Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);	6327	Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
6328	}	6328	}
6329		6329
6330	for (auto i = 0; i < SrcIdx; ++i) {	6330	for (auto i = 0; i < SrcIdx; ++i) {
6331	if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {	6331	if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {
6332	EnMask \|= Compr? (0x3 << i * 2) : (0x1 << i);	6332	EnMask \|= Compr? (0x3 << i * 2) : (0x1 << i);
6333	}	6333	}
6334	}	6334	}
6335		6335
6336	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);	6336	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);
6337	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);	6337	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);
6338		6338
6339	Inst.addOperand(MCOperand::createImm(EnMask));	6339	Inst.addOperand(MCOperand::createImm(EnMask));
6340	}	6340	}
6341		6341
6342	//===----------------------------------------------------------------------===//	6342	//===----------------------------------------------------------------------===//
6343	// s_waitcnt	6343	// s_waitcnt
6344	//===----------------------------------------------------------------------===//	6344	//===----------------------------------------------------------------------===//
6345		6345
6346	static bool	6346	static bool
6347	encodeCnt(	6347	encodeCnt(
6348	const AMDGPU::IsaVersion ISA,	6348	const AMDGPU::IsaVersion ISA,
6349	int64_t &IntVal,	6349	int64_t &IntVal,
6350	int64_t CntVal,	6350	int64_t CntVal,
6351	bool Saturate,	6351	bool Saturate,
6352	unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned),	6352	unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned),
6353	unsigned (*decode)(const IsaVersion &Version, unsigned))	6353	unsigned (*decode)(const IsaVersion &Version, unsigned))
6354	{	6354	{
6355	bool Failed = false;	6355	bool Failed = false;
6356		6356
6357	IntVal = encode(ISA, IntVal, CntVal);	6357	IntVal = encode(ISA, IntVal, CntVal);
6358	if (CntVal != decode(ISA, IntVal)) {	6358	if (CntVal != decode(ISA, IntVal)) {
6359	if (Saturate) {	6359	if (Saturate) {
6360	IntVal = encode(ISA, IntVal, -1);	6360	IntVal = encode(ISA, IntVal, -1);
6361	} else {	6361	} else {
6362	Failed = true;	6362	Failed = true;
6363	}	6363	}
6364	}	6364	}
6365	return Failed;	6365	return Failed;
6366	}	6366	}
6367		6367
6368	bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {	6368	bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {
6369		6369
6370	SMLoc CntLoc = getLoc();	6370	SMLoc CntLoc = getLoc();
6371	StringRef CntName = getTokenStr();	6371	StringRef CntName = getTokenStr();
6372		6372
6373	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	6373	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|
6374	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	6374	!skipToken(AsmToken::LParen, "expected a left parenthesis"))
6375	return false;	6375	return false;
6376		6376
6377	int64_t CntVal;	6377	int64_t CntVal;
6378	SMLoc ValLoc = getLoc();	6378	SMLoc ValLoc = getLoc();
6379	if (!parseExpr(CntVal))	6379	if (!parseExpr(CntVal))
6380	return false;	6380	return false;
6381		6381
6382	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	6382	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
6383		6383
6384	bool Failed = true;	6384	bool Failed = true;
6385	bool Sat = CntName.endswith("_sat");	6385	bool Sat = CntName.endswith("_sat");
6386		6386
6387	if (CntName == "vmcnt" \|\| CntName == "vmcnt_sat") {	6387	if (CntName == "vmcnt" \|\| CntName == "vmcnt_sat") {
6388	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeVmcnt, decodeVmcnt);	6388	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeVmcnt, decodeVmcnt);
6389	} else if (CntName == "expcnt" \|\| CntName == "expcnt_sat") {	6389	} else if (CntName == "expcnt" \|\| CntName == "expcnt_sat") {
6390	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeExpcnt, decodeExpcnt);	6390	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeExpcnt, decodeExpcnt);
6391	} else if (CntName == "lgkmcnt" \|\| CntName == "lgkmcnt_sat") {	6391	} else if (CntName == "lgkmcnt" \|\| CntName == "lgkmcnt_sat") {
6392	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeLgkmcnt, decodeLgkmcnt);	6392	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeLgkmcnt, decodeLgkmcnt);
6393	} else {	6393	} else {
6394	Error(CntLoc, "invalid counter name " + CntName);	6394	Error(CntLoc, "invalid counter name " + CntName);
6395	return false;	6395	return false;
6396	}	6396	}
6397		6397
6398	if (Failed) {	6398	if (Failed) {
6399	Error(ValLoc, "too large value for " + CntName);	6399	Error(ValLoc, "too large value for " + CntName);
6400	return false;	6400	return false;
6401	}	6401	}
6402		6402
6403	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	6403	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))
6404	return false;	6404	return false;
6405		6405
6406	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	6406	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {
6407	if (isToken(AsmToken::EndOfStatement)) {	6407	if (isToken(AsmToken::EndOfStatement)) {
6408	Error(getLoc(), "expected a counter name");	6408	Error(getLoc(), "expected a counter name");
6409	return false;	6409	return false;
6410	}	6410	}
6411	}	6411	}
6412		6412
6413	return true;	6413	return true;
6414	}	6414	}
6415		6415
6416	ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {	6416	ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {
6417	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	6417	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());
6418	int64_t Waitcnt = getWaitcntBitMask(ISA);	6418	int64_t Waitcnt = getWaitcntBitMask(ISA);
6419	SMLoc S = getLoc();	6419	SMLoc S = getLoc();
6420		6420
6421	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	6421	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {
6422	while (!isToken(AsmToken::EndOfStatement)) {	6422	while (!isToken(AsmToken::EndOfStatement)) {
6423	if (!parseCnt(Waitcnt))	6423	if (!parseCnt(Waitcnt))
6424	return ParseStatus::Failure;	6424	return ParseStatus::Failure;
6425	}	6425	}
6426	} else {	6426	} else {
6427	if (!parseExpr(Waitcnt))	6427	if (!parseExpr(Waitcnt))
6428	return ParseStatus::Failure;	6428	return ParseStatus::Failure;
6429	}	6429	}
6430		6430
6431	Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));	6431	Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));
6432	return ParseStatus::Success;	6432	return ParseStatus::Success;
6433	}	6433	}
6434		6434
6435	bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {	6435	bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {
6436	SMLoc FieldLoc = getLoc();	6436	SMLoc FieldLoc = getLoc();
6437	StringRef FieldName = getTokenStr();	6437	StringRef FieldName = getTokenStr();
6438	if (!skipToken(AsmToken::Identifier, "expected a field name") \|\|	6438	if (!skipToken(AsmToken::Identifier, "expected a field name") \|\|
6439	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	6439	!skipToken(AsmToken::LParen, "expected a left parenthesis"))
6440	return false;	6440	return false;
6441		6441
6442	SMLoc ValueLoc = getLoc();	6442	SMLoc ValueLoc = getLoc();
6443	StringRef ValueName = getTokenStr();	6443	StringRef ValueName = getTokenStr();
6444	if (!skipToken(AsmToken::Identifier, "expected a value name") \|\|	6444	if (!skipToken(AsmToken::Identifier, "expected a value name") \|\|
6445	!skipToken(AsmToken::RParen, "expected a right parenthesis"))	6445	!skipToken(AsmToken::RParen, "expected a right parenthesis"))
6446	return false;	6446	return false;
6447		6447
6448	unsigned Shift;	6448	unsigned Shift;
6449	if (FieldName == "instid0") {	6449	if (FieldName == "instid0") {
6450	Shift = 0;	6450	Shift = 0;
6451	} else if (FieldName == "instskip") {	6451	} else if (FieldName == "instskip") {
6452	Shift = 4;	6452	Shift = 4;
6453	} else if (FieldName == "instid1") {	6453	} else if (FieldName == "instid1") {
6454	Shift = 7;	6454	Shift = 7;
6455	} else {	6455	} else {
6456	Error(FieldLoc, "invalid field name " + FieldName);	6456	Error(FieldLoc, "invalid field name " + FieldName);
6457	return false;	6457	return false;
6458	}	6458	}
6459		6459
6460	int Value;	6460	int Value;
6461	if (Shift == 4) {	6461	if (Shift == 4) {
6462	// Parse values for instskip.	6462	// Parse values for instskip.
6463	Value = StringSwitch(ValueName)	6463	Value = StringSwitch(ValueName)
6464	.Case("SAME", 0)	6464	.Case("SAME", 0)
6465	.Case("NEXT", 1)	6465	.Case("NEXT", 1)
6466	.Case("SKIP_1", 2)	6466	.Case("SKIP_1", 2)
6467	.Case("SKIP_2", 3)	6467	.Case("SKIP_2", 3)
6468	.Case("SKIP_3", 4)	6468	.Case("SKIP_3", 4)
6469	.Case("SKIP_4", 5)	6469	.Case("SKIP_4", 5)
6470	.Default(-1);	6470	.Default(-1);
6471	} else {	6471	} else {
6472	// Parse values for instid0 and instid1.	6472	// Parse values for instid0 and instid1.
6473	Value = StringSwitch(ValueName)	6473	Value = StringSwitch(ValueName)
6474	.Case("NO_DEP", 0)	6474	.Case("NO_DEP", 0)
6475	.Case("VALU_DEP_1", 1)	6475	.Case("VALU_DEP_1", 1)
6476	.Case("VALU_DEP_2", 2)	6476	.Case("VALU_DEP_2", 2)
6477	.Case("VALU_DEP_3", 3)	6477	.Case("VALU_DEP_3", 3)
6478	.Case("VALU_DEP_4", 4)	6478	.Case("VALU_DEP_4", 4)
6479	.Case("TRANS32_DEP_1", 5)	6479	.Case("TRANS32_DEP_1", 5)
6480	.Case("TRANS32_DEP_2", 6)	6480	.Case("TRANS32_DEP_2", 6)
6481	.Case("TRANS32_DEP_3", 7)	6481	.Case("TRANS32_DEP_3", 7)
6482	.Case("FMA_ACCUM_CYCLE_1", 8)	6482	.Case("FMA_ACCUM_CYCLE_1", 8)
6483	.Case("SALU_CYCLE_1", 9)	6483	.Case("SALU_CYCLE_1", 9)
6484	.Case("SALU_CYCLE_2", 10)	6484	.Case("SALU_CYCLE_2", 10)
6485	.Case("SALU_CYCLE_3", 11)	6485	.Case("SALU_CYCLE_3", 11)
6486	.Default(-1);	6486	.Default(-1);
6487	}	6487	}
6488	if (Value < 0) {	6488	if (Value < 0) {
6489	Error(ValueLoc, "invalid value name " + ValueName);	6489	Error(ValueLoc, "invalid value name " + ValueName);
6490	return false;	6490	return false;
6491	}	6491	}
6492		6492
6493	Delay \|= Value << Shift;	6493	Delay \|= Value << Shift;
6494	return true;	6494	return true;
6495	}	6495	}
6496		6496
6497	ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {	6497	ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {
6498	int64_t Delay = 0;	6498	int64_t Delay = 0;
6499	SMLoc S = getLoc();	6499	SMLoc S = getLoc();
6500		6500
6501	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	6501	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {
6502	do {	6502	do {
6503	if (!parseDelay(Delay))	6503	if (!parseDelay(Delay))
6504	return ParseStatus::Failure;	6504	return ParseStatus::Failure;
6505	} while (trySkipToken(AsmToken::Pipe));	6505	} while (trySkipToken(AsmToken::Pipe));
6506	} else {	6506	} else {
6507	if (!parseExpr(Delay))	6507	if (!parseExpr(Delay))
6508	return ParseStatus::Failure;	6508	return ParseStatus::Failure;
6509	}	6509	}
6510		6510
6511	Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));	6511	Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));
6512	return ParseStatus::Success;	6512	return ParseStatus::Success;
6513	}	6513	}
6514		6514
6515	bool	6515	bool
6516	AMDGPUOperand::isSWaitCnt() const {	6516	AMDGPUOperand::isSWaitCnt() const {
6517	return isImm();	6517	return isImm();
6518	}	6518	}
6519		6519
6520	bool AMDGPUOperand::isSDelayALU() const { return isImm(); }	6520	bool AMDGPUOperand::isSDelayALU() const { return isImm(); }
6521		6521
6522	//===----------------------------------------------------------------------===//	6522	//===----------------------------------------------------------------------===//
6523	// DepCtr	6523	// DepCtr
6524	//===----------------------------------------------------------------------===//	6524	//===----------------------------------------------------------------------===//
6525		6525
6526	void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,	6526	void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,
6527	StringRef DepCtrName) {	6527	StringRef DepCtrName) {
6528	switch (ErrorId) {	6528	switch (ErrorId) {
6529	case OPR_ID_UNKNOWN:	6529	case OPR_ID_UNKNOWN:
6530	Error(Loc, Twine("invalid counter name ", DepCtrName));	6530	Error(Loc, Twine("invalid counter name ", DepCtrName));
6531	return;	6531	return;
6532	case OPR_ID_UNSUPPORTED:	6532	case OPR_ID_UNSUPPORTED:
6533	Error(Loc, Twine(DepCtrName, " is not supported on this GPU"));	6533	Error(Loc, Twine(DepCtrName, " is not supported on this GPU"));
6534	return;	6534	return;
6535	case OPR_ID_DUPLICATE:	6535	case OPR_ID_DUPLICATE:
6536	Error(Loc, Twine("duplicate counter name ", DepCtrName));	6536	Error(Loc, Twine("duplicate counter name ", DepCtrName));
6537	return;	6537	return;
6538	case OPR_VAL_INVALID:	6538	case OPR_VAL_INVALID:
6539	Error(Loc, Twine("invalid value for ", DepCtrName));	6539	Error(Loc, Twine("invalid value for ", DepCtrName));
6540	return;	6540	return;
6541	default:	6541	default:
6542	assert(false);	6542	assert(false);
6543	}	6543	}
6544	}	6544	}
6545		6545
6546	bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {	6546	bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {
6547		6547
6548	using namespace llvm::AMDGPU::DepCtr;	6548	using namespace llvm::AMDGPU::DepCtr;
6549		6549
6550	SMLoc DepCtrLoc = getLoc();	6550	SMLoc DepCtrLoc = getLoc();
6551	StringRef DepCtrName = getTokenStr();	6551	StringRef DepCtrName = getTokenStr();
6552		6552
6553	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	6553	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|
6554	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	6554	!skipToken(AsmToken::LParen, "expected a left parenthesis"))
6555	return false;	6555	return false;
6556		6556
6557	int64_t ExprVal;	6557	int64_t ExprVal;
6558	if (!parseExpr(ExprVal))	6558	if (!parseExpr(ExprVal))
6559	return false;	6559	return false;
6560		6560
6561	unsigned PrevOprMask = UsedOprMask;	6561	unsigned PrevOprMask = UsedOprMask;
6562	int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());	6562	int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());
6563		6563
6564	if (CntVal < 0) {	6564	if (CntVal < 0) {
6565	depCtrError(DepCtrLoc, CntVal, DepCtrName);	6565	depCtrError(DepCtrLoc, CntVal, DepCtrName);
6566	return false;	6566	return false;
6567	}	6567	}
6568		6568
6569	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	6569	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))
6570	return false;	6570	return false;
6571		6571
6572	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	6572	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {
6573	if (isToken(AsmToken::EndOfStatement)) {	6573	if (isToken(AsmToken::EndOfStatement)) {
6574	Error(getLoc(), "expected a counter name");	6574	Error(getLoc(), "expected a counter name");
6575	return false;	6575	return false;
6576	}	6576	}
6577	}	6577	}
6578		6578
6579	unsigned CntValMask = PrevOprMask ^ UsedOprMask;	6579	unsigned CntValMask = PrevOprMask ^ UsedOprMask;
6580	DepCtr = (DepCtr & ~CntValMask) \| CntVal;	6580	DepCtr = (DepCtr & ~CntValMask) \| CntVal;
6581	return true;	6581	return true;
6582	}	6582	}
6583		6583
6584	ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {	6584	ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {
6585	using namespace llvm::AMDGPU::DepCtr;	6585	using namespace llvm::AMDGPU::DepCtr;
6586		6586
6587	int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());	6587	int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());
6588	SMLoc Loc = getLoc();	6588	SMLoc Loc = getLoc();
6589		6589
6590	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	6590	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {
6591	unsigned UsedOprMask = 0;	6591	unsigned UsedOprMask = 0;
6592	while (!isToken(AsmToken::EndOfStatement)) {	6592	while (!isToken(AsmToken::EndOfStatement)) {
6593	if (!parseDepCtr(DepCtr, UsedOprMask))	6593	if (!parseDepCtr(DepCtr, UsedOprMask))
6594	return ParseStatus::Failure;	6594	return ParseStatus::Failure;
6595	}	6595	}
6596	} else {	6596	} else {
6597	if (!parseExpr(DepCtr))	6597	if (!parseExpr(DepCtr))
6598	return ParseStatus::Failure;	6598	return ParseStatus::Failure;
6599	}	6599	}
6600		6600
6601	Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));	6601	Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));
6602	return ParseStatus::Success;	6602	return ParseStatus::Success;
6603	}	6603	}
6604		6604
6605	bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }	6605	bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }
6606		6606
6607	//===----------------------------------------------------------------------===//	6607	//===----------------------------------------------------------------------===//
6608	// hwreg	6608	// hwreg
6609	//===----------------------------------------------------------------------===//	6609	//===----------------------------------------------------------------------===//
6610		6610
6611	bool	6611	bool
6612	AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,	6612	AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,
6613	OperandInfoTy &Offset,	6613	OperandInfoTy &Offset,
6614	OperandInfoTy &Width) {	6614	OperandInfoTy &Width) {
6615	using namespace llvm::AMDGPU::Hwreg;	6615	using namespace llvm::AMDGPU::Hwreg;
6616		6616
6617	// The register may be specified by name or using a numeric code	6617	// The register may be specified by name or using a numeric code
6618	HwReg.Loc = getLoc();	6618	HwReg.Loc = getLoc();
6619	if (isToken(AsmToken::Identifier) &&	6619	if (isToken(AsmToken::Identifier) &&
6620	(HwReg.Id = getHwregId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	6620	(HwReg.Id = getHwregId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {
6621	HwReg.IsSymbolic = true;	6621	HwReg.IsSymbolic = true;
6622	lex(); // skip register name	6622	lex(); // skip register name
6623	} else if (!parseExpr(HwReg.Id, "a register name")) {	6623	} else if (!parseExpr(HwReg.Id, "a register name")) {
6624	return false;	6624	return false;
6625	}	6625	}
6626		6626
6627	if (trySkipToken(AsmToken::RParen))	6627	if (trySkipToken(AsmToken::RParen))
6628	return true;	6628	return true;
6629		6629
6630	// parse optional params	6630	// parse optional params
6631	if (!skipToken(AsmToken::Comma, "expected a comma or a closing parenthesis"))	6631	if (!skipToken(AsmToken::Comma, "expected a comma or a closing parenthesis"))
6632	return false;	6632	return false;
6633		6633
6634	Offset.Loc = getLoc();	6634	Offset.Loc = getLoc();
6635	if (!parseExpr(Offset.Id))	6635	if (!parseExpr(Offset.Id))
6636	return false;	6636	return false;
6637		6637
6638	if (!skipToken(AsmToken::Comma, "expected a comma"))	6638	if (!skipToken(AsmToken::Comma, "expected a comma"))
6639	return false;	6639	return false;
6640		6640
6641	Width.Loc = getLoc();	6641	Width.Loc = getLoc();
6642	return parseExpr(Width.Id) &&	6642	return parseExpr(Width.Id) &&
6643	skipToken(AsmToken::RParen, "expected a closing parenthesis");	6643	skipToken(AsmToken::RParen, "expected a closing parenthesis");
6644	}	6644	}
6645		6645
6646	bool	6646	bool
6647	AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,	6647	AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,
6648	const OperandInfoTy &Offset,	6648	const OperandInfoTy &Offset,
6649	const OperandInfoTy &Width) {	6649	const OperandInfoTy &Width) {
6650		6650
6651	using namespace llvm::AMDGPU::Hwreg;	6651	using namespace llvm::AMDGPU::Hwreg;
6652		6652
6653	if (HwReg.IsSymbolic) {	6653	if (HwReg.IsSymbolic) {
6654	if (HwReg.Id == OPR_ID_UNSUPPORTED) {	6654	if (HwReg.Id == OPR_ID_UNSUPPORTED) {
6655	Error(HwReg.Loc,	6655	Error(HwReg.Loc,
6656	"specified hardware register is not supported on this GPU");	6656	"specified hardware register is not supported on this GPU");
6657	return false;	6657	return false;
6658	}	6658	}
6659	} else {	6659	} else {
6660	if (!isValidHwreg(HwReg.Id)) {	6660	if (!isValidHwreg(HwReg.Id)) {
6661	Error(HwReg.Loc,	6661	Error(HwReg.Loc,
6662	"invalid code of hardware register: only 6-bit values are legal");	6662	"invalid code of hardware register: only 6-bit values are legal");
6663	return false;	6663	return false;
6664	}	6664	}
6665	}	6665	}
6666	if (!isValidHwregOffset(Offset.Id)) {	6666	if (!isValidHwregOffset(Offset.Id)) {
6667	Error(Offset.Loc, "invalid bit offset: only 5-bit values are legal");	6667	Error(Offset.Loc, "invalid bit offset: only 5-bit values are legal");
6668	return false;	6668	return false;
6669	}	6669	}
6670	if (!isValidHwregWidth(Width.Id)) {	6670	if (!isValidHwregWidth(Width.Id)) {
6671	Error(Width.Loc,	6671	Error(Width.Loc,
6672	"invalid bitfield width: only values from 1 to 32 are legal");	6672	"invalid bitfield width: only values from 1 to 32 are legal");
6673	return false;	6673	return false;
6674	}	6674	}
6675	return true;	6675	return true;
6676	}	6676	}
6677		6677
6678	ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {	6678	ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
6679	using namespace llvm::AMDGPU::Hwreg;	6679	using namespace llvm::AMDGPU::Hwreg;
6680		6680
6681	int64_t ImmVal = 0;	6681	int64_t ImmVal = 0;
6682	SMLoc Loc = getLoc();	6682	SMLoc Loc = getLoc();
6683		6683
6684	if (trySkipId("hwreg", AsmToken::LParen)) {	6684	if (trySkipId("hwreg", AsmToken::LParen)) {
6685	OperandInfoTy HwReg(OPR_ID_UNKNOWN);	6685	OperandInfoTy HwReg(OPR_ID_UNKNOWN);
6686	OperandInfoTy Offset(OFFSET_DEFAULT_);	6686	OperandInfoTy Offset(OFFSET_DEFAULT_);
6687	OperandInfoTy Width(WIDTH_DEFAULT_);	6687	OperandInfoTy Width(WIDTH_DEFAULT_);
6688	if (parseHwregBody(HwReg, Offset, Width) &&	6688	if (parseHwregBody(HwReg, Offset, Width) &&
6689	validateHwreg(HwReg, Offset, Width)) {	6689	validateHwreg(HwReg, Offset, Width)) {
6690	ImmVal = encodeHwreg(HwReg.Id, Offset.Id, Width.Id);	6690	ImmVal = encodeHwreg(HwReg.Id, Offset.Id, Width.Id);
6691	} else {	6691	} else {
6692	return ParseStatus::Failure;	6692	return ParseStatus::Failure;
6693	}	6693	}
6694	} else if (parseExpr(ImmVal, "a hwreg macro")) {	6694	} else if (parseExpr(ImmVal, "a hwreg macro")) {
6695	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	6695	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))
6696	return Error(Loc, "invalid immediate: only 16-bit values are legal");	6696	return Error(Loc, "invalid immediate: only 16-bit values are legal");
6697	} else {	6697	} else {
6698	return ParseStatus::Failure;	6698	return ParseStatus::Failure;
6699	}	6699	}
6700		6700
6701	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg));	6701	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg));
6702	return ParseStatus::Success;	6702	return ParseStatus::Success;
6703	}	6703	}
6704		6704
6705	bool AMDGPUOperand::isHwreg() const {	6705	bool AMDGPUOperand::isHwreg() const {
6706	return isImmTy(ImmTyHwreg);	6706	return isImmTy(ImmTyHwreg);
6707	}	6707	}
6708		6708
6709	//===----------------------------------------------------------------------===//	6709	//===----------------------------------------------------------------------===//
6710	// sendmsg	6710	// sendmsg
6711	//===----------------------------------------------------------------------===//	6711	//===----------------------------------------------------------------------===//
6712		6712
6713	bool	6713	bool
6714	AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,	6714	AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,
6715	OperandInfoTy &Op,	6715	OperandInfoTy &Op,
6716	OperandInfoTy &Stream) {	6716	OperandInfoTy &Stream) {
6717	using namespace llvm::AMDGPU::SendMsg;	6717	using namespace llvm::AMDGPU::SendMsg;
6718		6718
6719	Msg.Loc = getLoc();	6719	Msg.Loc = getLoc();
6720	if (isToken(AsmToken::Identifier) &&	6720	if (isToken(AsmToken::Identifier) &&
6721	(Msg.Id = getMsgId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	6721	(Msg.Id = getMsgId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {
6722	Msg.IsSymbolic = true;	6722	Msg.IsSymbolic = true;
6723	lex(); // skip message name	6723	lex(); // skip message name
6724	} else if (!parseExpr(Msg.Id, "a message name")) {	6724	} else if (!parseExpr(Msg.Id, "a message name")) {
6725	return false;	6725	return false;
6726	}	6726	}
6727		6727
6728	if (trySkipToken(AsmToken::Comma)) {	6728	if (trySkipToken(AsmToken::Comma)) {
6729	Op.IsDefined = true;	6729	Op.IsDefined = true;
6730	Op.Loc = getLoc();	6730	Op.Loc = getLoc();
6731	if (isToken(AsmToken::Identifier) &&	6731	if (isToken(AsmToken::Identifier) &&
6732	(Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {	6732	(Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {
6733	lex(); // skip operation name	6733	lex(); // skip operation name
6734	} else if (!parseExpr(Op.Id, "an operation name")) {	6734	} else if (!parseExpr(Op.Id, "an operation name")) {
6735	return false;	6735	return false;
6736	}	6736	}
6737		6737
6738	if (trySkipToken(AsmToken::Comma)) {	6738	if (trySkipToken(AsmToken::Comma)) {
6739	Stream.IsDefined = true;	6739	Stream.IsDefined = true;
6740	Stream.Loc = getLoc();	6740	Stream.Loc = getLoc();
6741	if (!parseExpr(Stream.Id))	6741	if (!parseExpr(Stream.Id))
6742	return false;	6742	return false;
6743	}	6743	}
6744	}	6744	}
6745		6745
6746	return skipToken(AsmToken::RParen, "expected a closing parenthesis");	6746	return skipToken(AsmToken::RParen, "expected a closing parenthesis");
6747	}	6747	}
6748		6748
6749	bool	6749	bool
6750	AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,	6750	AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,
6751	const OperandInfoTy &Op,	6751	const OperandInfoTy &Op,
6752	const OperandInfoTy &Stream) {	6752	const OperandInfoTy &Stream) {
6753	using namespace llvm::AMDGPU::SendMsg;	6753	using namespace llvm::AMDGPU::SendMsg;
6754		6754
6755	// Validation strictness depends on whether message is specified	6755	// Validation strictness depends on whether message is specified
6756	// in a symbolic or in a numeric form. In the latter case	6756	// in a symbolic or in a numeric form. In the latter case
6757	// only encoding possibility is checked.	6757	// only encoding possibility is checked.
6758	bool Strict = Msg.IsSymbolic;	6758	bool Strict = Msg.IsSymbolic;
6759		6759
6760	if (Strict) {	6760	if (Strict) {
6761	if (Msg.Id == OPR_ID_UNSUPPORTED) {	6761	if (Msg.Id == OPR_ID_UNSUPPORTED) {
6762	Error(Msg.Loc, "specified message id is not supported on this GPU");	6762	Error(Msg.Loc, "specified message id is not supported on this GPU");
6763	return false;	6763	return false;
6764	}	6764	}
6765	} else {	6765	} else {
6766	if (!isValidMsgId(Msg.Id, getSTI())) {	6766	if (!isValidMsgId(Msg.Id, getSTI())) {
6767	Error(Msg.Loc, "invalid message id");	6767	Error(Msg.Loc, "invalid message id");
6768	return false;	6768	return false;
6769	}	6769	}
6770	}	6770	}
6771	if (Strict && (msgRequiresOp(Msg.Id, getSTI()) != Op.IsDefined)) {	6771	if (Strict && (msgRequiresOp(Msg.Id, getSTI()) != Op.IsDefined)) {
6772	if (Op.IsDefined) {	6772	if (Op.IsDefined) {
6773	Error(Op.Loc, "message does not support operations");	6773	Error(Op.Loc, "message does not support operations");
6774	} else {	6774	} else {
6775	Error(Msg.Loc, "missing message operation");	6775	Error(Msg.Loc, "missing message operation");
6776	}	6776	}
6777	return false;	6777	return false;
6778	}	6778	}
6779	if (!isValidMsgOp(Msg.Id, Op.Id, getSTI(), Strict)) {	6779	if (!isValidMsgOp(Msg.Id, Op.Id, getSTI(), Strict)) {
6780	Error(Op.Loc, "invalid operation id");	6780	Error(Op.Loc, "invalid operation id");
6781	return false;	6781	return false;
6782	}	6782	}
6783	if (Strict && !msgSupportsStream(Msg.Id, Op.Id, getSTI()) &&	6783	if (Strict && !msgSupportsStream(Msg.Id, Op.Id, getSTI()) &&
6784	Stream.IsDefined) {	6784	Stream.IsDefined) {
6785	Error(Stream.Loc, "message operation does not support streams");	6785	Error(Stream.Loc, "message operation does not support streams");
6786	return false;	6786	return false;
6787	}	6787	}
6788	if (!isValidMsgStream(Msg.Id, Op.Id, Stream.Id, getSTI(), Strict)) {	6788	if (!isValidMsgStream(Msg.Id, Op.Id, Stream.Id, getSTI(), Strict)) {
6789	Error(Stream.Loc, "invalid message stream id");	6789	Error(Stream.Loc, "invalid message stream id");
6790	return false;	6790	return false;
6791	}	6791	}
6792	return true;	6792	return true;
6793	}	6793	}
6794		6794
6795	ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {	6795	ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {
6796	using namespace llvm::AMDGPU::SendMsg;	6796	using namespace llvm::AMDGPU::SendMsg;
6797		6797
6798	int64_t ImmVal = 0;	6798	int64_t ImmVal = 0;
6799	SMLoc Loc = getLoc();	6799	SMLoc Loc = getLoc();
6800		6800
6801	if (trySkipId("sendmsg", AsmToken::LParen)) {	6801	if (trySkipId("sendmsg", AsmToken::LParen)) {
6802	OperandInfoTy Msg(OPR_ID_UNKNOWN);	6802	OperandInfoTy Msg(OPR_ID_UNKNOWN);
6803	OperandInfoTy Op(OP_NONE_);	6803	OperandInfoTy Op(OP_NONE_);
6804	OperandInfoTy Stream(STREAM_ID_NONE_);	6804	OperandInfoTy Stream(STREAM_ID_NONE_);
6805	if (parseSendMsgBody(Msg, Op, Stream) &&	6805	if (parseSendMsgBody(Msg, Op, Stream) &&
6806	validateSendMsg(Msg, Op, Stream)) {	6806	validateSendMsg(Msg, Op, Stream)) {
6807	ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id);	6807	ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id);
6808	} else {	6808	} else {
6809	return ParseStatus::Failure;	6809	return ParseStatus::Failure;
6810	}	6810	}
6811	} else if (parseExpr(ImmVal, "a sendmsg macro")) {	6811	} else if (parseExpr(ImmVal, "a sendmsg macro")) {
6812	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	6812	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))
6813	return Error(Loc, "invalid immediate: only 16-bit values are legal");	6813	return Error(Loc, "invalid immediate: only 16-bit values are legal");
6814	} else {	6814	} else {
6815	return ParseStatus::Failure;	6815	return ParseStatus::Failure;
6816	}	6816	}
6817		6817
6818	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));	6818	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));
6819	return ParseStatus::Success;	6819	return ParseStatus::Success;
6820	}	6820	}
6821		6821
6822	bool AMDGPUOperand::isSendMsg() const {	6822	bool AMDGPUOperand::isSendMsg() const {
6823	return isImmTy(ImmTySendMsg);	6823	return isImmTy(ImmTySendMsg);
6824	}	6824	}
6825		6825
6826	//===----------------------------------------------------------------------===//	6826	//===----------------------------------------------------------------------===//
6827	// v_interp	6827	// v_interp
6828	//===----------------------------------------------------------------------===//	6828	//===----------------------------------------------------------------------===//
6829		6829
6830	ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {	6830	ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {
6831	StringRef Str;	6831	StringRef Str;
6832	SMLoc S = getLoc();	6832	SMLoc S = getLoc();
6833		6833
6834	if (!parseId(Str))	6834	if (!parseId(Str))
6835	return ParseStatus::NoMatch;	6835	return ParseStatus::NoMatch;
6836		6836
6837	int Slot = StringSwitch(Str)	6837	int Slot = StringSwitch(Str)
6838	.Case("p10", 0)	6838	.Case("p10", 0)
6839	.Case("p20", 1)	6839	.Case("p20", 1)
6840	.Case("p0", 2)	6840	.Case("p0", 2)
6841	.Default(-1);	6841	.Default(-1);
6842		6842
6843	if (Slot == -1)	6843	if (Slot == -1)
6844	return Error(S, "invalid interpolation slot");	6844	return Error(S, "invalid interpolation slot");
6845		6845
6846	Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,	6846	Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,
6847	AMDGPUOperand::ImmTyInterpSlot));	6847	AMDGPUOperand::ImmTyInterpSlot));
6848	return ParseStatus::Success;	6848	return ParseStatus::Success;
6849	}	6849	}
6850		6850
6851	ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {	6851	ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {
6852	StringRef Str;	6852	StringRef Str;
6853	SMLoc S = getLoc();	6853	SMLoc S = getLoc();
6854		6854
6855	if (!parseId(Str))	6855	if (!parseId(Str))
6856	return ParseStatus::NoMatch;	6856	return ParseStatus::NoMatch;
6857		6857
6858	if (!Str.startswith("attr"))	6858	if (!Str.startswith("attr"))
6859	return Error(S, "invalid interpolation attribute");	6859	return Error(S, "invalid interpolation attribute");
6860		6860
6861	StringRef Chan = Str.take_back(2);	6861	StringRef Chan = Str.take_back(2);
6862	int AttrChan = StringSwitch(Chan)	6862	int AttrChan = StringSwitch(Chan)
6863	.Case(".x", 0)	6863	.Case(".x", 0)
6864	.Case(".y", 1)	6864	.Case(".y", 1)
6865	.Case(".z", 2)	6865	.Case(".z", 2)
6866	.Case(".w", 3)	6866	.Case(".w", 3)
6867	.Default(-1);	6867	.Default(-1);
6868	if (AttrChan == -1)	6868	if (AttrChan == -1)
6869	return Error(S, "invalid or missing interpolation attribute channel");	6869	return Error(S, "invalid or missing interpolation attribute channel");
6870		6870
6871	Str = Str.drop_back(2).drop_front(4);	6871	Str = Str.drop_back(2).drop_front(4);
6872		6872
6873	uint8_t Attr;	6873	uint8_t Attr;
6874	if (Str.getAsInteger(10, Attr))	6874	if (Str.getAsInteger(10, Attr))
6875	return Error(S, "invalid or missing interpolation attribute number");	6875	return Error(S, "invalid or missing interpolation attribute number");
6876		6876
6877	if (Attr > 32)	6877	if (Attr > 32)
6878	return Error(S, "out of bounds interpolation attribute number");	6878	return Error(S, "out of bounds interpolation attribute number");
6879		6879
6880	SMLoc SChan = SMLoc::getFromPointer(Chan.data());	6880	SMLoc SChan = SMLoc::getFromPointer(Chan.data());
6881		6881
6882	Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,	6882	Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,
6883	AMDGPUOperand::ImmTyInterpAttr));	6883	AMDGPUOperand::ImmTyInterpAttr));
6884	Operands.push_back(AMDGPUOperand::CreateImm(	6884	Operands.push_back(AMDGPUOperand::CreateImm(
6885	this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));	6885	this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));
6886	return ParseStatus::Success;	6886	return ParseStatus::Success;
6887	}	6887	}
6888		6888
6889	//===----------------------------------------------------------------------===//	6889	//===----------------------------------------------------------------------===//
6890	// exp	6890	// exp
6891	//===----------------------------------------------------------------------===//	6891	//===----------------------------------------------------------------------===//
6892		6892
6893	ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {	6893	ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {
6894	using namespace llvm::AMDGPU::Exp;	6894	using namespace llvm::AMDGPU::Exp;
6895		6895
6896	StringRef Str;	6896	StringRef Str;
6897	SMLoc S = getLoc();	6897	SMLoc S = getLoc();
6898		6898
6899	if (!parseId(Str))	6899	if (!parseId(Str))
6900	return ParseStatus::NoMatch;	6900	return ParseStatus::NoMatch;
6901		6901
6902	unsigned Id = getTgtId(Str);	6902	unsigned Id = getTgtId(Str);
6903	if (Id == ET_INVALID \|\| !isSupportedTgtId(Id, getSTI()))	6903	if (Id == ET_INVALID \|\| !isSupportedTgtId(Id, getSTI()))
6904	return Error(S, (Id == ET_INVALID)	6904	return Error(S, (Id == ET_INVALID)
6905	? "invalid exp target"	6905	? "invalid exp target"
6906	: "exp target is not supported on this GPU");	6906	: "exp target is not supported on this GPU");
6907		6907
6908	Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,	6908	Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,
6909	AMDGPUOperand::ImmTyExpTgt));	6909	AMDGPUOperand::ImmTyExpTgt));
6910	return ParseStatus::Success;	6910	return ParseStatus::Success;
6911	}	6911	}
6912		6912
6913	//===----------------------------------------------------------------------===//	6913	//===----------------------------------------------------------------------===//
6914	// parser helpers	6914	// parser helpers
6915	//===----------------------------------------------------------------------===//	6915	//===----------------------------------------------------------------------===//
6916		6916
6917	bool	6917	bool
6918	AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {	6918	AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {
6919	return Token.is(AsmToken::Identifier) && Token.getString() == Id;	6919	return Token.is(AsmToken::Identifier) && Token.getString() == Id;
6920	}	6920	}
6921		6921
6922	bool	6922	bool
6923	AMDGPUAsmParser::isId(const StringRef Id) const {	6923	AMDGPUAsmParser::isId(const StringRef Id) const {
6924	return isId(getToken(), Id);	6924	return isId(getToken(), Id);
6925	}	6925	}
6926		6926
6927	bool	6927	bool
6928	AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {	6928	AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {
6929	return getTokenKind() == Kind;	6929	return getTokenKind() == Kind;
6930	}	6930	}
6931		6931
6932	StringRef AMDGPUAsmParser::getId() const {	6932	StringRef AMDGPUAsmParser::getId() const {
6933	return isToken(AsmToken::Identifier) ? getTokenStr() : StringRef();	6933	return isToken(AsmToken::Identifier) ? getTokenStr() : StringRef();
6934	}	6934	}
6935		6935
6936	bool	6936	bool
6937	AMDGPUAsmParser::trySkipId(const StringRef Id) {	6937	AMDGPUAsmParser::trySkipId(const StringRef Id) {
6938	if (isId(Id)) {	6938	if (isId(Id)) {
6939	lex();	6939	lex();
6940	return true;	6940	return true;
6941	}	6941	}
6942	return false;	6942	return false;
6943	}	6943	}
6944		6944
6945	bool	6945	bool
6946	AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {	6946	AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {
6947	if (isToken(AsmToken::Identifier)) {	6947	if (isToken(AsmToken::Identifier)) {
6948	StringRef Tok = getTokenStr();	6948	StringRef Tok = getTokenStr();
6949	if (Tok.startswith(Pref) && Tok.drop_front(Pref.size()) == Id) {	6949	if (Tok.startswith(Pref) && Tok.drop_front(Pref.size()) == Id) {
6950	lex();	6950	lex();
6951	return true;	6951	return true;
6952	}	6952	}
6953	}	6953	}
6954	return false;	6954	return false;
6955	}	6955	}
6956		6956
6957	bool	6957	bool
6958	AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {	6958	AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {
6959	if (isId(Id) && peekToken().is(Kind)) {	6959	if (isId(Id) && peekToken().is(Kind)) {
6960	lex();	6960	lex();
6961	lex();	6961	lex();
6962	return true;	6962	return true;
6963	}	6963	}
6964	return false;	6964	return false;
6965	}	6965	}
6966		6966
6967	bool	6967	bool
6968	AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {	6968	AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {
6969	if (isToken(Kind)) {	6969	if (isToken(Kind)) {
6970	lex();	6970	lex();
6971	return true;	6971	return true;
6972	}	6972	}
6973	return false;	6973	return false;
6974	}	6974	}
6975		6975
6976	bool	6976	bool
6977	AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,	6977	AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,
6978	const StringRef ErrMsg) {	6978	const StringRef ErrMsg) {
6979	if (!trySkipToken(Kind)) {	6979	if (!trySkipToken(Kind)) {
6980	Error(getLoc(), ErrMsg);	6980	Error(getLoc(), ErrMsg);
6981	return false;	6981	return false;
6982	}	6982	}
6983	return true;	6983	return true;
6984	}	6984	}
6985		6985
6986	bool	6986	bool
6987	AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {	6987	AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {
6988	SMLoc S = getLoc();	6988	SMLoc S = getLoc();
6989		6989
6990	const MCExpr *Expr;	6990	const MCExpr *Expr;
6991	if (Parser.parseExpression(Expr))	6991	if (Parser.parseExpression(Expr))
6992	return false;	6992	return false;
6993		6993
6994	if (Expr->evaluateAsAbsolute(Imm))	6994	if (Expr->evaluateAsAbsolute(Imm))
6995	return true;	6995	return true;
6996		6996
6997	if (Expected.empty()) {	6997	if (Expected.empty()) {
6998	Error(S, "expected absolute expression");	6998	Error(S, "expected absolute expression");
6999	} else {	6999	} else {
7000	Error(S, Twine("expected ", Expected) +	7000	Error(S, Twine("expected ", Expected) +
7001	Twine(" or an absolute expression"));	7001	Twine(" or an absolute expression"));
7002	}	7002	}
7003	return false;	7003	return false;
7004	}	7004	}
7005		7005
7006	bool	7006	bool
7007	AMDGPUAsmParser::parseExpr(OperandVector &Operands) {	7007	AMDGPUAsmParser::parseExpr(OperandVector &Operands) {
7008	SMLoc S = getLoc();	7008	SMLoc S = getLoc();
7009		7009
7010	const MCExpr *Expr;	7010	const MCExpr *Expr;
7011	if (Parser.parseExpression(Expr))	7011	if (Parser.parseExpression(Expr))
7012	return false;	7012	return false;
7013		7013
7014	int64_t IntVal;	7014	int64_t IntVal;
7015	if (Expr->evaluateAsAbsolute(IntVal)) {	7015	if (Expr->evaluateAsAbsolute(IntVal)) {
7016	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	7016	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));
7017	} else {	7017	} else {
7018	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	7018	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));
7019	}	7019	}
7020	return true;	7020	return true;
7021	}	7021	}
7022		7022
7023	bool	7023	bool
7024	AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {	7024	AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {
7025	if (isToken(AsmToken::String)) {	7025	if (isToken(AsmToken::String)) {
7026	Val = getToken().getStringContents();	7026	Val = getToken().getStringContents();
7027	lex();	7027	lex();
7028	return true;	7028	return true;
7029	} else {	7029	} else {
7030	Error(getLoc(), ErrMsg);	7030	Error(getLoc(), ErrMsg);
7031	return false;	7031	return false;
7032	}	7032	}
7033	}	7033	}
7034		7034
7035	bool	7035	bool
7036	AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {	7036	AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {
7037	if (isToken(AsmToken::Identifier)) {	7037	if (isToken(AsmToken::Identifier)) {
7038	Val = getTokenStr();	7038	Val = getTokenStr();
7039	lex();	7039	lex();
7040	return true;	7040	return true;
7041	} else {	7041	} else {
7042	if (!ErrMsg.empty())	7042	if (!ErrMsg.empty())
7043	Error(getLoc(), ErrMsg);	7043	Error(getLoc(), ErrMsg);
7044	return false;	7044	return false;
7045	}	7045	}
7046	}	7046	}
7047		7047
7048	AsmToken	7048	AsmToken
7049	AMDGPUAsmParser::getToken() const {	7049	AMDGPUAsmParser::getToken() const {
7050	return Parser.getTok();	7050	return Parser.getTok();
7051	}	7051	}
7052		7052
7053	AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {	7053	AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {
7054	return isToken(AsmToken::EndOfStatement)	7054	return isToken(AsmToken::EndOfStatement)
7055	? getToken()	7055	? getToken()
7056	: getLexer().peekTok(ShouldSkipSpace);	7056	: getLexer().peekTok(ShouldSkipSpace);
7057	}	7057	}
7058		7058
7059	void	7059	void
7060	AMDGPUAsmParser::peekTokens(MutableArrayRef Tokens) {	7060	AMDGPUAsmParser::peekTokens(MutableArrayRef Tokens) {
7061	auto TokCount = getLexer().peekTokens(Tokens);	7061	auto TokCount = getLexer().peekTokens(Tokens);
7062		7062
7063	for (auto Idx = TokCount; Idx < Tokens.size(); ++Idx)	7063	for (auto Idx = TokCount; Idx < Tokens.size(); ++Idx)
7064	Tokens[Idx] = AsmToken(AsmToken::Error, "");	7064	Tokens[Idx] = AsmToken(AsmToken::Error, "");
7065	}	7065	}
7066		7066
7067	AsmToken::TokenKind	7067	AsmToken::TokenKind
7068	AMDGPUAsmParser::getTokenKind() const {	7068	AMDGPUAsmParser::getTokenKind() const {
7069	return getLexer().getKind();	7069	return getLexer().getKind();
7070	}	7070	}
7071		7071
7072	SMLoc	7072	SMLoc
7073	AMDGPUAsmParser::getLoc() const {	7073	AMDGPUAsmParser::getLoc() const {
7074	return getToken().getLoc();	7074	return getToken().getLoc();
7075	}	7075	}
7076		7076
7077	StringRef	7077	StringRef
7078	AMDGPUAsmParser::getTokenStr() const {	7078	AMDGPUAsmParser::getTokenStr() const {
7079	return getToken().getString();	7079	return getToken().getString();
7080	}	7080	}
7081		7081
7082	void	7082	void
7083	AMDGPUAsmParser::lex() {	7083	AMDGPUAsmParser::lex() {
7084	Parser.Lex();	7084	Parser.Lex();
7085	}	7085	}
7086		7086
7087	SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {	7087	SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {
7088	return ((AMDGPUOperand &)*Operands[0]).getStartLoc();	7088	return ((AMDGPUOperand &)*Operands[0]).getStartLoc();
7089	}	7089	}
7090		7090
7091	SMLoc	7091	SMLoc
7092	AMDGPUAsmParser::getOperandLoc(std::function Test,	7092	AMDGPUAsmParser::getOperandLoc(std::function Test,
7093	const OperandVector &Operands) const {	7093	const OperandVector &Operands) const {
7094	for (unsigned i = Operands.size() - 1; i > 0; --i) {	7094	for (unsigned i = Operands.size() - 1; i > 0; --i) {
7095	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	7095	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7096	if (Test(Op))	7096	if (Test(Op))
7097	return Op.getStartLoc();	7097	return Op.getStartLoc();
7098	}	7098	}
7099	return getInstLoc(Operands);	7099	return getInstLoc(Operands);
7100	}	7100	}
7101		7101
7102	SMLoc	7102	SMLoc
7103	AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,	7103	AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,
7104	const OperandVector &Operands) const {	7104	const OperandVector &Operands) const {
7105	auto Test = [=](const AMDGPUOperand& Op) { return Op.isImmTy(Type); };	7105	auto Test = [=](const AMDGPUOperand& Op) { return Op.isImmTy(Type); };
7106	return getOperandLoc(Test, Operands);	7106	return getOperandLoc(Test, Operands);
7107	}	7107	}
7108		7108
7109	SMLoc	7109	SMLoc
7110	AMDGPUAsmParser::getRegLoc(unsigned Reg,	7110	AMDGPUAsmParser::getRegLoc(unsigned Reg,
7111	const OperandVector &Operands) const {	7111	const OperandVector &Operands) const {
7112	auto Test = [=](const AMDGPUOperand& Op) {	7112	auto Test = [=](const AMDGPUOperand& Op) {
7113	return Op.isRegKind() && Op.getReg() == Reg;	7113	return Op.isRegKind() && Op.getReg() == Reg;
7114	};	7114	};
7115	return getOperandLoc(Test, Operands);	7115	return getOperandLoc(Test, Operands);
7116	}	7116	}
7117		7117
7118	SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,	7118	SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,
7119	bool SearchMandatoryLiterals) const {	7119	bool SearchMandatoryLiterals) const {
7120	auto Test = [](const AMDGPUOperand& Op) {	7120	auto Test = [](const AMDGPUOperand& Op) {
7121	return Op.IsImmKindLiteral() \|\| Op.isExpr();	7121	return Op.IsImmKindLiteral() \|\| Op.isExpr();
7122	};	7122	};
7123	SMLoc Loc = getOperandLoc(Test, Operands);	7123	SMLoc Loc = getOperandLoc(Test, Operands);
7124	if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))	7124	if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))
7125	Loc = getMandatoryLitLoc(Operands);	7125	Loc = getMandatoryLitLoc(Operands);
7126	return Loc;	7126	return Loc;
7127	}	7127	}
7128		7128
7129	SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {	7129	SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {
7130	auto Test = [](const AMDGPUOperand &Op) {	7130	auto Test = [](const AMDGPUOperand &Op) {
7131	return Op.IsImmKindMandatoryLiteral();	7131	return Op.IsImmKindMandatoryLiteral();
7132	};	7132	};
7133	return getOperandLoc(Test, Operands);	7133	return getOperandLoc(Test, Operands);
7134	}	7134	}
7135		7135
7136	SMLoc	7136	SMLoc
7137	AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {	7137	AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {
7138	auto Test = [](const AMDGPUOperand& Op) {	7138	auto Test = [](const AMDGPUOperand& Op) {
7139	return Op.isImmKindConst();	7139	return Op.isImmKindConst();
7140	};	7140	};
7141	return getOperandLoc(Test, Operands);	7141	return getOperandLoc(Test, Operands);
7142	}	7142	}
7143		7143
7144	//===----------------------------------------------------------------------===//	7144	//===----------------------------------------------------------------------===//
7145	// swizzle	7145	// swizzle
7146	//===----------------------------------------------------------------------===//	7146	//===----------------------------------------------------------------------===//
7147		7147
7148	LLVM_READNONE	7148	LLVM_READNONE
7149	static unsigned	7149	static unsigned
7150	encodeBitmaskPerm(const unsigned AndMask,	7150	encodeBitmaskPerm(const unsigned AndMask,
7151	const unsigned OrMask,	7151	const unsigned OrMask,
7152	const unsigned XorMask) {	7152	const unsigned XorMask) {
7153	using namespace llvm::AMDGPU::Swizzle;	7153	using namespace llvm::AMDGPU::Swizzle;
7154		7154
7155	return BITMASK_PERM_ENC \|	7155	return BITMASK_PERM_ENC \|
7156	(AndMask << BITMASK_AND_SHIFT) \|	7156	(AndMask << BITMASK_AND_SHIFT) \|
7157	(OrMask << BITMASK_OR_SHIFT) \|	7157	(OrMask << BITMASK_OR_SHIFT) \|
7158	(XorMask << BITMASK_XOR_SHIFT);	7158	(XorMask << BITMASK_XOR_SHIFT);
7159	}	7159	}
7160		7160
7161	bool	7161	bool
7162	AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,	7162	AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,
7163	const unsigned MinVal,	7163	const unsigned MinVal,
7164	const unsigned MaxVal,	7164	const unsigned MaxVal,
7165	const StringRef ErrMsg,	7165	const StringRef ErrMsg,
7166	SMLoc &Loc) {	7166	SMLoc &Loc) {
7167	if (!skipToken(AsmToken::Comma, "expected a comma")) {	7167	if (!skipToken(AsmToken::Comma, "expected a comma")) {
7168	return false;	7168	return false;
7169	}	7169	}
7170	Loc = getLoc();	7170	Loc = getLoc();
7171	if (!parseExpr(Op)) {	7171	if (!parseExpr(Op)) {
7172	return false;	7172	return false;
7173	}	7173	}
7174	if (Op < MinVal \|\| Op > MaxVal) {	7174	if (Op < MinVal \|\| Op > MaxVal) {
7175	Error(Loc, ErrMsg);	7175	Error(Loc, ErrMsg);
7176	return false;	7176	return false;
7177	}	7177	}
7178		7178
7179	return true;	7179	return true;
7180	}	7180	}
7181		7181
7182	bool	7182	bool
7183	AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	7183	AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,
7184	const unsigned MinVal,	7184	const unsigned MinVal,
7185	const unsigned MaxVal,	7185	const unsigned MaxVal,
7186	const StringRef ErrMsg) {	7186	const StringRef ErrMsg) {
7187	SMLoc Loc;	7187	SMLoc Loc;
7188	for (unsigned i = 0; i < OpNum; ++i) {	7188	for (unsigned i = 0; i < OpNum; ++i) {
7189	if (!parseSwizzleOperand(Op[i], MinVal, MaxVal, ErrMsg, Loc))	7189	if (!parseSwizzleOperand(Op[i], MinVal, MaxVal, ErrMsg, Loc))
7190	return false;	7190	return false;
7191	}	7191	}
7192		7192
7193	return true;	7193	return true;
7194	}	7194	}
7195		7195
7196	bool	7196	bool
7197	AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {	7197	AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {
7198	using namespace llvm::AMDGPU::Swizzle;	7198	using namespace llvm::AMDGPU::Swizzle;
7199		7199
7200	int64_t Lane[LANE_NUM];	7200	int64_t Lane[LANE_NUM];
7201	if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,	7201	if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,
7202	"expected a 2-bit lane id")) {	7202	"expected a 2-bit lane id")) {
7203	Imm = QUAD_PERM_ENC;	7203	Imm = QUAD_PERM_ENC;
7204	for (unsigned I = 0; I < LANE_NUM; ++I) {	7204	for (unsigned I = 0; I < LANE_NUM; ++I) {
7205	Imm \|= Lane[I] << (LANE_SHIFT * I);	7205	Imm \|= Lane[I] << (LANE_SHIFT * I);
7206	}	7206	}
7207	return true;	7207	return true;
7208	}	7208	}
7209	return false;	7209	return false;
7210	}	7210	}
7211		7211
7212	bool	7212	bool
7213	AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {	7213	AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {
7214	using namespace llvm::AMDGPU::Swizzle;	7214	using namespace llvm::AMDGPU::Swizzle;
7215		7215
7216	SMLoc Loc;	7216	SMLoc Loc;
7217	int64_t GroupSize;	7217	int64_t GroupSize;
7218	int64_t LaneIdx;	7218	int64_t LaneIdx;
7219		7219
7220	if (!parseSwizzleOperand(GroupSize,	7220	if (!parseSwizzleOperand(GroupSize,
7221	2, 32,	7221	2, 32,
7222	"group size must be in the interval [2,32]",	7222	"group size must be in the interval [2,32]",
7223	Loc)) {	7223	Loc)) {
7224	return false;	7224	return false;
7225	}	7225	}
7226	if (!isPowerOf2_64(GroupSize)) {	7226	if (!isPowerOf2_64(GroupSize)) {
7227	Error(Loc, "group size must be a power of two");	7227	Error(Loc, "group size must be a power of two");
7228	return false;	7228	return false;
7229	}	7229	}
7230	if (parseSwizzleOperand(LaneIdx,	7230	if (parseSwizzleOperand(LaneIdx,
7231	0, GroupSize - 1,	7231	0, GroupSize - 1,
7232	"lane id must be in the interval [0,group size - 1]",	7232	"lane id must be in the interval [0,group size - 1]",
7233	Loc)) {	7233	Loc)) {
7234	Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);	7234	Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);
7235	return true;	7235	return true;
7236	}	7236	}
7237	return false;	7237	return false;
7238	}	7238	}
7239		7239
7240	bool	7240	bool
7241	AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {	7241	AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {
7242	using namespace llvm::AMDGPU::Swizzle;	7242	using namespace llvm::AMDGPU::Swizzle;
7243		7243
7244	SMLoc Loc;	7244	SMLoc Loc;
7245	int64_t GroupSize;	7245	int64_t GroupSize;
7246		7246
7247	if (!parseSwizzleOperand(GroupSize,	7247	if (!parseSwizzleOperand(GroupSize,
7248	2, 32,	7248	2, 32,
7249	"group size must be in the interval [2,32]",	7249	"group size must be in the interval [2,32]",
7250	Loc)) {	7250	Loc)) {
7251	return false;	7251	return false;
7252	}	7252	}
7253	if (!isPowerOf2_64(GroupSize)) {	7253	if (!isPowerOf2_64(GroupSize)) {
7254	Error(Loc, "group size must be a power of two");	7254	Error(Loc, "group size must be a power of two");
7255	return false;	7255	return false;
7256	}	7256	}
7257		7257
7258	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);	7258	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);
7259	return true;	7259	return true;
7260	}	7260	}
7261		7261
7262	bool	7262	bool
7263	AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {	7263	AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {
7264	using namespace llvm::AMDGPU::Swizzle;	7264	using namespace llvm::AMDGPU::Swizzle;
7265		7265
7266	SMLoc Loc;	7266	SMLoc Loc;
7267	int64_t GroupSize;	7267	int64_t GroupSize;
7268		7268
7269	if (!parseSwizzleOperand(GroupSize,	7269	if (!parseSwizzleOperand(GroupSize,
7270	1, 16,	7270	1, 16,
7271	"group size must be in the interval [1,16]",	7271	"group size must be in the interval [1,16]",
7272	Loc)) {	7272	Loc)) {
7273	return false;	7273	return false;
7274	}	7274	}
7275	if (!isPowerOf2_64(GroupSize)) {	7275	if (!isPowerOf2_64(GroupSize)) {
7276	Error(Loc, "group size must be a power of two");	7276	Error(Loc, "group size must be a power of two");
7277	return false;	7277	return false;
7278	}	7278	}
7279		7279
7280	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize);	7280	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize);
7281	return true;	7281	return true;
7282	}	7282	}
7283		7283
7284	bool	7284	bool
7285	AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {	7285	AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {
7286	using namespace llvm::AMDGPU::Swizzle;	7286	using namespace llvm::AMDGPU::Swizzle;
7287		7287
7288	if (!skipToken(AsmToken::Comma, "expected a comma")) {	7288	if (!skipToken(AsmToken::Comma, "expected a comma")) {
7289	return false;	7289	return false;
7290	}	7290	}
7291		7291
7292	StringRef Ctl;	7292	StringRef Ctl;
7293	SMLoc StrLoc = getLoc();	7293	SMLoc StrLoc = getLoc();
7294	if (!parseString(Ctl)) {	7294	if (!parseString(Ctl)) {
7295	return false;	7295	return false;
7296	}	7296	}
7297	if (Ctl.size() != BITMASK_WIDTH) {	7297	if (Ctl.size() != BITMASK_WIDTH) {
7298	Error(StrLoc, "expected a 5-character mask");	7298	Error(StrLoc, "expected a 5-character mask");
7299	return false;	7299	return false;
7300	}	7300	}
7301		7301
7302	unsigned AndMask = 0;	7302	unsigned AndMask = 0;
7303	unsigned OrMask = 0;	7303	unsigned OrMask = 0;
7304	unsigned XorMask = 0;	7304	unsigned XorMask = 0;
7305		7305
7306	for (size_t i = 0; i < Ctl.size(); ++i) {	7306	for (size_t i = 0; i < Ctl.size(); ++i) {
7307	unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);	7307	unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);
7308	switch(Ctl[i]) {	7308	switch(Ctl[i]) {
7309	default:	7309	default:
7310	Error(StrLoc, "invalid mask");	7310	Error(StrLoc, "invalid mask");
7311	return false;	7311	return false;
7312	case '0':	7312	case '0':
7313	break;	7313	break;
7314	case '1':	7314	case '1':
7315	OrMask \|= Mask;	7315	OrMask \|= Mask;
7316	break;	7316	break;
7317	case 'p':	7317	case 'p':
7318	AndMask \|= Mask;	7318	AndMask \|= Mask;
7319	break;	7319	break;
7320	case 'i':	7320	case 'i':
7321	AndMask \|= Mask;	7321	AndMask \|= Mask;
7322	XorMask \|= Mask;	7322	XorMask \|= Mask;
7323	break;	7323	break;
7324	}	7324	}
7325	}	7325	}
7326		7326
7327	Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask);	7327	Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask);
7328	return true;	7328	return true;
7329	}	7329	}
7330		7330
7331	bool	7331	bool
7332	AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {	7332	AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {
7333		7333
7334	SMLoc OffsetLoc = getLoc();	7334	SMLoc OffsetLoc = getLoc();
7335		7335
7336	if (!parseExpr(Imm, "a swizzle macro")) {	7336	if (!parseExpr(Imm, "a swizzle macro")) {
7337	return false;	7337	return false;
7338	}	7338	}
7339	if (!isUInt<16>(Imm)) {	7339	if (!isUInt<16>(Imm)) {
7340	Error(OffsetLoc, "expected a 16-bit offset");	7340	Error(OffsetLoc, "expected a 16-bit offset");
7341	return false;	7341	return false;
7342	}	7342	}
7343	return true;	7343	return true;
7344	}	7344	}
7345		7345
7346	bool	7346	bool
7347	AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {	7347	AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {
7348	using namespace llvm::AMDGPU::Swizzle;	7348	using namespace llvm::AMDGPU::Swizzle;
7349		7349
7350	if (skipToken(AsmToken::LParen, "expected a left parentheses")) {	7350	if (skipToken(AsmToken::LParen, "expected a left parentheses")) {
7351		7351
7352	SMLoc ModeLoc = getLoc();	7352	SMLoc ModeLoc = getLoc();
7353	bool Ok = false;	7353	bool Ok = false;
7354		7354
7355	if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {	7355	if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {
7356	Ok = parseSwizzleQuadPerm(Imm);	7356	Ok = parseSwizzleQuadPerm(Imm);
7357	} else if (trySkipId(IdSymbolic[ID_BITMASK_PERM])) {	7357	} else if (trySkipId(IdSymbolic[ID_BITMASK_PERM])) {
7358	Ok = parseSwizzleBitmaskPerm(Imm);	7358	Ok = parseSwizzleBitmaskPerm(Imm);
7359	} else if (trySkipId(IdSymbolic[ID_BROADCAST])) {	7359	} else if (trySkipId(IdSymbolic[ID_BROADCAST])) {
7360	Ok = parseSwizzleBroadcast(Imm);	7360	Ok = parseSwizzleBroadcast(Imm);
7361	} else if (trySkipId(IdSymbolic[ID_SWAP])) {	7361	} else if (trySkipId(IdSymbolic[ID_SWAP])) {
7362	Ok = parseSwizzleSwap(Imm);	7362	Ok = parseSwizzleSwap(Imm);
7363	} else if (trySkipId(IdSymbolic[ID_REVERSE])) {	7363	} else if (trySkipId(IdSymbolic[ID_REVERSE])) {
7364	Ok = parseSwizzleReverse(Imm);	7364	Ok = parseSwizzleReverse(Imm);
7365	} else {	7365	} else {
7366	Error(ModeLoc, "expected a swizzle mode");	7366	Error(ModeLoc, "expected a swizzle mode");
7367	}	7367	}
7368		7368
7369	return Ok && skipToken(AsmToken::RParen, "expected a closing parentheses");	7369	return Ok && skipToken(AsmToken::RParen, "expected a closing parentheses");
7370	}	7370	}
7371		7371
7372	return false;	7372	return false;
7373	}	7373	}
7374		7374
7375	ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {	7375	ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {
7376	SMLoc S = getLoc();	7376	SMLoc S = getLoc();
7377	int64_t Imm = 0;	7377	int64_t Imm = 0;
7378		7378
7379	if (trySkipId("offset")) {	7379	if (trySkipId("offset")) {
7380		7380
7381	bool Ok = false;	7381	bool Ok = false;
7382	if (skipToken(AsmToken::Colon, "expected a colon")) {	7382	if (skipToken(AsmToken::Colon, "expected a colon")) {
7383	if (trySkipId("swizzle")) {	7383	if (trySkipId("swizzle")) {
7384	Ok = parseSwizzleMacro(Imm);	7384	Ok = parseSwizzleMacro(Imm);
7385	} else {	7385	} else {
7386	Ok = parseSwizzleOffset(Imm);	7386	Ok = parseSwizzleOffset(Imm);
7387	}	7387	}
7388	}	7388	}
7389		7389
7390	Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));	7390	Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));
7391		7391
7392	return Ok ? ParseStatus::Success : ParseStatus::Failure;	7392	return Ok ? ParseStatus::Success : ParseStatus::Failure;
7393	}	7393	}
7394	return ParseStatus::NoMatch;	7394	return ParseStatus::NoMatch;
7395	}	7395	}
7396		7396
7397	bool	7397	bool
7398	AMDGPUOperand::isSwizzle() const {	7398	AMDGPUOperand::isSwizzle() const {
7399	return isImmTy(ImmTySwizzle);	7399	return isImmTy(ImmTySwizzle);
7400	}	7400	}
7401		7401
7402	//===----------------------------------------------------------------------===//	7402	//===----------------------------------------------------------------------===//
7403	// VGPR Index Mode	7403	// VGPR Index Mode
7404	//===----------------------------------------------------------------------===//	7404	//===----------------------------------------------------------------------===//
7405		7405
7406	int64_t AMDGPUAsmParser::parseGPRIdxMacro() {	7406	int64_t AMDGPUAsmParser::parseGPRIdxMacro() {
7407		7407
7408	using namespace llvm::AMDGPU::VGPRIndexMode;	7408	using namespace llvm::AMDGPU::VGPRIndexMode;
7409		7409
7410	if (trySkipToken(AsmToken::RParen)) {	7410	if (trySkipToken(AsmToken::RParen)) {
7411	return OFF;	7411	return OFF;
7412	}	7412	}
7413		7413
7414	int64_t Imm = 0;	7414	int64_t Imm = 0;
7415		7415
7416	while (true) {	7416	while (true) {
7417	unsigned Mode = 0;	7417	unsigned Mode = 0;
7418	SMLoc S = getLoc();	7418	SMLoc S = getLoc();
7419		7419
7420	for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {	7420	for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {
7421	if (trySkipId(IdSymbolic[ModeId])) {	7421	if (trySkipId(IdSymbolic[ModeId])) {
7422	Mode = 1 << ModeId;	7422	Mode = 1 << ModeId;
7423	break;	7423	break;
7424	}	7424	}
7425	}	7425	}
7426		7426
7427	if (Mode == 0) {	7427	if (Mode == 0) {
7428	Error(S, (Imm == 0)?	7428	Error(S, (Imm == 0)?
7429	"expected a VGPR index mode or a closing parenthesis" :	7429	"expected a VGPR index mode or a closing parenthesis" :
7430	"expected a VGPR index mode");	7430	"expected a VGPR index mode");
7431	return UNDEF;	7431	return UNDEF;
7432	}	7432	}
7433		7433
7434	if (Imm & Mode) {	7434	if (Imm & Mode) {
7435	Error(S, "duplicate VGPR index mode");	7435	Error(S, "duplicate VGPR index mode");
7436	return UNDEF;	7436	return UNDEF;
7437	}	7437	}
7438	Imm \|= Mode;	7438	Imm \|= Mode;
7439		7439
7440	if (trySkipToken(AsmToken::RParen))	7440	if (trySkipToken(AsmToken::RParen))
7441	break;	7441	break;
7442	if (!skipToken(AsmToken::Comma,	7442	if (!skipToken(AsmToken::Comma,
7443	"expected a comma or a closing parenthesis"))	7443	"expected a comma or a closing parenthesis"))
7444	return UNDEF;	7444	return UNDEF;
7445	}	7445	}
7446		7446
7447	return Imm;	7447	return Imm;
7448	}	7448	}
7449		7449
7450	ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {	7450	ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {
7451		7451
7452	using namespace llvm::AMDGPU::VGPRIndexMode;	7452	using namespace llvm::AMDGPU::VGPRIndexMode;
7453		7453
7454	int64_t Imm = 0;	7454	int64_t Imm = 0;
7455	SMLoc S = getLoc();	7455	SMLoc S = getLoc();
7456		7456
7457	if (trySkipId("gpr_idx", AsmToken::LParen)) {	7457	if (trySkipId("gpr_idx", AsmToken::LParen)) {
7458	Imm = parseGPRIdxMacro();	7458	Imm = parseGPRIdxMacro();
7459	if (Imm == UNDEF)	7459	if (Imm == UNDEF)
7460	return ParseStatus::Failure;	7460	return ParseStatus::Failure;
7461	} else {	7461	} else {
7462	if (getParser().parseAbsoluteExpression(Imm))	7462	if (getParser().parseAbsoluteExpression(Imm))
7463	return ParseStatus::Failure;	7463	return ParseStatus::Failure;
7464	if (Imm < 0 \|\| !isUInt<4>(Imm))	7464	if (Imm < 0 \|\| !isUInt<4>(Imm))
7465	return Error(S, "invalid immediate: only 4-bit values are legal");	7465	return Error(S, "invalid immediate: only 4-bit values are legal");
7466	}	7466	}
7467		7467
7468	Operands.push_back(	7468	Operands.push_back(
7469	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode));	7469	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode));
7470	return ParseStatus::Success;	7470	return ParseStatus::Success;
7471	}	7471	}
7472		7472
7473	bool AMDGPUOperand::isGPRIdxMode() const {	7473	bool AMDGPUOperand::isGPRIdxMode() const {
7474	return isImmTy(ImmTyGprIdxMode);	7474	return isImmTy(ImmTyGprIdxMode);
7475	}	7475	}
7476		7476
7477	//===----------------------------------------------------------------------===//	7477	//===----------------------------------------------------------------------===//
7478	// sopp branch targets	7478	// sopp branch targets
7479	//===----------------------------------------------------------------------===//	7479	//===----------------------------------------------------------------------===//
7480		7480
7481	ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {	7481	ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {
7482		7482
7483	// Make sure we are not parsing something	7483	// Make sure we are not parsing something
7484	// that looks like a label or an expression but is not.	7484	// that looks like a label or an expression but is not.
7485	// This will improve error messages.	7485	// This will improve error messages.
7486	if (isRegister() \|\| isModifier())	7486	if (isRegister() \|\| isModifier())
7487	return ParseStatus::NoMatch;	7487	return ParseStatus::NoMatch;
7488		7488
7489	if (!parseExpr(Operands))	7489	if (!parseExpr(Operands))
7490	return ParseStatus::Failure;	7490	return ParseStatus::Failure;
7491		7491
7492	AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);	7492	AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);
7493	assert(Opr.isImm() \|\| Opr.isExpr());	7493	assert(Opr.isImm() \|\| Opr.isExpr());
7494	SMLoc Loc = Opr.getStartLoc();	7494	SMLoc Loc = Opr.getStartLoc();
7495		7495
7496	// Currently we do not support arbitrary expressions as branch targets.	7496	// Currently we do not support arbitrary expressions as branch targets.
7497	// Only labels and absolute expressions are accepted.	7497	// Only labels and absolute expressions are accepted.
7498	if (Opr.isExpr() && !Opr.isSymbolRefExpr()) {	7498	if (Opr.isExpr() && !Opr.isSymbolRefExpr()) {
7499	Error(Loc, "expected an absolute expression or a label");	7499	Error(Loc, "expected an absolute expression or a label");
7500	} else if (Opr.isImm() && !Opr.isS16Imm()) {	7500	} else if (Opr.isImm() && !Opr.isS16Imm()) {
7501	Error(Loc, "expected a 16-bit signed jump offset");	7501	Error(Loc, "expected a 16-bit signed jump offset");
7502	}	7502	}
7503		7503
7504	return ParseStatus::Success;	7504	return ParseStatus::Success;
7505	}	7505	}
7506		7506
7507	//===----------------------------------------------------------------------===//	7507	//===----------------------------------------------------------------------===//
7508	// Boolean holding registers	7508	// Boolean holding registers
7509	//===----------------------------------------------------------------------===//	7509	//===----------------------------------------------------------------------===//
7510		7510
7511	ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {	7511	ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {
7512	return parseReg(Operands);	7512	return parseReg(Operands);
7513	}	7513	}
7514		7514
7515	//===----------------------------------------------------------------------===//	7515	//===----------------------------------------------------------------------===//
7516	// mubuf	7516	// mubuf
7517	//===----------------------------------------------------------------------===//	7517	//===----------------------------------------------------------------------===//
7518		7518
7519	void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,	7519	void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
7520	const OperandVector &Operands,	7520	const OperandVector &Operands,
7521	bool IsAtomic) {	7521	bool IsAtomic) {
7522	OptionalImmIndexMap OptionalIdx;	7522	OptionalImmIndexMap OptionalIdx;
7523	unsigned FirstOperandIdx = 1;	7523	unsigned FirstOperandIdx = 1;
7524	bool IsAtomicReturn = false;	7524	bool IsAtomicReturn = false;
7525		7525
7526	if (IsAtomic) {	7526	if (IsAtomic) {
7527	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	7527	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
7528	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	7528	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7529	if (!Op.isCPol())	7529	if (!Op.isCPol())
7530	continue;	7530	continue;
7531	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	7531	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;
7532	break;	7532	break;
7533	}	7533	}
7534		7534
7535	if (!IsAtomicReturn) {	7535	if (!IsAtomicReturn) {
7536	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	7536	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());
7537	if (NewOpc != -1)	7537	if (NewOpc != -1)
7538	Inst.setOpcode(NewOpc);	7538	Inst.setOpcode(NewOpc);
7539	}	7539	}
7540		7540
7541	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	7541	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &
7542	SIInstrFlags::IsAtomicRet;	7542	SIInstrFlags::IsAtomicRet;
7543	}	7543	}
7544		7544
7545	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	7545	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {
7546	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	7546	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7547		7547
7548	// Add the register arguments	7548	// Add the register arguments
7549	if (Op.isReg()) {	7549	if (Op.isReg()) {
7550	Op.addRegOperands(Inst, 1);	7550	Op.addRegOperands(Inst, 1);
7551	// Insert a tied src for atomic return dst.	7551	// Insert a tied src for atomic return dst.
7552	// This cannot be postponed as subsequent calls to	7552	// This cannot be postponed as subsequent calls to
7553	// addImmOperands rely on correct number of MC operands.	7553	// addImmOperands rely on correct number of MC operands.
7554	if (IsAtomicReturn && i == FirstOperandIdx)	7554	if (IsAtomicReturn && i == FirstOperandIdx)
7555	Op.addRegOperands(Inst, 1);	7555	Op.addRegOperands(Inst, 1);
7556	continue;	7556	continue;
7557	}	7557	}
7558		7558
7559	// Handle the case where soffset is an immediate	7559	// Handle the case where soffset is an immediate
7560	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	7560	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
7561	Op.addImmOperands(Inst, 1);	7561	Op.addImmOperands(Inst, 1);
7562	continue;	7562	continue;
7563	}	7563	}
7564		7564
7565	// Handle tokens like 'offen' which are sometimes hard-coded into the	7565	// Handle tokens like 'offen' which are sometimes hard-coded into the
7566	// asm string. There are no MCInst operands for these.	7566	// asm string. There are no MCInst operands for these.
7567	if (Op.isToken()) {	7567	if (Op.isToken()) {
7568	continue;	7568	continue;
7569	}	7569	}
7570	assert(Op.isImm());	7570	assert(Op.isImm());
7571		7571
7572	// Handle optional arguments	7572	// Handle optional arguments
7573	OptionalIdx[Op.getImmTy()] = i;	7573	OptionalIdx[Op.getImmTy()] = i;
7574	}	7574	}
7575		7575
7576	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);	7576	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);
7577	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	7577	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
7578	}	7578	}
7579		7579
7580	//===----------------------------------------------------------------------===//	7580	//===----------------------------------------------------------------------===//
7581	// SMEM	7581	// SMEM
7582	//===----------------------------------------------------------------------===//	7582	//===----------------------------------------------------------------------===//
7583		7583
7584	void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {	7584	void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {
7585	OptionalImmIndexMap OptionalIdx;	7585	OptionalImmIndexMap OptionalIdx;
7586	bool IsAtomicReturn = false;	7586	bool IsAtomicReturn = false;
7587		7587
7588	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	7588	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
7589	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	7589	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7590	if (!Op.isCPol())	7590	if (!Op.isCPol())
7591	continue;	7591	continue;
7592	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	7592	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;
7593	break;	7593	break;
7594	}	7594	}
7595		7595
7596	if (!IsAtomicReturn) {	7596	if (!IsAtomicReturn) {
7597	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	7597	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());
7598	if (NewOpc != -1)	7598	if (NewOpc != -1)
7599	Inst.setOpcode(NewOpc);	7599	Inst.setOpcode(NewOpc);
7600	}	7600	}
7601		7601
7602	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	7602	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &
7603	SIInstrFlags::IsAtomicRet;	7603	SIInstrFlags::IsAtomicRet;
7604		7604
7605	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	7605	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
7606	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	7606	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
7607		7607
7608	// Add the register arguments	7608	// Add the register arguments
7609	if (Op.isReg()) {	7609	if (Op.isReg()) {
7610	Op.addRegOperands(Inst, 1);	7610	Op.addRegOperands(Inst, 1);
7611	if (IsAtomicReturn && i == 1)	7611	if (IsAtomicReturn && i == 1)
7612	Op.addRegOperands(Inst, 1);	7612	Op.addRegOperands(Inst, 1);
7613	continue;	7613	continue;
7614	}	7614	}
7615		7615
7616	// Handle the case where soffset is an immediate	7616	// Handle the case where soffset is an immediate
7617	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	7617	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {
7618	Op.addImmOperands(Inst, 1);	7618	Op.addImmOperands(Inst, 1);
7619	continue;	7619	continue;
7620	}	7620	}
7621		7621
7622	// Handle tokens like 'offen' which are sometimes hard-coded into the	7622	// Handle tokens like 'offen' which are sometimes hard-coded into the
7623	// asm string. There are no MCInst operands for these.	7623	// asm string. There are no MCInst operands for these.
7624	if (Op.isToken()) {	7624	if (Op.isToken()) {
7625	continue;	7625	continue;
7626	}	7626	}
7627	assert(Op.isImm());	7627	assert(Op.isImm());
7628		7628
7629	// Handle optional arguments	7629	// Handle optional arguments
7630	OptionalIdx[Op.getImmTy()] = i;	7630	OptionalIdx[Op.getImmTy()] = i;
7631	}	7631	}
7632		7632
7633	if ((int)Inst.getNumOperands() <=	7633	if ((int)Inst.getNumOperands() <=
7634	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset))	7634	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset))
7635	addOptionalImmOperand(Inst, Operands, OptionalIdx,	7635	addOptionalImmOperand(Inst, Operands, OptionalIdx,
7636	AMDGPUOperand::ImmTySMEMOffsetMod);	7636	AMDGPUOperand::ImmTySMEMOffsetMod);
7637	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	7637	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);
7638	}	7638	}
7639		7639
7640	//===----------------------------------------------------------------------===//	7640	//===----------------------------------------------------------------------===//
7641	// smrd	7641	// smrd
7642	//===----------------------------------------------------------------------===//	7642	//===----------------------------------------------------------------------===//
7643		7643
7644	bool AMDGPUOperand::isSMRDOffset8() const {	7644	bool AMDGPUOperand::isSMRDOffset8() const {
7645	return isImmLiteral() && isUInt<8>(getImm());	7645	return isImmLiteral() && isUInt<8>(getImm());
7646	}	7646	}
7647		7647
7648	bool AMDGPUOperand::isSMEMOffset() const {	7648	bool AMDGPUOperand::isSMEMOffset() const {
7649	// Offset range is checked later by validator.	7649	// Offset range is checked later by validator.
7650	return isImmLiteral();	7650	return isImmLiteral();
7651	}	7651	}
7652		7652
7653	bool AMDGPUOperand::isSMRDLiteralOffset() const {	7653	bool AMDGPUOperand::isSMRDLiteralOffset() const {
7654	// 32-bit literals are only supported on CI and we only want to use them	7654	// 32-bit literals are only supported on CI and we only want to use them
7655	// when the offset is > 8-bits.	7655	// when the offset is > 8-bits.
7656	return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());	7656	return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());
7657	}	7657	}
7658		7658
7659	//===----------------------------------------------------------------------===//	7659	//===----------------------------------------------------------------------===//
7660	// vop3	7660	// vop3
7661	//===----------------------------------------------------------------------===//	7661	//===----------------------------------------------------------------------===//
7662		7662
7663	static bool ConvertOmodMul(int64_t &Mul) {	7663	static bool ConvertOmodMul(int64_t &Mul) {
7664	if (Mul != 1 && Mul != 2 && Mul != 4)	7664	if (Mul != 1 && Mul != 2 && Mul != 4)
7665	return false;	7665	return false;
7666		7666
7667	Mul >>= 1;	7667	Mul >>= 1;
7668	return true;	7668	return true;
7669	}	7669	}
7670		7670
7671	static bool ConvertOmodDiv(int64_t &Div) {	7671	static bool ConvertOmodDiv(int64_t &Div) {
7672	if (Div == 1) {	7672	if (Div == 1) {
7673	Div = 0;	7673	Div = 0;
7674	return true;	7674	return true;
7675	}	7675	}
7676		7676
7677	if (Div == 2) {	7677	if (Div == 2) {
7678	Div = 3;	7678	Div = 3;
7679	return true;	7679	return true;
7680	}	7680	}
7681		7681
7682	return false;	7682	return false;
7683	}	7683	}
7684		7684
7685	// For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.	7685	// For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.
7686	// This is intentional and ensures compatibility with sp3.	7686	// This is intentional and ensures compatibility with sp3.
7687	// See bug 35397 for details.	7687	// See bug 35397 for details.
7688	bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {	7688	bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {
7689	if (BoundCtrl == 0 \|\| BoundCtrl == 1) {	7689	if (BoundCtrl == 0 \|\| BoundCtrl == 1) {
7690	if (!isGFX11Plus())	7690	if (!isGFX11Plus())
7691	BoundCtrl = 1;	7691	BoundCtrl = 1;
7692	return true;	7692	return true;
7693	}	7693	}
7694	return false;	7694	return false;
7695	}	7695	}
7696		7696
7697	void AMDGPUAsmParser::onBeginOfFile() {	7697	void AMDGPUAsmParser::onBeginOfFile() {
7698	if (!getParser().getStreamer().getTargetStreamer() \|\|	7698	if (!getParser().getStreamer().getTargetStreamer() \|\|
7699	getSTI().getTargetTriple().getArch() == Triple::r600)	7699	getSTI().getTargetTriple().getArch() == Triple::r600)
7700	return;	7700	return;
7701		7701
7702	if (!getTargetStreamer().getTargetID())	7702	if (!getTargetStreamer().getTargetID())
7703	getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(),	7703	getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(),
7704	// TODO: Should try to check code object version from directive???	7704	// TODO: Should try to check code object version from directive???
7705	AMDGPU::getAmdhsaCodeObjectVersion());	7705	AMDGPU::getAmdhsaCodeObjectVersion());
7706		7706
7707	if (isHsaAbiVersion3AndAbove(&getSTI()))	7707	if (isHsaAbiVersion3AndAbove(&getSTI()))
7708	getTargetStreamer().EmitDirectiveAMDGCNTarget();	7708	getTargetStreamer().EmitDirectiveAMDGCNTarget();
7709	}	7709	}
7710		7710
7711	ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {	7711	ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {
7712	StringRef Name = getTokenStr();	7712	StringRef Name = getTokenStr();
7713	if (Name == "mul") {	7713	if (Name == "mul") {
7714	return parseIntWithPrefix("mul", Operands,	7714	return parseIntWithPrefix("mul", Operands,
7715	AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);	7715	AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);
7716	}	7716	}
7717		7717
7718	if (Name == "div") {	7718	if (Name == "div") {
7719	return parseIntWithPrefix("div", Operands,	7719	return parseIntWithPrefix("div", Operands,
7720	AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);	7720	AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);
7721	}	7721	}
7722		7722
7723	return ParseStatus::NoMatch;	7723	return ParseStatus::NoMatch;
7724	}	7724	}
7725		7725
7726	// Determines which bit DST_OP_SEL occupies in the op_sel operand according to	7726	// Determines which bit DST_OP_SEL occupies in the op_sel operand according to
7727	// the number of src operands present, then copies that bit into src0_modifiers.	7727	// the number of src operands present, then copies that bit into src0_modifiers.
7728	void cvtVOP3DstOpSelOnly(MCInst &Inst) {	7728	void cvtVOP3DstOpSelOnly(MCInst &Inst) {
7729	int Opc = Inst.getOpcode();	7729	int Opc = Inst.getOpcode();
7730	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	7730	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
7731	if (OpSelIdx == -1)	7731	if (OpSelIdx == -1)
7732	return;	7732	return;
7733		7733
7734	int SrcNum;	7734	int SrcNum;
7735	const int Ops[] = { AMDGPU::OpName::src0,	7735	const int Ops[] = { AMDGPU::OpName::src0,
7736	AMDGPU::OpName::src1,	7736	AMDGPU::OpName::src1,
7737	AMDGPU::OpName::src2 };	7737	AMDGPU::OpName::src2 };
7738	for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);	7738	for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);
7739	++SrcNum)	7739	++SrcNum)
7740	;	7740	;
7741	assert(SrcNum > 0);	7741	assert(SrcNum > 0);
7742		7742
7743	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	7743	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
7744		7744
7745	if ((OpSel & (1 << SrcNum)) != 0) {	7745	if ((OpSel & (1 << SrcNum)) != 0) {
7746	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);	7746	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
7747	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	7747	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
7748	Inst.getOperand(ModIdx).setImm(ModVal \| SISrcMods::DST_OP_SEL);	7748	Inst.getOperand(ModIdx).setImm(ModVal \| SISrcMods::DST_OP_SEL);
7749	}	7749	}
7750	}	7750	}
7751		7751
7752	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,	7752	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,
7753	const OperandVector &Operands) {	7753	const OperandVector &Operands) {
7754	cvtVOP3P(Inst, Operands);	7754	cvtVOP3P(Inst, Operands);
7755	cvtVOP3DstOpSelOnly(Inst);	7755	cvtVOP3DstOpSelOnly(Inst);
7756	}	7756	}
7757		7757
7758	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	7758	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,
7759	OptionalImmIndexMap &OptionalIdx) {	7759	OptionalImmIndexMap &OptionalIdx) {
7760	cvtVOP3P(Inst, Operands, OptionalIdx);	7760	cvtVOP3P(Inst, Operands, OptionalIdx);
7761	cvtVOP3DstOpSelOnly(Inst);	7761	cvtVOP3DstOpSelOnly(Inst);
7762	}	7762	}
7763		7763
7764	static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {	7764	static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {
7765	return	7765	return
7766	// 1. This operand is input modifiers	7766	// 1. This operand is input modifiers
7767	Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS	7767	Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS
7768	// 2. This is not last operand	7768	// 2. This is not last operand
7769	&& Desc.NumOperands > (OpNum + 1)	7769	&& Desc.NumOperands > (OpNum + 1)
7770	// 3. Next operand is register class	7770	// 3. Next operand is register class
7771	&& Desc.operands()[OpNum + 1].RegClass != -1	7771	&& Desc.operands()[OpNum + 1].RegClass != -1
7772	// 4. Next register is not tied to any other operand	7772	// 4. Next register is not tied to any other operand
7773	&& Desc.getOperandConstraint(OpNum + 1,	7773	&& Desc.getOperandConstraint(OpNum + 1,
7774	MCOI::OperandConstraint::TIED_TO) == -1;	7774	MCOI::OperandConstraint::TIED_TO) == -1;
7775	}	7775	}
7776		7776
7777	void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)	7777	void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)
7778	{	7778	{
7779	OptionalImmIndexMap OptionalIdx;	7779	OptionalImmIndexMap OptionalIdx;
7780	unsigned Opc = Inst.getOpcode();	7780	unsigned Opc = Inst.getOpcode();
7781		7781
7782	unsigned I = 1;	7782	unsigned I = 1;
7783	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	7783	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
7784	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	7784	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
7785	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	7785	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
7786	}	7786	}
7787		7787
7788	for (unsigned E = Operands.size(); I != E; ++I) {	7788	for (unsigned E = Operands.size(); I != E; ++I) {
7789	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	7789	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
7790	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	7790	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
7791	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	7791	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
7792	} else if (Op.isInterpSlot() \|\| Op.isInterpAttr() \|\|	7792	} else if (Op.isInterpSlot() \|\| Op.isInterpAttr() \|\|
7793	Op.isInterpAttrChan()) {	7793	Op.isInterpAttrChan()) {
7794	Inst.addOperand(MCOperand::createImm(Op.getImm()));	7794	Inst.addOperand(MCOperand::createImm(Op.getImm()));
7795	} else if (Op.isImmModifier()) {	7795	} else if (Op.isImmModifier()) {
7796	OptionalIdx[Op.getImmTy()] = I;	7796	OptionalIdx[Op.getImmTy()] = I;
7797	} else {	7797	} else {
7798	llvm_unreachable("unhandled operand type");	7798	llvm_unreachable("unhandled operand type");
7799	}	7799	}
7800	}	7800	}
7801		7801
7802	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))	7802	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))
7803	addOptionalImmOperand(Inst, Operands, OptionalIdx,	7803	addOptionalImmOperand(Inst, Operands, OptionalIdx,
7804	AMDGPUOperand::ImmTyHigh);	7804	AMDGPUOperand::ImmTyHigh);
7805		7805
7806	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	7806	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
7807	addOptionalImmOperand(Inst, Operands, OptionalIdx,	7807	addOptionalImmOperand(Inst, Operands, OptionalIdx,
7808	AMDGPUOperand::ImmTyClampSI);	7808	AMDGPUOperand::ImmTyClampSI);
7809		7809
7810	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	7810	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
7811	addOptionalImmOperand(Inst, Operands, OptionalIdx,	7811	addOptionalImmOperand(Inst, Operands, OptionalIdx,
7812	AMDGPUOperand::ImmTyOModSI);	7812	AMDGPUOperand::ImmTyOModSI);
7813	}	7813	}
7814		7814
7815	void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)	7815	void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
7816	{	7816	{
7817	OptionalImmIndexMap OptionalIdx;	7817	OptionalImmIndexMap OptionalIdx;
7818	unsigned Opc = Inst.getOpcode();	7818	unsigned Opc = Inst.getOpcode();
7819		7819
7820	unsigned I = 1;	7820	unsigned I = 1;
7821	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	7821	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
7822	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	7822	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
7823	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	7823	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
7824	}	7824	}
7825		7825
7826	for (unsigned E = Operands.size(); I != E; ++I) {	7826	for (unsigned E = Operands.size(); I != E; ++I) {
7827	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	7827	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
7828	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	7828	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
7829	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	7829	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
7830	} else if (Op.isImmModifier()) {	7830	} else if (Op.isImmModifier()) {
7831	OptionalIdx[Op.getImmTy()] = I;	7831	OptionalIdx[Op.getImmTy()] = I;
7832	} else {	7832	} else {
7833	llvm_unreachable("unhandled operand type");	7833	llvm_unreachable("unhandled operand type");
7834	}	7834	}
7835	}	7835	}
7836		7836
7837	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	7837	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
7838		7838
7839	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	7839	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
7840	if (OpSelIdx != -1)	7840	if (OpSelIdx != -1)
7841	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	7841	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
7842		7842
7843	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);	7843	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);
7844		7844
7845	if (OpSelIdx == -1)	7845	if (OpSelIdx == -1)
7846	return;	7846	return;
7847		7847
7848	const int Ops[] = { AMDGPU::OpName::src0,	7848	const int Ops[] = { AMDGPU::OpName::src0,
7849	AMDGPU::OpName::src1,	7849	AMDGPU::OpName::src1,
7850	AMDGPU::OpName::src2 };	7850	AMDGPU::OpName::src2 };
7851	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	7851	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
7852	AMDGPU::OpName::src1_modifiers,	7852	AMDGPU::OpName::src1_modifiers,
7853	AMDGPU::OpName::src2_modifiers };	7853	AMDGPU::OpName::src2_modifiers };
7854		7854
7855	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	7855	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
7856		7856
7857	for (int J = 0; J < 3; ++J) {	7857	for (int J = 0; J < 3; ++J) {
7858	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	7858	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);
7859	if (OpIdx == -1)	7859	if (OpIdx == -1)
7860	break;	7860	break;
7861		7861
7862	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	7862	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
7863	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	7863	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();
7864		7864
7865	if ((OpSel & (1 << J)) != 0)	7865	if ((OpSel & (1 << J)) != 0)
7866	ModVal \|= SISrcMods::OP_SEL_0;	7866	ModVal \|= SISrcMods::OP_SEL_0;
7867	if (ModOps[J] == AMDGPU::OpName::src0_modifiers &&	7867	if (ModOps[J] == AMDGPU::OpName::src0_modifiers &&
7868	(OpSel & (1 << 3)) != 0)	7868	(OpSel & (1 << 3)) != 0)
7869	ModVal \|= SISrcMods::DST_OP_SEL;	7869	ModVal \|= SISrcMods::DST_OP_SEL;
7870		7870
7871	Inst.getOperand(ModIdx).setImm(ModVal);	7871	Inst.getOperand(ModIdx).setImm(ModVal);
7872	}	7872	}
7873	}	7873	}
7874		7874
7875	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,	7875	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
7876	OptionalImmIndexMap &OptionalIdx) {	7876	OptionalImmIndexMap &OptionalIdx) {
7877	unsigned Opc = Inst.getOpcode();	7877	unsigned Opc = Inst.getOpcode();
7878		7878
7879	unsigned I = 1;	7879	unsigned I = 1;
7880	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	7880	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
7881	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	7881	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
7882	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	7882	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
7883	}	7883	}
7884		7884
7885	for (unsigned E = Operands.size(); I != E; ++I) {	7885	for (unsigned E = Operands.size(); I != E; ++I) {
7886	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	7886	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
7887	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	7887	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
7888	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	7888	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
7889	} else if (Op.isImmModifier()) {	7889	} else if (Op.isImmModifier()) {
7890	OptionalIdx[Op.getImmTy()] = I;	7890	OptionalIdx[Op.getImmTy()] = I;
7891	} else if (Op.isRegOrImm()) {	7891	} else if (Op.isRegOrImm()) {
7892	Op.addRegOrImmOperands(Inst, 1);	7892	Op.addRegOrImmOperands(Inst, 1);
7893	} else {	7893	} else {
7894	llvm_unreachable("unhandled operand type");	7894	llvm_unreachable("unhandled operand type");
7895	}	7895	}
7896	}	7896	}
7897		7897
7898	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	7898	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
7899	addOptionalImmOperand(Inst, Operands, OptionalIdx,	7899	addOptionalImmOperand(Inst, Operands, OptionalIdx,
7900	AMDGPUOperand::ImmTyClampSI);	7900	AMDGPUOperand::ImmTyClampSI);
7901		7901
7902	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	7902	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
7903	addOptionalImmOperand(Inst, Operands, OptionalIdx,	7903	addOptionalImmOperand(Inst, Operands, OptionalIdx,
7904	AMDGPUOperand::ImmTyOModSI);	7904	AMDGPUOperand::ImmTyOModSI);
7905		7905
7906	// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):	7906	// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):
7907	// it has src2 register operand that is tied to dst operand	7907	// it has src2 register operand that is tied to dst operand
7908	// we don't allow modifiers for this operand in assembler so src2_modifiers	7908	// we don't allow modifiers for this operand in assembler so src2_modifiers
7909	// should be 0.	7909	// should be 0.
7910	if (isMAC(Opc)) {	7910	if (isMAC(Opc)) {
7911	auto it = Inst.begin();	7911	auto it = Inst.begin();
7912	std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));	7912	std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));
7913	it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2	7913	it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2
7914	++it;	7914	++it;
7915	// Copy the operand to ensure it's not invalidated when Inst grows.	7915	// Copy the operand to ensure it's not invalidated when Inst grows.
7916	Inst.insert(it, MCOperand(Inst.getOperand(0))); // src2 = dst	7916	Inst.insert(it, MCOperand(Inst.getOperand(0))); // src2 = dst
7917	}	7917	}
7918	}	7918	}
7919		7919
7920	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {	7920	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {
7921	OptionalImmIndexMap OptionalIdx;	7921	OptionalImmIndexMap OptionalIdx;
7922	cvtVOP3(Inst, Operands, OptionalIdx);	7922	cvtVOP3(Inst, Operands, OptionalIdx);
7923	}	7923	}
7924		7924
7925	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	7925	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
7926	OptionalImmIndexMap &OptIdx) {	7926	OptionalImmIndexMap &OptIdx) {
7927	const int Opc = Inst.getOpcode();	7927	const int Opc = Inst.getOpcode();
7928	const MCInstrDesc &Desc = MII.get(Opc);	7928	const MCInstrDesc &Desc = MII.get(Opc);
7929		7929
7930	const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;	7930	const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;
7931		7931
7932	if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi \|\|	7932	if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi \|\|
7933	Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) {	7933	Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) {
7934	Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods	7934	Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods
7935	Inst.addOperand(Inst.getOperand(0));	7935	Inst.addOperand(Inst.getOperand(0));
7936	}	7936	}
7937		7937
7938	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {	7938	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {
7939	assert(!IsPacked);	7939	assert(!IsPacked);
7940	Inst.addOperand(Inst.getOperand(0));	7940	Inst.addOperand(Inst.getOperand(0));
7941	}	7941	}
7942		7942
7943	// FIXME: This is messy. Parse the modifiers as if it was a normal VOP3	7943	// FIXME: This is messy. Parse the modifiers as if it was a normal VOP3
7944	// instruction, and then figure out where to actually put the modifiers	7944	// instruction, and then figure out where to actually put the modifiers
7945		7945
7946	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	7946	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);
7947	if (OpSelIdx != -1) {	7947	if (OpSelIdx != -1) {
7948	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);	7948	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);
7949	}	7949	}
7950		7950
7951	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	7951	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);
7952	if (OpSelHiIdx != -1) {	7952	if (OpSelHiIdx != -1) {
7953	int DefaultVal = IsPacked ? -1 : 0;	7953	int DefaultVal = IsPacked ? -1 : 0;
7954	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,	7954	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,
7955	DefaultVal);	7955	DefaultVal);
7956	}	7956	}
7957		7957
7958	int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);	7958	int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);
7959	if (NegLoIdx != -1) {	7959	if (NegLoIdx != -1) {
7960	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);	7960	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);
7961	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);	7961	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);
7962	}	7962	}
7963		7963
7964	const int Ops[] = { AMDGPU::OpName::src0,	7964	const int Ops[] = { AMDGPU::OpName::src0,
7965	AMDGPU::OpName::src1,	7965	AMDGPU::OpName::src1,
7966	AMDGPU::OpName::src2 };	7966	AMDGPU::OpName::src2 };
7967	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	7967	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,
7968	AMDGPU::OpName::src1_modifiers,	7968	AMDGPU::OpName::src1_modifiers,
7969	AMDGPU::OpName::src2_modifiers };	7969	AMDGPU::OpName::src2_modifiers };
7970		7970
7971	unsigned OpSel = 0;	7971	unsigned OpSel = 0;
7972	unsigned OpSelHi = 0;	7972	unsigned OpSelHi = 0;
7973	unsigned NegLo = 0;	7973	unsigned NegLo = 0;
7974	unsigned NegHi = 0;	7974	unsigned NegHi = 0;
7975		7975
7976	if (OpSelIdx != -1)	7976	if (OpSelIdx != -1)
7977	OpSel = Inst.getOperand(OpSelIdx).getImm();	7977	OpSel = Inst.getOperand(OpSelIdx).getImm();
7978		7978
7979	if (OpSelHiIdx != -1)	7979	if (OpSelHiIdx != -1)
7980	OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();	7980	OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();
7981		7981
7982	if (NegLoIdx != -1) {	7982	if (NegLoIdx != -1) {
7983	int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);	7983	int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);
7984	NegLo = Inst.getOperand(NegLoIdx).getImm();	7984	NegLo = Inst.getOperand(NegLoIdx).getImm();
7985	NegHi = Inst.getOperand(NegHiIdx).getImm();	7985	NegHi = Inst.getOperand(NegHiIdx).getImm();
7986	}	7986	}
7987		7987
7988	for (int J = 0; J < 3; ++J) {	7988	for (int J = 0; J < 3; ++J) {
7989	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	7989	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);
7990	if (OpIdx == -1)	7990	if (OpIdx == -1)
7991	break;	7991	break;
7992		7992
7993	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	7993	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);
7994		7994
7995	if (ModIdx == -1)	7995	if (ModIdx == -1)
7996	continue;	7996	continue;
7997		7997
7998	uint32_t ModVal = 0;	7998	uint32_t ModVal = 0;
7999		7999
8000	if ((OpSel & (1 << J)) != 0)	8000	if ((OpSel & (1 << J)) != 0)
8001	ModVal \|= SISrcMods::OP_SEL_0;	8001	ModVal \|= SISrcMods::OP_SEL_0;
8002		8002
8003	if ((OpSelHi & (1 << J)) != 0)	8003	if ((OpSelHi & (1 << J)) != 0)
8004	ModVal \|= SISrcMods::OP_SEL_1;	8004	ModVal \|= SISrcMods::OP_SEL_1;
8005		8005
8006	if ((NegLo & (1 << J)) != 0)	8006	if ((NegLo & (1 << J)) != 0)
8007	ModVal \|= SISrcMods::NEG;	8007	ModVal \|= SISrcMods::NEG;
8008		8008
8009	if ((NegHi & (1 << J)) != 0)	8009	if ((NegHi & (1 << J)) != 0)
8010	ModVal \|= SISrcMods::NEG_HI;	8010	ModVal \|= SISrcMods::NEG_HI;
8011		8011
8012	Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() \| ModVal);	8012	Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() \| ModVal);
8013	}	8013	}
8014	}	8014	}
8015		8015
8016	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {	8016	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {
8017	OptionalImmIndexMap OptIdx;	8017	OptionalImmIndexMap OptIdx;
8018	cvtVOP3(Inst, Operands, OptIdx);	8018	cvtVOP3(Inst, Operands, OptIdx);
8019	cvtVOP3P(Inst, Operands, OptIdx);	8019	cvtVOP3P(Inst, Operands, OptIdx);
8020	}	8020	}
8021		8021
8022	//===----------------------------------------------------------------------===//	8022	//===----------------------------------------------------------------------===//
8023	// VOPD	8023	// VOPD
8024	//===----------------------------------------------------------------------===//	8024	//===----------------------------------------------------------------------===//
8025		8025
8026	ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {	8026	ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {
8027	if (!hasVOPD(getSTI()))	8027	if (!hasVOPD(getSTI()))
8028	return ParseStatus::NoMatch;	8028	return ParseStatus::NoMatch;
8029		8029
8030	if (isToken(AsmToken::Colon) && peekToken(false).is(AsmToken::Colon)) {	8030	if (isToken(AsmToken::Colon) && peekToken(false).is(AsmToken::Colon)) {
8031	SMLoc S = getLoc();	8031	SMLoc S = getLoc();
8032	lex();	8032	lex();
8033	lex();	8033	lex();
8034	Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));	8034	Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));
8035	SMLoc OpYLoc = getLoc();	8035	SMLoc OpYLoc = getLoc();
8036	StringRef OpYName;	8036	StringRef OpYName;
8037	if (isToken(AsmToken::Identifier) && !Parser.parseIdentifier(OpYName)) {	8037	if (isToken(AsmToken::Identifier) && !Parser.parseIdentifier(OpYName)) {
8038	Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));	8038	Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));
8039	return ParseStatus::Success;	8039	return ParseStatus::Success;
8040	}	8040	}
8041	return Error(OpYLoc, "expected a VOPDY instruction after ::");	8041	return Error(OpYLoc, "expected a VOPDY instruction after ::");
8042	}	8042	}
8043	return ParseStatus::NoMatch;	8043	return ParseStatus::NoMatch;
8044	}	8044	}
8045		8045
8046	// Create VOPD MCInst operands using parsed assembler operands.	8046	// Create VOPD MCInst operands using parsed assembler operands.
8047	void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {	8047	void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {
8048	auto addOp = [&](uint16_t ParsedOprIdx) { // NOLINT:function pointer	8048	auto addOp = [&](uint16_t ParsedOprIdx) { // NOLINT:function pointer
8049	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);	8049	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);
8050	if (Op.isReg()) {	8050	if (Op.isReg()) {
8051	Op.addRegOperands(Inst, 1);	8051	Op.addRegOperands(Inst, 1);
8052	return;	8052	return;
8053	}	8053	}
8054	if (Op.isImm()) {	8054	if (Op.isImm()) {
8055	Op.addImmOperands(Inst, 1);	8055	Op.addImmOperands(Inst, 1);
8056	return;	8056	return;
8057	}	8057	}
8058	llvm_unreachable("Unhandled operand type in cvtVOPD");	8058	llvm_unreachable("Unhandled operand type in cvtVOPD");
8059	};	8059	};
8060		8060
8061	const auto &InstInfo = getVOPDInstInfo(Inst.getOpcode(), &MII);	8061	const auto &InstInfo = getVOPDInstInfo(Inst.getOpcode(), &MII);
8062		8062
8063	// MCInst operands are ordered as follows:	8063	// MCInst operands are ordered as follows:
8064	// dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]	8064	// dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]
8065		8065
8066	for (auto CompIdx : VOPD::COMPONENTS) {	8066	for (auto CompIdx : VOPD::COMPONENTS) {
8067	addOp(InstInfo[CompIdx].getIndexOfDstInParsedOperands());	8067	addOp(InstInfo[CompIdx].getIndexOfDstInParsedOperands());
8068	}	8068	}
8069		8069
8070	for (auto CompIdx : VOPD::COMPONENTS) {	8070	for (auto CompIdx : VOPD::COMPONENTS) {
8071	const auto &CInfo = InstInfo[CompIdx];	8071	const auto &CInfo = InstInfo[CompIdx];
8072	auto CompSrcOperandsNum = InstInfo[CompIdx].getCompParsedSrcOperandsNum();	8072	auto CompSrcOperandsNum = InstInfo[CompIdx].getCompParsedSrcOperandsNum();
8073	for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOperandsNum; ++CompSrcIdx)	8073	for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOperandsNum; ++CompSrcIdx)
8074	addOp(CInfo.getIndexOfSrcInParsedOperands(CompSrcIdx));	8074	addOp(CInfo.getIndexOfSrcInParsedOperands(CompSrcIdx));
8075	if (CInfo.hasSrc2Acc())	8075	if (CInfo.hasSrc2Acc())
8076	addOp(CInfo.getIndexOfDstInParsedOperands());	8076	addOp(CInfo.getIndexOfDstInParsedOperands());
8077	}	8077	}
8078	}	8078	}
8079		8079
8080	//===----------------------------------------------------------------------===//	8080	//===----------------------------------------------------------------------===//
8081	// dpp	8081	// dpp
8082	//===----------------------------------------------------------------------===//	8082	//===----------------------------------------------------------------------===//
8083		8083
8084	bool AMDGPUOperand::isDPP8() const {	8084	bool AMDGPUOperand::isDPP8() const {
8085	return isImmTy(ImmTyDPP8);	8085	return isImmTy(ImmTyDPP8);
8086	}	8086	}
8087		8087
8088	bool AMDGPUOperand::isDPPCtrl() const {	8088	bool AMDGPUOperand::isDPPCtrl() const {
8089	using namespace AMDGPU::DPP;	8089	using namespace AMDGPU::DPP;
8090		8090
8091	bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());	8091	bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());
8092	if (result) {	8092	if (result) {
8093	int64_t Imm = getImm();	8093	int64_t Imm = getImm();
8094	return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) \|\|	8094	return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) \|\|
8095	(Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) \|\|	8095	(Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) \|\|
8096	(Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) \|\|	8096	(Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) \|\|
8097	(Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) \|\|	8097	(Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) \|\|
8098	(Imm == DppCtrl::WAVE_SHL1) \|\|	8098	(Imm == DppCtrl::WAVE_SHL1) \|\|
8099	(Imm == DppCtrl::WAVE_ROL1) \|\|	8099	(Imm == DppCtrl::WAVE_ROL1) \|\|
8100	(Imm == DppCtrl::WAVE_SHR1) \|\|	8100	(Imm == DppCtrl::WAVE_SHR1) \|\|
8101	(Imm == DppCtrl::WAVE_ROR1) \|\|	8101	(Imm == DppCtrl::WAVE_ROR1) \|\|
8102	(Imm == DppCtrl::ROW_MIRROR) \|\|	8102	(Imm == DppCtrl::ROW_MIRROR) \|\|
8103	(Imm == DppCtrl::ROW_HALF_MIRROR) \|\|	8103	(Imm == DppCtrl::ROW_HALF_MIRROR) \|\|
8104	(Imm == DppCtrl::BCAST15) \|\|	8104	(Imm == DppCtrl::BCAST15) \|\|
8105	(Imm == DppCtrl::BCAST31) \|\|	8105	(Imm == DppCtrl::BCAST31) \|\|
8106	(Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) \|\|	8106	(Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) \|\|
8107	(Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST);	8107	(Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST);
8108	}	8108	}
8109	return false;	8109	return false;
8110	}	8110	}
8111		8111
8112	//===----------------------------------------------------------------------===//	8112	//===----------------------------------------------------------------------===//
8113	// mAI	8113	// mAI
8114	//===----------------------------------------------------------------------===//	8114	//===----------------------------------------------------------------------===//
8115		8115
8116	bool AMDGPUOperand::isBLGP() const {	8116	bool AMDGPUOperand::isBLGP() const {
8117	return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());	8117	return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());
8118	}	8118	}
8119		8119
8120	bool AMDGPUOperand::isCBSZ() const {	8120	bool AMDGPUOperand::isCBSZ() const {
8121	return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());	8121	return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());
8122	}	8122	}
8123		8123
8124	bool AMDGPUOperand::isABID() const {	8124	bool AMDGPUOperand::isABID() const {
8125	return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());	8125	return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());
8126	}	8126	}
8127		8127
8128	bool AMDGPUOperand::isS16Imm() const {	8128	bool AMDGPUOperand::isS16Imm() const {
8129	return isImmLiteral() && (isInt<16>(getImm()) \|\| isUInt<16>(getImm()));	8129	return isImmLiteral() && (isInt<16>(getImm()) \|\| isUInt<16>(getImm()));
8130	}	8130	}
8131		8131
8132	bool AMDGPUOperand::isU16Imm() const {	8132	bool AMDGPUOperand::isU16Imm() const {
8133	return isImmLiteral() && isUInt<16>(getImm());	8133	return isImmLiteral() && isUInt<16>(getImm());
8134	}	8134	}
8135		8135
8136	//===----------------------------------------------------------------------===//	8136	//===----------------------------------------------------------------------===//
8137	// dim	8137	// dim
8138	//===----------------------------------------------------------------------===//	8138	//===----------------------------------------------------------------------===//
8139		8139
8140	bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {	8140	bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {
8141	// We want to allow "dim:1D" etc.,	8141	// We want to allow "dim:1D" etc.,
8142	// but the initial 1 is tokenized as an integer.	8142	// but the initial 1 is tokenized as an integer.
8143	std::string Token;	8143	std::string Token;
8144	if (isToken(AsmToken::Integer)) {	8144	if (isToken(AsmToken::Integer)) {
8145	SMLoc Loc = getToken().getEndLoc();	8145	SMLoc Loc = getToken().getEndLoc();
8146	Token = std::string(getTokenStr());	8146	Token = std::string(getTokenStr());
8147	lex();	8147	lex();
8148	if (getLoc() != Loc)	8148	if (getLoc() != Loc)
8149	return false;	8149	return false;
8150	}	8150	}
8151		8151
8152	StringRef Suffix;	8152	StringRef Suffix;
8153	if (!parseId(Suffix))	8153	if (!parseId(Suffix))
8154	return false;	8154	return false;
8155	Token += Suffix;	8155	Token += Suffix;
8156		8156
8157	StringRef DimId = Token;	8157	StringRef DimId = Token;
8158	if (DimId.startswith("SQ_RSRC_IMG_"))	8158	if (DimId.startswith("SQ_RSRC_IMG_"))
8159	DimId = DimId.drop_front(12);	8159	DimId = DimId.drop_front(12);
8160		8160
8161	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);	8161	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);
8162	if (!DimInfo)	8162	if (!DimInfo)
8163	return false;	8163	return false;
8164		8164
8165	Encoding = DimInfo->Encoding;	8165	Encoding = DimInfo->Encoding;
8166	return true;	8166	return true;
8167	}	8167	}
8168		8168
8169	ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {	8169	ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {
8170	if (!isGFX10Plus())	8170	if (!isGFX10Plus())
8171	return ParseStatus::NoMatch;	8171	return ParseStatus::NoMatch;
8172		8172
8173	SMLoc S = getLoc();	8173	SMLoc S = getLoc();
8174		8174
8175	if (!trySkipId("dim", AsmToken::Colon))	8175	if (!trySkipId("dim", AsmToken::Colon))
8176	return ParseStatus::NoMatch;	8176	return ParseStatus::NoMatch;
8177		8177
8178	unsigned Encoding;	8178	unsigned Encoding;
8179	SMLoc Loc = getLoc();	8179	SMLoc Loc = getLoc();
8180	if (!parseDimId(Encoding))	8180	if (!parseDimId(Encoding))
8181	return Error(Loc, "invalid dim value");	8181	return Error(Loc, "invalid dim value");
8182		8182
8183	Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,	8183	Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,
8184	AMDGPUOperand::ImmTyDim));	8184	AMDGPUOperand::ImmTyDim));
8185	return ParseStatus::Success;	8185	return ParseStatus::Success;
8186	}	8186	}
8187		8187
8188	//===----------------------------------------------------------------------===//	8188	//===----------------------------------------------------------------------===//
8189	// dpp	8189	// dpp
8190	//===----------------------------------------------------------------------===//	8190	//===----------------------------------------------------------------------===//
8191		8191
8192	ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {	8192	ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {
8193	SMLoc S = getLoc();	8193	SMLoc S = getLoc();
8194		8194
8195	if (!isGFX10Plus() \|\| !trySkipId("dpp8", AsmToken::Colon))	8195	if (!isGFX10Plus() \|\| !trySkipId("dpp8", AsmToken::Colon))
8196	return ParseStatus::NoMatch;	8196	return ParseStatus::NoMatch;
8197		8197
8198	// dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]	8198	// dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]
8199		8199
8200	int64_t Sels[8];	8200	int64_t Sels[8];
8201		8201
8202	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	8202	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))
8203	return ParseStatus::Failure;	8203	return ParseStatus::Failure;
8204		8204
8205	for (size_t i = 0; i < 8; ++i) {	8205	for (size_t i = 0; i < 8; ++i) {
8206	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	8206	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))
8207	return ParseStatus::Failure;	8207	return ParseStatus::Failure;
8208		8208
8209	SMLoc Loc = getLoc();	8209	SMLoc Loc = getLoc();
8210	if (getParser().parseAbsoluteExpression(Sels[i]))	8210	if (getParser().parseAbsoluteExpression(Sels[i]))
8211	return ParseStatus::Failure;	8211	return ParseStatus::Failure;
8212	if (0 > Sels[i] \|\| 7 < Sels[i])	8212	if (0 > Sels[i] \|\| 7 < Sels[i])
8213	return Error(Loc, "expected a 3-bit value");	8213	return Error(Loc, "expected a 3-bit value");
8214	}	8214	}
8215		8215
8216	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	8216	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
8217	return ParseStatus::Failure;	8217	return ParseStatus::Failure;
8218		8218
8219	unsigned DPP8 = 0;	8219	unsigned DPP8 = 0;
8220	for (size_t i = 0; i < 8; ++i)	8220	for (size_t i = 0; i < 8; ++i)
8221	DPP8 \|= (Sels[i] << (i * 3));	8221	DPP8 \|= (Sels[i] << (i * 3));
8222		8222
8223	Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));	8223	Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));
8224	return ParseStatus::Success;	8224	return ParseStatus::Success;
8225	}	8225	}
8226		8226
8227	bool	8227	bool
8228	AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,	8228	AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,
8229	const OperandVector &Operands) {	8229	const OperandVector &Operands) {
8230	if (Ctrl == "row_newbcast")	8230	if (Ctrl == "row_newbcast")
8231	return isGFX90A();	8231	return isGFX90A();
8232		8232
8233	if (Ctrl == "row_share" \|\|	8233	if (Ctrl == "row_share" \|\|
8234	Ctrl == "row_xmask")	8234	Ctrl == "row_xmask")
8235	return isGFX10Plus();	8235	return isGFX10Plus();
8236		8236
8237	if (Ctrl == "wave_shl" \|\|	8237	if (Ctrl == "wave_shl" \|\|
8238	Ctrl == "wave_shr" \|\|	8238	Ctrl == "wave_shr" \|\|
8239	Ctrl == "wave_rol" \|\|	8239	Ctrl == "wave_rol" \|\|
8240	Ctrl == "wave_ror" \|\|	8240	Ctrl == "wave_ror" \|\|
8241	Ctrl == "row_bcast")	8241	Ctrl == "row_bcast")
8242	return isVI() \|\| isGFX9();	8242	return isVI() \|\| isGFX9();
8243		8243
8244	return Ctrl == "row_mirror" \|\|	8244	return Ctrl == "row_mirror" \|\|
8245	Ctrl == "row_half_mirror" \|\|	8245	Ctrl == "row_half_mirror" \|\|
8246	Ctrl == "quad_perm" \|\|	8246	Ctrl == "quad_perm" \|\|
8247	Ctrl == "row_shl" \|\|	8247	Ctrl == "row_shl" \|\|
8248	Ctrl == "row_shr" \|\|	8248	Ctrl == "row_shr" \|\|
8249	Ctrl == "row_ror";	8249	Ctrl == "row_ror";
8250	}	8250	}
8251		8251
8252	int64_t	8252	int64_t
8253	AMDGPUAsmParser::parseDPPCtrlPerm() {	8253	AMDGPUAsmParser::parseDPPCtrlPerm() {
8254	// quad_perm:[%d,%d,%d,%d]	8254	// quad_perm:[%d,%d,%d,%d]
8255		8255
8256	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	8256	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))
8257	return -1;	8257	return -1;
8258		8258
8259	int64_t Val = 0;	8259	int64_t Val = 0;
8260	for (int i = 0; i < 4; ++i) {	8260	for (int i = 0; i < 4; ++i) {
8261	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	8261	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))
8262	return -1;	8262	return -1;
8263		8263
8264	int64_t Temp;	8264	int64_t Temp;
8265	SMLoc Loc = getLoc();	8265	SMLoc Loc = getLoc();
8266	if (getParser().parseAbsoluteExpression(Temp))	8266	if (getParser().parseAbsoluteExpression(Temp))
8267	return -1;	8267	return -1;
8268	if (Temp < 0 \|\| Temp > 3) {	8268	if (Temp < 0 \|\| Temp > 3) {
8269	Error(Loc, "expected a 2-bit value");	8269	Error(Loc, "expected a 2-bit value");
8270	return -1;	8270	return -1;
8271	}	8271	}
8272		8272
8273	Val += (Temp << i * 2);	8273	Val += (Temp << i * 2);
8274	}	8274	}
8275		8275
8276	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	8276	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))
8277	return -1;	8277	return -1;
8278		8278
8279	return Val;	8279	return Val;
8280	}	8280	}
8281		8281
8282	int64_t	8282	int64_t
8283	AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {	8283	AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {
8284	using namespace AMDGPU::DPP;	8284	using namespace AMDGPU::DPP;
8285		8285
8286	// sel:%d	8286	// sel:%d
8287		8287
8288	int64_t Val;	8288	int64_t Val;
8289	SMLoc Loc = getLoc();	8289	SMLoc Loc = getLoc();
8290		8290
8291	if (getParser().parseAbsoluteExpression(Val))	8291	if (getParser().parseAbsoluteExpression(Val))
8292	return -1;	8292	return -1;
8293		8293
8294	struct DppCtrlCheck {	8294	struct DppCtrlCheck {
8295	int64_t Ctrl;	8295	int64_t Ctrl;
8296	int Lo;	8296	int Lo;
8297	int Hi;	8297	int Hi;
8298	};	8298	};
8299		8299
8300	DppCtrlCheck Check = StringSwitch(Ctrl)	8300	DppCtrlCheck Check = StringSwitch(Ctrl)
8301	.Case("wave_shl", {DppCtrl::WAVE_SHL1, 1, 1})	8301	.Case("wave_shl", {DppCtrl::WAVE_SHL1, 1, 1})
8302	.Case("wave_rol", {DppCtrl::WAVE_ROL1, 1, 1})	8302	.Case("wave_rol", {DppCtrl::WAVE_ROL1, 1, 1})
8303	.Case("wave_shr", {DppCtrl::WAVE_SHR1, 1, 1})	8303	.Case("wave_shr", {DppCtrl::WAVE_SHR1, 1, 1})
8304	.Case("wave_ror", {DppCtrl::WAVE_ROR1, 1, 1})	8304	.Case("wave_ror", {DppCtrl::WAVE_ROR1, 1, 1})
8305	.Case("row_shl", {DppCtrl::ROW_SHL0, 1, 15})	8305	.Case("row_shl", {DppCtrl::ROW_SHL0, 1, 15})
8306	.Case("row_shr", {DppCtrl::ROW_SHR0, 1, 15})	8306	.Case("row_shr", {DppCtrl::ROW_SHR0, 1, 15})
8307	.Case("row_ror", {DppCtrl::ROW_ROR0, 1, 15})	8307	.Case("row_ror", {DppCtrl::ROW_ROR0, 1, 15})
8308	.Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})	8308	.Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})
8309	.Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})	8309	.Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})
8310	.Case("row_newbcast", {DppCtrl::ROW_NEWBCAST_FIRST, 0, 15})	8310	.Case("row_newbcast", {DppCtrl::ROW_NEWBCAST_FIRST, 0, 15})
8311	.Default({-1, 0, 0});	8311	.Default({-1, 0, 0});
8312		8312
8313	bool Valid;	8313	bool Valid;
8314	if (Check.Ctrl == -1) {	8314	if (Check.Ctrl == -1) {
8315	Valid = (Ctrl == "row_bcast" && (Val == 15 \|\| Val == 31));	8315	Valid = (Ctrl == "row_bcast" && (Val == 15 \|\| Val == 31));
8316	Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31;	8316	Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31;
8317	} else {	8317	} else {
8318	Valid = Check.Lo <= Val && Val <= Check.Hi;	8318	Valid = Check.Lo <= Val && Val <= Check.Hi;
8319	Val = (Check.Lo == Check.Hi) ? Check.Ctrl : (Check.Ctrl \| Val);	8319	Val = (Check.Lo == Check.Hi) ? Check.Ctrl : (Check.Ctrl \| Val);
8320	}	8320	}
8321		8321
8322	if (!Valid) {	8322	if (!Valid) {
8323	Error(Loc, Twine("invalid ", Ctrl) + Twine(" value"));	8323	Error(Loc, Twine("invalid ", Ctrl) + Twine(" value"));
8324	return -1;	8324	return -1;
8325	}	8325	}
8326		8326
8327	return Val;	8327	return Val;
8328	}	8328	}
8329		8329
8330	ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {	8330	ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
8331	using namespace AMDGPU::DPP;	8331	using namespace AMDGPU::DPP;
8332		8332
8333	if (!isToken(AsmToken::Identifier) \|\|	8333	if (!isToken(AsmToken::Identifier) \|\|
8334	!isSupportedDPPCtrl(getTokenStr(), Operands))	8334	!isSupportedDPPCtrl(getTokenStr(), Operands))
8335	return ParseStatus::NoMatch;	8335	return ParseStatus::NoMatch;
8336		8336
8337	SMLoc S = getLoc();	8337	SMLoc S = getLoc();
8338	int64_t Val = -1;	8338	int64_t Val = -1;
8339	StringRef Ctrl;	8339	StringRef Ctrl;
8340		8340
8341	parseId(Ctrl);	8341	parseId(Ctrl);
8342		8342
8343	if (Ctrl == "row_mirror") {	8343	if (Ctrl == "row_mirror") {
8344	Val = DppCtrl::ROW_MIRROR;	8344	Val = DppCtrl::ROW_MIRROR;
8345	} else if (Ctrl == "row_half_mirror") {	8345	} else if (Ctrl == "row_half_mirror") {
8346	Val = DppCtrl::ROW_HALF_MIRROR;	8346	Val = DppCtrl::ROW_HALF_MIRROR;
8347	} else {	8347	} else {
8348	if (skipToken(AsmToken::Colon, "expected a colon")) {	8348	if (skipToken(AsmToken::Colon, "expected a colon")) {
8349	if (Ctrl == "quad_perm") {	8349	if (Ctrl == "quad_perm") {
8350	Val = parseDPPCtrlPerm();	8350	Val = parseDPPCtrlPerm();
8351	} else {	8351	} else {
8352	Val = parseDPPCtrlSel(Ctrl);	8352	Val = parseDPPCtrlSel(Ctrl);
8353	}	8353	}
8354	}	8354	}
8355	}	8355	}
8356		8356
8357	if (Val == -1)	8357	if (Val == -1)
8358	return ParseStatus::Failure;	8358	return ParseStatus::Failure;
8359		8359
8360	Operands.push_back(	8360	Operands.push_back(
8361	AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyDppCtrl));	8361	AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyDppCtrl));
8362	return ParseStatus::Success;	8362	return ParseStatus::Success;
8363	}	8363	}
8364		8364
8365	void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	8365	void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
8366	bool IsDPP8) {	8366	bool IsDPP8) {
8367	OptionalImmIndexMap OptionalIdx;	8367	OptionalImmIndexMap OptionalIdx;
8368	unsigned Opc = Inst.getOpcode();	8368	unsigned Opc = Inst.getOpcode();
8369	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	8369	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
8370		8370
8371	// MAC instructions are special because they have 'old'	8371	// MAC instructions are special because they have 'old'
8372	// operand which is not tied to dst (but assumed to be).	8372	// operand which is not tied to dst (but assumed to be).
8373	// They also have dummy unused src2_modifiers.	8373	// They also have dummy unused src2_modifiers.
8374	int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old);	8374	int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old);
8375	int Src2ModIdx =	8375	int Src2ModIdx =
8376	AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);	8376	AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
8377	bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&	8377	bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&
8378	Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;	8378	Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;
8379		8379
8380	unsigned I = 1;	8380	unsigned I = 1;
8381	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	8381	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
8382	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	8382	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8383	}	8383	}
8384		8384
8385	int Fi = 0;	8385	int Fi = 0;
8386	for (unsigned E = Operands.size(); I != E; ++I) {	8386	for (unsigned E = Operands.size(); I != E; ++I) {
8387		8387
8388	if (IsMAC) {	8388	if (IsMAC) {
8389	int NumOperands = Inst.getNumOperands();	8389	int NumOperands = Inst.getNumOperands();
8390	if (OldIdx == NumOperands) {	8390	if (OldIdx == NumOperands) {
8391	// Handle old operand	8391	// Handle old operand
8392	constexpr int DST_IDX = 0;	8392	constexpr int DST_IDX = 0;
8393	Inst.addOperand(Inst.getOperand(DST_IDX));	8393	Inst.addOperand(Inst.getOperand(DST_IDX));
8394	} else if (Src2ModIdx == NumOperands) {	8394	} else if (Src2ModIdx == NumOperands) {
8395	// Add unused dummy src2_modifiers	8395	// Add unused dummy src2_modifiers
8396	Inst.addOperand(MCOperand::createImm(0));	8396	Inst.addOperand(MCOperand::createImm(0));
8397	}	8397	}
8398	}	8398	}
8399		8399
8400	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	8400	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),
8401	MCOI::TIED_TO);	8401	MCOI::TIED_TO);
8402	if (TiedTo != -1) {	8402	if (TiedTo != -1) {
8403	assert((unsigned)TiedTo < Inst.getNumOperands());	8403	assert((unsigned)TiedTo < Inst.getNumOperands());
8404	// handle tied old or src2 for MAC instructions	8404	// handle tied old or src2 for MAC instructions
8405	Inst.addOperand(Inst.getOperand(TiedTo));	8405	Inst.addOperand(Inst.getOperand(TiedTo));
8406	}	8406	}
8407	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	8407	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8408	// Add the register arguments	8408	// Add the register arguments
8409	if (IsDPP8 && Op.isDppFI()) {	8409	if (IsDPP8 && Op.isDppFI()) {
8410	Fi = Op.getImm();	8410	Fi = Op.getImm();
8411	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	8411	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
8412	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	8412	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
8413	} else if (Op.isReg()) {	8413	} else if (Op.isReg()) {
8414	Op.addRegOperands(Inst, 1);	8414	Op.addRegOperands(Inst, 1);
8415	} else if (Op.isImm() &&	8415	} else if (Op.isImm() &&
8416	Desc.operands()[Inst.getNumOperands()].RegClass != -1) {	8416	Desc.operands()[Inst.getNumOperands()].RegClass != -1) {
8417	assert(!Op.IsImmKindLiteral() && "Cannot use literal with DPP");	8417	assert(!Op.IsImmKindLiteral() && "Cannot use literal with DPP");
8418	Op.addImmOperands(Inst, 1);	8418	Op.addImmOperands(Inst, 1);
8419	} else if (Op.isImm()) {	8419	} else if (Op.isImm()) {
8420	OptionalIdx[Op.getImmTy()] = I;	8420	OptionalIdx[Op.getImmTy()] = I;
8421	} else {	8421	} else {
8422	llvm_unreachable("unhandled operand type");	8422	llvm_unreachable("unhandled operand type");
8423	}	8423	}
8424	}	8424	}
8425	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	8425	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
8426	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	8426	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
8427		8427
8428	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	8428	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
8429	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);	8429	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
8430		8430
8431	if (Desc.TSFlags & SIInstrFlags::VOP3P)	8431	if (Desc.TSFlags & SIInstrFlags::VOP3P)
8432	cvtVOP3P(Inst, Operands, OptionalIdx);	8432	cvtVOP3P(Inst, Operands, OptionalIdx);
8433	else if (Desc.TSFlags & SIInstrFlags::VOP3)	8433	else if (Desc.TSFlags & SIInstrFlags::VOP3)
8434	cvtVOP3OpSel(Inst, Operands, OptionalIdx);	8434	cvtVOP3OpSel(Inst, Operands, OptionalIdx);
8435	else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {	8435	else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
8436	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	8436	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
8437	}	8437	}
8438		8438
8439	if (IsDPP8) {	8439	if (IsDPP8) {
8440	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);	8440	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);
8441	using namespace llvm::AMDGPU::DPP;	8441	using namespace llvm::AMDGPU::DPP;
8442	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	8442	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));
8443	} else {	8443	} else {
8444	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);	8444	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);
8445	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	8445	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
8446	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	8446	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
8447	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	8447	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
8448		8448
8449	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))	8449	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))
8450	addOptionalImmOperand(Inst, Operands, OptionalIdx,	8450	addOptionalImmOperand(Inst, Operands, OptionalIdx,
8451	AMDGPUOperand::ImmTyDppFI);	8451	AMDGPUOperand::ImmTyDppFI);
8452	}	8452	}
8453	}	8453	}
8454		8454
8455	void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {	8455	void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {
8456	OptionalImmIndexMap OptionalIdx;	8456	OptionalImmIndexMap OptionalIdx;
8457		8457
8458	unsigned I = 1;	8458	unsigned I = 1;
8459	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	8459	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
8460	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	8460	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
8461	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	8461	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8462	}	8462	}
8463		8463
8464	int Fi = 0;	8464	int Fi = 0;
8465	for (unsigned E = Operands.size(); I != E; ++I) {	8465	for (unsigned E = Operands.size(); I != E; ++I) {
8466	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	8466	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),
8467	MCOI::TIED_TO);	8467	MCOI::TIED_TO);
8468	if (TiedTo != -1) {	8468	if (TiedTo != -1) {
8469	assert((unsigned)TiedTo < Inst.getNumOperands());	8469	assert((unsigned)TiedTo < Inst.getNumOperands());
8470	// handle tied old or src2 for MAC instructions	8470	// handle tied old or src2 for MAC instructions
8471	Inst.addOperand(Inst.getOperand(TiedTo));	8471	Inst.addOperand(Inst.getOperand(TiedTo));
8472	}	8472	}
8473	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	8473	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8474	// Add the register arguments	8474	// Add the register arguments
8475	if (Op.isReg() && validateVccOperand(Op.getReg())) {	8475	if (Op.isReg() && validateVccOperand(Op.getReg())) {
8476	// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.	8476	// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.
8477	// Skip it.	8477	// Skip it.
8478	continue;	8478	continue;
8479	}	8479	}
8480		8480
8481	if (IsDPP8) {	8481	if (IsDPP8) {
8482	if (Op.isDPP8()) {	8482	if (Op.isDPP8()) {
8483	Op.addImmOperands(Inst, 1);	8483	Op.addImmOperands(Inst, 1);
8484	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	8484	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
8485	Op.addRegWithFPInputModsOperands(Inst, 2);	8485	Op.addRegWithFPInputModsOperands(Inst, 2);
8486	} else if (Op.isDppFI()) {	8486	} else if (Op.isDppFI()) {
8487	Fi = Op.getImm();	8487	Fi = Op.getImm();
8488	} else if (Op.isReg()) {	8488	} else if (Op.isReg()) {
8489	Op.addRegOperands(Inst, 1);	8489	Op.addRegOperands(Inst, 1);
8490	} else {	8490	} else {
8491	llvm_unreachable("Invalid operand type");	8491	llvm_unreachable("Invalid operand type");
8492	}	8492	}
8493	} else {	8493	} else {
8494	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	8494	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
8495	Op.addRegWithFPInputModsOperands(Inst, 2);	8495	Op.addRegWithFPInputModsOperands(Inst, 2);
8496	} else if (Op.isReg()) {	8496	} else if (Op.isReg()) {
8497	Op.addRegOperands(Inst, 1);	8497	Op.addRegOperands(Inst, 1);
8498	} else if (Op.isDPPCtrl()) {	8498	} else if (Op.isDPPCtrl()) {
8499	Op.addImmOperands(Inst, 1);	8499	Op.addImmOperands(Inst, 1);
8500	} else if (Op.isImm()) {	8500	} else if (Op.isImm()) {
8501	// Handle optional arguments	8501	// Handle optional arguments
8502	OptionalIdx[Op.getImmTy()] = I;	8502	OptionalIdx[Op.getImmTy()] = I;
8503	} else {	8503	} else {
8504	llvm_unreachable("Invalid operand type");	8504	llvm_unreachable("Invalid operand type");
8505	}	8505	}
8506	}	8506	}
8507	}	8507	}
8508		8508
8509	if (IsDPP8) {	8509	if (IsDPP8) {
8510	using namespace llvm::AMDGPU::DPP;	8510	using namespace llvm::AMDGPU::DPP;
8511	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	8511	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));
8512	} else {	8512	} else {
8513	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	8513	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
8514	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	8514	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
8515	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	8515	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
8516	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {	8516	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {
8517	addOptionalImmOperand(Inst, Operands, OptionalIdx,	8517	addOptionalImmOperand(Inst, Operands, OptionalIdx,
8518	AMDGPUOperand::ImmTyDppFI);	8518	AMDGPUOperand::ImmTyDppFI);
8519	}	8519	}
8520	}	8520	}
8521	}	8521	}
8522		8522
8523	//===----------------------------------------------------------------------===//	8523	//===----------------------------------------------------------------------===//
8524	// sdwa	8524	// sdwa
8525	//===----------------------------------------------------------------------===//	8525	//===----------------------------------------------------------------------===//
8526		8526
8527	ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,	8527	ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,
8528	StringRef Prefix,	8528	StringRef Prefix,
8529	AMDGPUOperand::ImmTy Type) {	8529	AMDGPUOperand::ImmTy Type) {
8530	using namespace llvm::AMDGPU::SDWA;	8530	using namespace llvm::AMDGPU::SDWA;
8531		8531
8532	SMLoc S = getLoc();	8532	SMLoc S = getLoc();
8533	StringRef Value;	8533	StringRef Value;
8534		8534
8535	SMLoc StringLoc;	8535	SMLoc StringLoc;
8536	ParseStatus Res = parseStringWithPrefix(Prefix, Value, StringLoc);	8536	ParseStatus Res = parseStringWithPrefix(Prefix, Value, StringLoc);
8537	if (!Res.isSuccess())	8537	if (!Res.isSuccess())
8538	return Res;	8538	return Res;
8539		8539
8540	int64_t Int;	8540	int64_t Int;
8541	Int = StringSwitch(Value)	8541	Int = StringSwitch(Value)
8542	.Case("BYTE_0", SdwaSel::BYTE_0)	8542	.Case("BYTE_0", SdwaSel::BYTE_0)
8543	.Case("BYTE_1", SdwaSel::BYTE_1)	8543	.Case("BYTE_1", SdwaSel::BYTE_1)
8544	.Case("BYTE_2", SdwaSel::BYTE_2)	8544	.Case("BYTE_2", SdwaSel::BYTE_2)
8545	.Case("BYTE_3", SdwaSel::BYTE_3)	8545	.Case("BYTE_3", SdwaSel::BYTE_3)
8546	.Case("WORD_0", SdwaSel::WORD_0)	8546	.Case("WORD_0", SdwaSel::WORD_0)
8547	.Case("WORD_1", SdwaSel::WORD_1)	8547	.Case("WORD_1", SdwaSel::WORD_1)
8548	.Case("DWORD", SdwaSel::DWORD)	8548	.Case("DWORD", SdwaSel::DWORD)
8549	.Default(0xffffffff);	8549	.Default(0xffffffff);
8550		8550
8551	if (Int == 0xffffffff)	8551	if (Int == 0xffffffff)
8552	return Error(StringLoc, "invalid " + Twine(Prefix) + " value");	8552	return Error(StringLoc, "invalid " + Twine(Prefix) + " value");
8553		8553
8554	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));	8554	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));
8555	return ParseStatus::Success;	8555	return ParseStatus::Success;
8556	}	8556	}
8557		8557
8558	ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {	8558	ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
8559	using namespace llvm::AMDGPU::SDWA;	8559	using namespace llvm::AMDGPU::SDWA;
8560		8560
8561	SMLoc S = getLoc();	8561	SMLoc S = getLoc();
8562	StringRef Value;	8562	StringRef Value;
8563		8563
8564	SMLoc StringLoc;	8564	SMLoc StringLoc;
8565	ParseStatus Res = parseStringWithPrefix("dst_unused", Value, StringLoc);	8565	ParseStatus Res = parseStringWithPrefix("dst_unused", Value, StringLoc);
8566	if (!Res.isSuccess())	8566	if (!Res.isSuccess())
8567	return Res;	8567	return Res;
8568		8568
8569	int64_t Int;	8569	int64_t Int;
8570	Int = StringSwitch(Value)	8570	Int = StringSwitch(Value)
8571	.Case("UNUSED_PAD", DstUnused::UNUSED_PAD)	8571	.Case("UNUSED_PAD", DstUnused::UNUSED_PAD)
8572	.Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)	8572	.Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)
8573	.Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)	8573	.Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)
8574	.Default(0xffffffff);	8574	.Default(0xffffffff);
8575		8575
8576	if (Int == 0xffffffff)	8576	if (Int == 0xffffffff)
8577	return Error(StringLoc, "invalid dst_unused value");	8577	return Error(StringLoc, "invalid dst_unused value");
8578		8578
8579	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));	8579	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));
8580	return ParseStatus::Success;	8580	return ParseStatus::Success;
8581	}	8581	}
8582		8582
8583	void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {	8583	void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {
8584	cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);	8584	cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);
8585	}	8585	}
8586		8586
8587	void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {	8587	void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {
8588	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);	8588	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);
8589	}	8589	}
8590		8590
8591	void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {	8591	void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {
8592	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);	8592	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);
8593	}	8593	}
8594		8594
8595	void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {	8595	void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {
8596	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);	8596	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);
8597	}	8597	}
8598		8598
8599	void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {	8599	void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {
8600	cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());	8600	cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());
8601	}	8601	}
8602		8602
8603	void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,	8603	void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,
8604	uint64_t BasicInstType,	8604	uint64_t BasicInstType,
8605	bool SkipDstVcc,	8605	bool SkipDstVcc,
8606	bool SkipSrcVcc) {	8606	bool SkipSrcVcc) {
8607	using namespace llvm::AMDGPU::SDWA;	8607	using namespace llvm::AMDGPU::SDWA;
8608		8608
8609	OptionalImmIndexMap OptionalIdx;	8609	OptionalImmIndexMap OptionalIdx;
8610	bool SkipVcc = SkipDstVcc \|\| SkipSrcVcc;	8610	bool SkipVcc = SkipDstVcc \|\| SkipSrcVcc;
8611	bool SkippedVcc = false;	8611	bool SkippedVcc = false;
8612		8612
8613	unsigned I = 1;	8613	unsigned I = 1;
8614	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	8614	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
8615	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	8615	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
8616	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	8616	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
8617	}	8617	}
8618		8618
8619	for (unsigned E = Operands.size(); I != E; ++I) {	8619	for (unsigned E = Operands.size(); I != E; ++I) {
8620	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	8620	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
8621	if (SkipVcc && !SkippedVcc && Op.isReg() &&	8621	if (SkipVcc && !SkippedVcc && Op.isReg() &&
8622	(Op.getReg() == AMDGPU::VCC \|\| Op.getReg() == AMDGPU::VCC_LO)) {	8622	(Op.getReg() == AMDGPU::VCC \|\| Op.getReg() == AMDGPU::VCC_LO)) {
8623	// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.	8623	// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.
8624	// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)	8624	// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)
8625	// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.	8625	// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.
8626	// Skip VCC only if we didn't skip it on previous iteration.	8626	// Skip VCC only if we didn't skip it on previous iteration.
8627	// Note that src0 and src1 occupy 2 slots each because of modifiers.	8627	// Note that src0 and src1 occupy 2 slots each because of modifiers.
8628	if (BasicInstType == SIInstrFlags::VOP2 &&	8628	if (BasicInstType == SIInstrFlags::VOP2 &&
8629	((SkipDstVcc && Inst.getNumOperands() == 1) \|\|	8629	((SkipDstVcc && Inst.getNumOperands() == 1) \|\|
8630	(SkipSrcVcc && Inst.getNumOperands() == 5))) {	8630	(SkipSrcVcc && Inst.getNumOperands() == 5))) {
8631	SkippedVcc = true;	8631	SkippedVcc = true;
8632	continue;	8632	continue;
8633	} else if (BasicInstType == SIInstrFlags::VOPC &&	8633	} else if (BasicInstType == SIInstrFlags::VOPC &&
8634	Inst.getNumOperands() == 0) {	8634	Inst.getNumOperands() == 0) {
8635	SkippedVcc = true;	8635	SkippedVcc = true;
8636	continue;	8636	continue;
8637	}	8637	}
8638	}	8638	}
8639	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	8639	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
8640	Op.addRegOrImmWithInputModsOperands(Inst, 2);	8640	Op.addRegOrImmWithInputModsOperands(Inst, 2);
8641	} else if (Op.isImm()) {	8641	} else if (Op.isImm()) {
8642	// Handle optional arguments	8642	// Handle optional arguments
8643	OptionalIdx[Op.getImmTy()] = I;	8643	OptionalIdx[Op.getImmTy()] = I;
8644	} else {	8644	} else {
8645	llvm_unreachable("Invalid operand type");	8645	llvm_unreachable("Invalid operand type");
8646	}	8646	}
8647	SkippedVcc = false;	8647	SkippedVcc = false;
8648	}	8648	}
8649		8649
8650	const unsigned Opc = Inst.getOpcode();	8650	const unsigned Opc = Inst.getOpcode();
8651	if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&	8651	if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&
8652	Opc != AMDGPU::V_NOP_sdwa_vi) {	8652	Opc != AMDGPU::V_NOP_sdwa_vi) {
8653	// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments	8653	// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments
8654	switch (BasicInstType) {	8654	switch (BasicInstType) {
8655	case SIInstrFlags::VOP1:	8655	case SIInstrFlags::VOP1:
8656	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	8656	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
8657	addOptionalImmOperand(Inst, Operands, OptionalIdx,	8657	addOptionalImmOperand(Inst, Operands, OptionalIdx,
8658	AMDGPUOperand::ImmTyClampSI, 0);	8658	AMDGPUOperand::ImmTyClampSI, 0);
8659		8659
8660	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	8660	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
8661	addOptionalImmOperand(Inst, Operands, OptionalIdx,	8661	addOptionalImmOperand(Inst, Operands, OptionalIdx,
8662	AMDGPUOperand::ImmTyOModSI, 0);	8662	AMDGPUOperand::ImmTyOModSI, 0);
8663		8663
8664	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))	8664	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))
8665	addOptionalImmOperand(Inst, Operands, OptionalIdx,	8665	addOptionalImmOperand(Inst, Operands, OptionalIdx,
8666	AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	8666	AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);
8667		8667
8668	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))	8668	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))
8669	addOptionalImmOperand(Inst, Operands, OptionalIdx,	8669	addOptionalImmOperand(Inst, Operands, OptionalIdx,
8670	AMDGPUOperand::ImmTySDWADstUnused,	8670	AMDGPUOperand::ImmTySDWADstUnused,
8671	DstUnused::UNUSED_PRESERVE);	8671	DstUnused::UNUSED_PRESERVE);
8672		8672
8673	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	8673	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
8674	break;	8674	break;
8675		8675
8676	case SIInstrFlags::VOP2:	8676	case SIInstrFlags::VOP2:
8677	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	8677	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
8678		8678
8679	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))	8679	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))
8680	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);	8680	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
8681		8681
8682	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	8682	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);
8683	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);	8683	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);
8684	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	8684	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
8685	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	8685	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
8686	break;	8686	break;
8687		8687
8688	case SIInstrFlags::VOPC:	8688	case SIInstrFlags::VOPC:
8689	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))	8689	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))
8690	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	8690	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
8691	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	8691	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);
8692	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	8692	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);
8693	break;	8693	break;
8694		8694
8695	default:	8695	default:
8696	llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");	8696	llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");
8697	}	8697	}
8698	}	8698	}
8699		8699
8700	// special case v_mac_{f16, f32}:	8700	// special case v_mac_{f16, f32}:
8701	// it has src2 register operand that is tied to dst operand	8701	// it has src2 register operand that is tied to dst operand
8702	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	8702	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|
8703	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	8703	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
8704	auto it = Inst.begin();	8704	auto it = Inst.begin();
8705	std::advance(	8705	std::advance(
8706	it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));	8706	it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
8707	Inst.insert(it, Inst.getOperand(0)); // src2 = dst	8707	Inst.insert(it, Inst.getOperand(0)); // src2 = dst
8708	}	8708	}
8709	}	8709	}
8710		8710
8711	/// Force static initialization.	8711	/// Force static initialization.
8712	extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {	8712	extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {
8713	RegisterMCAsmParser A(getTheR600Target());	8713	RegisterMCAsmParser A(getTheR600Target());
8714	RegisterMCAsmParser B(getTheGCNTarget());	8714	RegisterMCAsmParser B(getTheGCNTarget());
8715	}	8715	}
8716		8716
8717	#define GET_REGISTER_MATCHER	8717	#define GET_REGISTER_MATCHER
8718	#define GET_MATCHER_IMPLEMENTATION	8718	#define GET_MATCHER_IMPLEMENTATION
8719	#define GET_MNEMONIC_SPELL_CHECKER	8719	#define GET_MNEMONIC_SPELL_CHECKER
8720	#define GET_MNEMONIC_CHECKER	8720	#define GET_MNEMONIC_CHECKER
8721	#include "AMDGPUGenAsmMatcher.inc"	8721	#include "AMDGPUGenAsmMatcher.inc"
8722		8722
8723	ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,	8723	ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,
8724	unsigned MCK) {	8724	unsigned MCK) {
8725	switch (MCK) {	8725	switch (MCK) {
8726	case MCK_addr64:	8726	case MCK_addr64:
8727	return parseTokenOp("addr64", Operands);	8727	return parseTokenOp("addr64", Operands);
8728	case MCK_done:	8728	case MCK_done:
8729	return parseTokenOp("done", Operands);	8729	return parseTokenOp("done", Operands);
8730	case MCK_idxen:	8730	case MCK_idxen:
8731	return parseTokenOp("idxen", Operands);	8731	return parseTokenOp("idxen", Operands);
8732	case MCK_lds:	8732	case MCK_lds:
8733	return parseTokenOp("lds", Operands);	8733	return parseTokenOp("lds", Operands);
8734	case MCK_offen:	8734	case MCK_offen:
8735	return parseTokenOp("offen", Operands);	8735	return parseTokenOp("offen", Operands);
8736	case MCK_off:	8736	case MCK_off:
8737	return parseTokenOp("off", Operands);	8737	return parseTokenOp("off", Operands);
8738	case MCK_row_95_en:	8738	case MCK_row_95_en:
8739	return parseTokenOp("row_en", Operands);	8739	return parseTokenOp("row_en", Operands);
8740	case MCK_gds:	8740	case MCK_gds:
8741	return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);	8741	return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);
8742	case MCK_tfe:	8742	case MCK_tfe:
8743	return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);	8743	return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);
8744	}	8744	}
8745	return tryCustomParseOperand(Operands, MCK);	8745	return tryCustomParseOperand(Operands, MCK);
8746	}	8746	}
8747		8747
8748	// This function should be defined after auto-generated include so that we have	8748	// This function should be defined after auto-generated include so that we have
8749	// MatchClassKind enum defined	8749	// MatchClassKind enum defined
8750	unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,	8750	unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
8751	unsigned Kind) {	8751	unsigned Kind) {
8752	// Tokens like "glc" would be parsed as immediate operands in ParseOperand().	8752	// Tokens like "glc" would be parsed as immediate operands in ParseOperand().
8753	// But MatchInstructionImpl() expects to meet token and fails to validate	8753	// But MatchInstructionImpl() expects to meet token and fails to validate
8754	// operand. This method checks if we are given immediate operand but expect to	8754	// operand. This method checks if we are given immediate operand but expect to
8755	// get corresponding token.	8755	// get corresponding token.
8756	AMDGPUOperand &Operand = (AMDGPUOperand&)Op;	8756	AMDGPUOperand &Operand = (AMDGPUOperand&)Op;
8757	switch (Kind) {	8757	switch (Kind) {
8758	case MCK_addr64:	8758	case MCK_addr64:
8759	return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;	8759	return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;
8760	case MCK_gds:	8760	case MCK_gds:
8761	return Operand.isGDS() ? Match_Success : Match_InvalidOperand;	8761	return Operand.isGDS() ? Match_Success : Match_InvalidOperand;
8762	case MCK_lds:	8762	case MCK_lds:
8763	return Operand.isLDS() ? Match_Success : Match_InvalidOperand;	8763	return Operand.isLDS() ? Match_Success : Match_InvalidOperand;
8764	case MCK_idxen:	8764	case MCK_idxen:
8765	return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;	8765	return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;
8766	case MCK_offen:	8766	case MCK_offen:
8767	return Operand.isOffen() ? Match_Success : Match_InvalidOperand;	8767	return Operand.isOffen() ? Match_Success : Match_InvalidOperand;
8768	case MCK_tfe:	8768	case MCK_tfe:
8769	return Operand.isTFE() ? Match_Success : Match_InvalidOperand;	8769	return Operand.isTFE() ? Match_Success : Match_InvalidOperand;
8770	case MCK_SSrcB32:	8770	case MCK_SSrcB32:
8771	// When operands have expression values, they will return true for isToken,	8771	// When operands have expression values, they will return true for isToken,
8772	// because it is not possible to distinguish between a token and an	8772	// because it is not possible to distinguish between a token and an
8773	// expression at parse time. MatchInstructionImpl() will always try to	8773	// expression at parse time. MatchInstructionImpl() will always try to
8774	// match an operand as a token, when isToken returns true, and when the	8774	// match an operand as a token, when isToken returns true, and when the
8775	// name of the expression is not a valid token, the match will fail,	8775	// name of the expression is not a valid token, the match will fail,
8776	// so we need to handle it here.	8776	// so we need to handle it here.
8777	return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;	8777	return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;
8778	case MCK_SSrcF32:	8778	case MCK_SSrcF32:
8779	return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;	8779	return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;
8780	case MCK_SOPPBrTarget:	8780	case MCK_SOPPBrTarget:
8781	return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;	8781	return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;
8782	case MCK_VReg32OrOff:	8782	case MCK_VReg32OrOff:
8783	return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;	8783	return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;
8784	case MCK_InterpSlot:	8784	case MCK_InterpSlot:
8785	return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;	8785	return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;
8786	case MCK_InterpAttr:	8786	case MCK_InterpAttr:
8787	return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;	8787	return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;
8788	case MCK_InterpAttrChan:	8788	case MCK_InterpAttrChan:
8789	return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;	8789	return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;
8790	case MCK_SReg_64:	8790	case MCK_SReg_64:
8791	case MCK_SReg_64_XEXEC:	8791	case MCK_SReg_64_XEXEC:
8792	// Null is defined as a 32-bit register but	8792	// Null is defined as a 32-bit register but
8793	// it should also be enabled with 64-bit operands.	8793	// it should also be enabled with 64-bit operands.
8794	// The following code enables it for SReg_64 operands	8794	// The following code enables it for SReg_64 operands
8795	// used as source and destination. Remaining source	8795	// used as source and destination. Remaining source
8796	// operands are handled in isInlinableImm.	8796	// operands are handled in isInlinableImm.
8797	return Operand.isNull() ? Match_Success : Match_InvalidOperand;	8797	return Operand.isNull() ? Match_Success : Match_InvalidOperand;
8798	default:	8798	default:
8799	return Match_InvalidOperand;	8799	return Match_InvalidOperand;
8800	}	8800	}
8801	}	8801	}
8802		8802
8803	//===----------------------------------------------------------------------===//	8803	//===----------------------------------------------------------------------===//
8804	// endpgm	8804	// endpgm
8805	//===----------------------------------------------------------------------===//	8805	//===----------------------------------------------------------------------===//
8806		8806
8807	ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {	8807	ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {
8808	SMLoc S = getLoc();	8808	SMLoc S = getLoc();
8809	int64_t Imm = 0;	8809	int64_t Imm = 0;
8810		8810
8811	if (!parseExpr(Imm)) {	8811	if (!parseExpr(Imm)) {
8812	// The operand is optional, if not present default to 0	8812	// The operand is optional, if not present default to 0
8813	Imm = 0;	8813	Imm = 0;
8814	}	8814	}
8815		8815
8816	if (!isUInt<16>(Imm))	8816	if (!isUInt<16>(Imm))
8817	return Error(S, "expected a 16-bit value");	8817	return Error(S, "expected a 16-bit value");
8818		8818
8819	Operands.push_back(	8819	Operands.push_back(
8820	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));	8820	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));
8821	return ParseStatus::Success;	8821	return ParseStatus::Success;
8822	}	8822	}
8823		8823
8824	bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }	8824	bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }
8825		8825
8826	//===----------------------------------------------------------------------===//	8826	//===----------------------------------------------------------------------===//
8827	// LDSDIR	8827	// LDSDIR
8828	//===----------------------------------------------------------------------===//	8828	//===----------------------------------------------------------------------===//
8829		8829
8830	bool AMDGPUOperand::isWaitVDST() const {	8830	bool AMDGPUOperand::isWaitVDST() const {
8831	return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());	8831	return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());
8832	}	8832	}
8833		8833
8834	//===----------------------------------------------------------------------===//	8834	//===----------------------------------------------------------------------===//
8835	// VINTERP	8835	// VINTERP
8836	//===----------------------------------------------------------------------===//	8836	//===----------------------------------------------------------------------===//
8837		8837
8838	bool AMDGPUOperand::isWaitEXP() const {	8838	bool AMDGPUOperand::isWaitEXP() const {
8839	return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());	8839	return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());
8840	}	8840	}
8841		8841

Side By Side Comparison

Line Number	../DebugInfoTest/example_mips_dbg.ll	Hit count	Line Number	../DebugInfoTest/example_mips.ll	Hit count
1	//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//	---	1	//===- AMDGPUAsmParser.cpp - Parse SI asm to MCInst instructions ----------===//	---
2	//	---	2	//	---
3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.	---	3	// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.	---
4	// See https://llvm.org/LICENSE.txt for license information.	---	4	// See https://llvm.org/LICENSE.txt for license information.	---
5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception	---	5	// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception	---
6	//	---	6	//	---
7	//===----------------------------------------------------------------------===//	---	7	//===----------------------------------------------------------------------===//	---
8		---	8		---
9	#include "AMDKernelCodeT.h"	---	9	#include "AMDKernelCodeT.h"	---
10	#include "MCTargetDesc/AMDGPUMCTargetDesc.h"	---	10	#include "MCTargetDesc/AMDGPUMCTargetDesc.h"	---
11	#include "MCTargetDesc/AMDGPUTargetStreamer.h"	---	11	#include "MCTargetDesc/AMDGPUTargetStreamer.h"	---
12	#include "SIDefines.h"	---	12	#include "SIDefines.h"	---
13	#include "SIInstrInfo.h"	---	13	#include "SIInstrInfo.h"	---
14	#include "SIRegisterInfo.h"	---	14	#include "SIRegisterInfo.h"	---
15	#include "TargetInfo/AMDGPUTargetInfo.h"	---	15	#include "TargetInfo/AMDGPUTargetInfo.h"	---
16	#include "Utils/AMDGPUAsmUtils.h"	---	16	#include "Utils/AMDGPUAsmUtils.h"	---
17	#include "Utils/AMDGPUBaseInfo.h"	---	17	#include "Utils/AMDGPUBaseInfo.h"	---
18	#include "Utils/AMDKernelCodeTUtils.h"	---	18	#include "Utils/AMDKernelCodeTUtils.h"	---
19	#include "llvm/ADT/APFloat.h"	---	19	#include "llvm/ADT/APFloat.h"	---
20	#include "llvm/ADT/SmallBitVector.h"	---	20	#include "llvm/ADT/SmallBitVector.h"	---
21	#include "llvm/ADT/StringSet.h"	---	21	#include "llvm/ADT/StringSet.h"	---
22	#include "llvm/ADT/Twine.h"	---	22	#include "llvm/ADT/Twine.h"	---
23	#include "llvm/BinaryFormat/ELF.h"	---	23	#include "llvm/BinaryFormat/ELF.h"	---
24	#include "llvm/CodeGen/MachineValueType.h"	---	24	#include "llvm/CodeGen/MachineValueType.h"	---
25	#include "llvm/MC/MCAsmInfo.h"	---	25	#include "llvm/MC/MCAsmInfo.h"	---
26	#include "llvm/MC/MCContext.h"	---	26	#include "llvm/MC/MCContext.h"	---
27	#include "llvm/MC/MCExpr.h"	---	27	#include "llvm/MC/MCExpr.h"	---
28	#include "llvm/MC/MCInst.h"	---	28	#include "llvm/MC/MCInst.h"	---
29	#include "llvm/MC/MCInstrDesc.h"	---	29	#include "llvm/MC/MCInstrDesc.h"	---
30	#include "llvm/MC/MCParser/MCAsmLexer.h"	---	30	#include "llvm/MC/MCParser/MCAsmLexer.h"	---
31	#include "llvm/MC/MCParser/MCAsmParser.h"	---	31	#include "llvm/MC/MCParser/MCAsmParser.h"	---
32	#include "llvm/MC/MCParser/MCParsedAsmOperand.h"	---	32	#include "llvm/MC/MCParser/MCParsedAsmOperand.h"	---
33	#include "llvm/MC/MCParser/MCTargetAsmParser.h"	---	33	#include "llvm/MC/MCParser/MCTargetAsmParser.h"	---
34	#include "llvm/MC/MCSymbol.h"	---	34	#include "llvm/MC/MCSymbol.h"	---
35	#include "llvm/MC/TargetRegistry.h"	---	35	#include "llvm/MC/TargetRegistry.h"	---
36	#include "llvm/Support/AMDGPUMetadata.h"	---	36	#include "llvm/Support/AMDGPUMetadata.h"	---
37	#include "llvm/Support/AMDHSAKernelDescriptor.h"	---	37	#include "llvm/Support/AMDHSAKernelDescriptor.h"	---
38	#include "llvm/Support/Casting.h"	---	38	#include "llvm/Support/Casting.h"	---
39	#include "llvm/Support/MathExtras.h"	---	39	#include "llvm/Support/MathExtras.h"	---
40	#include "llvm/TargetParser/TargetParser.h"	---	40	#include "llvm/TargetParser/TargetParser.h"	---
41	#include	---	41	#include	---
42		---	42		---
43	using namespace llvm;	---	43	using namespace llvm;	---
44	using namespace llvm::AMDGPU;	---	44	using namespace llvm::AMDGPU;	---
45	using namespace llvm::amdhsa;	---	45	using namespace llvm::amdhsa;	---
46		---	46		---
47	namespace {	---	47	namespace {	---
48		---	48		---
49	class AMDGPUAsmParser;	---	49	class AMDGPUAsmParser;	---
50		---	50		---
51	enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL };	---	51	enum RegisterKind { IS_UNKNOWN, IS_VGPR, IS_SGPR, IS_AGPR, IS_TTMP, IS_SPECIAL };	---
52		---	52		---
53	//===----------------------------------------------------------------------===//	---	53	//===----------------------------------------------------------------------===//	---
54	// Operand	---	54	// Operand	---
55	//===----------------------------------------------------------------------===//	---	55	//===----------------------------------------------------------------------===//	---
56		---	56		---
57	class AMDGPUOperand : public MCParsedAsmOperand {	---	57	class AMDGPUOperand : public MCParsedAsmOperand {	---
58	enum KindTy {	---	58	enum KindTy {	---
59	Token,	---	59	Token,	---
60	Immediate,	---	60	Immediate,	---
61	Register,	---	61	Register,	---
62	Expression	---	62	Expression	---
63	} Kind;	---	63	} Kind;	---
64		---	64		---
65	SMLoc StartLoc, EndLoc;	---	65	SMLoc StartLoc, EndLoc;	---
66	const AMDGPUAsmParser *AsmParser;	---	66	const AMDGPUAsmParser *AsmParser;	---
67		---	67		---
68	public:	---	68	public:	---
69	AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)	0	69	AMDGPUOperand(KindTy Kind_, const AMDGPUAsmParser *AsmParser_)	0
70	: Kind(Kind_), AsmParser(AsmParser_) {}	0	70	: Kind(Kind_), AsmParser(AsmParser_) {}	0
71		---	71		---
72	using Ptr = std::unique_ptr;	---	72	using Ptr = std::unique_ptr;	---
73		---	73		---
74	struct Modifiers {	---	74	struct Modifiers {	---
75	bool Abs = false;	---	75	bool Abs = false;	---
76	bool Neg = false;	---	76	bool Neg = false;	---
77	bool Sext = false;	---	77	bool Sext = false;	---
78		---	78		---
79	bool hasFPModifiers() const { return Abs \|\| Neg; }	0	79	bool hasFPModifiers() const { return Abs \|\| Neg; }	0
80	bool hasIntModifiers() const { return Sext; }	0	80	bool hasIntModifiers() const { return Sext; }	0
81	bool hasModifiers() const { return hasFPModifiers() \|\| hasIntModifiers(); }	0	81	bool hasModifiers() const { return hasFPModifiers() \|\| hasIntModifiers(); }	0
82		---	82		---
83	int64_t getFPModifiersOperand() const {	0	83	int64_t getFPModifiersOperand() const {	0
84	int64_t Operand = 0;	0	84	int64_t Operand = 0;	0
85	Operand \|= Abs ? SISrcMods::ABS : 0u;	0	85	Operand \|= Abs ? SISrcMods::ABS : 0u;	0
86	Operand \|= Neg ? SISrcMods::NEG : 0u;	0	86	Operand \|= Neg ? SISrcMods::NEG : 0u;	0
87	return Operand;	0	87	return Operand;	0
88	}	---	88	}	---
89		---	89		---
90	int64_t getIntModifiersOperand() const {	0	90	int64_t getIntModifiersOperand() const {	0
91	int64_t Operand = 0;	0	91	int64_t Operand = 0;	0
92	Operand \|= Sext ? SISrcMods::SEXT : 0u;	0	92	Operand \|= Sext ? SISrcMods::SEXT : 0u;	0
93	return Operand;	0	93	return Operand;	0
94	}	---	94	}	---
95		---	95		---
96	int64_t getModifiersOperand() const {	0	96	int64_t getModifiersOperand() const {	0
97	assert(!(hasFPModifiers() && hasIntModifiers())	0	97	assert(!(hasFPModifiers() && hasIntModifiers())	0
98	&& "fp and int modifiers should not be used simultaneously");	---	98	&& "fp and int modifiers should not be used simultaneously");	---
99	if (hasFPModifiers()) {	0	99	if (hasFPModifiers()) {	0
100	return getFPModifiersOperand();	0	100	return getFPModifiersOperand();	0
101	} else if (hasIntModifiers()) {	0	101	} else if (hasIntModifiers()) {	0
102	return getIntModifiersOperand();	0	102	return getIntModifiersOperand();	0
103	} else {	---	103	} else {	---
104	return 0;	0	104	return 0;	0
105	}	---	105	}	---
106	}	---	106	}	---
107		---	107		---
108	friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);	---	108	friend raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods);	---
109	};	---	109	};	---
110		---	110		---
111	enum ImmTy {	---	111	enum ImmTy {	---
112	ImmTyNone,	---	112	ImmTyNone,	---
113	ImmTyGDS,	---	113	ImmTyGDS,	---
114	ImmTyLDS,	---	114	ImmTyLDS,	---
115	ImmTyOffen,	---	115	ImmTyOffen,	---
116	ImmTyIdxen,	---	116	ImmTyIdxen,	---
117	ImmTyAddr64,	---	117	ImmTyAddr64,	---
118	ImmTyOffset,	---	118	ImmTyOffset,	---
119	ImmTyInstOffset,	---	119	ImmTyInstOffset,	---
120	ImmTyOffset0,	---	120	ImmTyOffset0,	---
121	ImmTyOffset1,	---	121	ImmTyOffset1,	---
122	ImmTySMEMOffsetMod,	---	122	ImmTySMEMOffsetMod,	---
123	ImmTyCPol,	---	123	ImmTyCPol,	---
124	ImmTyTFE,	---	124	ImmTyTFE,	---
125	ImmTyD16,	---	125	ImmTyD16,	---
126	ImmTyClampSI,	---	126	ImmTyClampSI,	---
127	ImmTyOModSI,	---	127	ImmTyOModSI,	---
128	ImmTySDWADstSel,	---	128	ImmTySDWADstSel,	---
129	ImmTySDWASrc0Sel,	---	129	ImmTySDWASrc0Sel,	---
130	ImmTySDWASrc1Sel,	---	130	ImmTySDWASrc1Sel,	---
131	ImmTySDWADstUnused,	---	131	ImmTySDWADstUnused,	---
132	ImmTyDMask,	---	132	ImmTyDMask,	---
133	ImmTyDim,	---	133	ImmTyDim,	---
134	ImmTyUNorm,	---	134	ImmTyUNorm,	---
135	ImmTyDA,	---	135	ImmTyDA,	---
136	ImmTyR128A16,	---	136	ImmTyR128A16,	---
137	ImmTyA16,	---	137	ImmTyA16,	---
138	ImmTyLWE,	---	138	ImmTyLWE,	---
139	ImmTyExpTgt,	---	139	ImmTyExpTgt,	---
140	ImmTyExpCompr,	---	140	ImmTyExpCompr,	---
141	ImmTyExpVM,	---	141	ImmTyExpVM,	---
142	ImmTyFORMAT,	---	142	ImmTyFORMAT,	---
143	ImmTyHwreg,	---	143	ImmTyHwreg,	---
144	ImmTyOff,	---	144	ImmTyOff,	---
145	ImmTySendMsg,	---	145	ImmTySendMsg,	---
146	ImmTyInterpSlot,	---	146	ImmTyInterpSlot,	---
147	ImmTyInterpAttr,	---	147	ImmTyInterpAttr,	---
148	ImmTyInterpAttrChan,	---	148	ImmTyInterpAttrChan,	---
149	ImmTyOpSel,	---	149	ImmTyOpSel,	---
150	ImmTyOpSelHi,	---	150	ImmTyOpSelHi,	---
151	ImmTyNegLo,	---	151	ImmTyNegLo,	---
152	ImmTyNegHi,	---	152	ImmTyNegHi,	---
153	ImmTyDPP8,	---	153	ImmTyDPP8,	---
154	ImmTyDppCtrl,	---	154	ImmTyDppCtrl,	---
155	ImmTyDppRowMask,	---	155	ImmTyDppRowMask,	---
156	ImmTyDppBankMask,	---	156	ImmTyDppBankMask,	---
157	ImmTyDppBoundCtrl,	---	157	ImmTyDppBoundCtrl,	---
158	ImmTyDppFI,	---	158	ImmTyDppFI,	---
159	ImmTySwizzle,	---	159	ImmTySwizzle,	---
160	ImmTyGprIdxMode,	---	160	ImmTyGprIdxMode,	---
161	ImmTyHigh,	---	161	ImmTyHigh,	---
162	ImmTyBLGP,	---	162	ImmTyBLGP,	---
163	ImmTyCBSZ,	---	163	ImmTyCBSZ,	---
164	ImmTyABID,	---	164	ImmTyABID,	---
165	ImmTyEndpgm,	---	165	ImmTyEndpgm,	---
166	ImmTyWaitVDST,	---	166	ImmTyWaitVDST,	---
167	ImmTyWaitEXP,	---	167	ImmTyWaitEXP,	---
168	};	---	168	};	---
169		---	169		---
170	// Immediate operand kind.	---	170	// Immediate operand kind.	---
171	// It helps to identify the location of an offending operand after an error.	---	171	// It helps to identify the location of an offending operand after an error.	---
172	// Note that regular literals and mandatory literals (KImm) must be handled	---	172	// Note that regular literals and mandatory literals (KImm) must be handled	---
173	// differently. When looking for an offending operand, we should usually	---	173	// differently. When looking for an offending operand, we should usually	---
174	// ignore mandatory literals because they are part of the instruction and	---	174	// ignore mandatory literals because they are part of the instruction and	---
175	// cannot be changed. Report location of mandatory operands only for VOPD,	---	175	// cannot be changed. Report location of mandatory operands only for VOPD,	---
176	// when both OpX and OpY have a KImm and there are no other literals.	---	176	// when both OpX and OpY have a KImm and there are no other literals.	---
177	enum ImmKindTy {	---	177	enum ImmKindTy {	---
178	ImmKindTyNone,	---	178	ImmKindTyNone,	---
179	ImmKindTyLiteral,	---	179	ImmKindTyLiteral,	---
180	ImmKindTyMandatoryLiteral,	---	180	ImmKindTyMandatoryLiteral,	---
181	ImmKindTyConst,	---	181	ImmKindTyConst,	---
182	};	---	182	};	---
183		---	183		---
184	private:	---	184	private:	---
185	struct TokOp {	---	185	struct TokOp {	---
186	const char *Data;	---	186	const char *Data;	---
187	unsigned Length;	---	187	unsigned Length;	---
188	};	---	188	};	---
189		---	189		---
190	struct ImmOp {	---	190	struct ImmOp {	---
191	int64_t Val;	---	191	int64_t Val;	---
192	ImmTy Type;	---	192	ImmTy Type;	---
193	bool IsFPImm;	---	193	bool IsFPImm;	---
194	mutable ImmKindTy Kind;	---	194	mutable ImmKindTy Kind;	---
195	Modifiers Mods;	---	195	Modifiers Mods;	---
196	};	---	196	};	---
197		---	197		---
198	struct RegOp {	---	198	struct RegOp {	---
199	unsigned RegNo;	---	199	unsigned RegNo;	---
200	Modifiers Mods;	---	200	Modifiers Mods;	---
201	};	---	201	};	---
202		---	202		---
203	union {	---	203	union {	---
204	TokOp Tok;	---	204	TokOp Tok;	---
205	ImmOp Imm;	---	205	ImmOp Imm;	---
206	RegOp Reg;	---	206	RegOp Reg;	---
207	const MCExpr *Expr;	---	207	const MCExpr *Expr;	---
208	};	---	208	};	---
209		---	209		---
210	public:	---	210	public:	---
211	bool isToken() const override { return Kind == Token; }	0	211	bool isToken() const override { return Kind == Token; }	0
212		---	212		---
213	bool isSymbolRefExpr() const {	0	213	bool isSymbolRefExpr() const {	0
214	return isExpr() && Expr && isa(Expr);	0	214	return isExpr() && Expr && isa(Expr);	0
215	}	---	215	}	---
216		---	216		---
217	bool isImm() const override {	0	217	bool isImm() const override {	0
218	return Kind == Immediate;	0	218	return Kind == Immediate;	0
219	}	---	219	}	---
220		---	220		---
221	void setImmKindNone() const {	0	221	void setImmKindNone() const {	0
222	assert(isImm());	0	222	assert(isImm());	0
223	Imm.Kind = ImmKindTyNone;	0	223	Imm.Kind = ImmKindTyNone;	0
224	}	0	224	}	0
225		---	225		---
226	void setImmKindLiteral() const {	0	226	void setImmKindLiteral() const {	0
227	assert(isImm());	0	227	assert(isImm());	0
228	Imm.Kind = ImmKindTyLiteral;	0	228	Imm.Kind = ImmKindTyLiteral;	0
229	}	0	229	}	0
230		---	230		---
231	void setImmKindMandatoryLiteral() const {	0	231	void setImmKindMandatoryLiteral() const {	0
232	assert(isImm());	0	232	assert(isImm());	0
233	Imm.Kind = ImmKindTyMandatoryLiteral;	0	233	Imm.Kind = ImmKindTyMandatoryLiteral;	0
234	}	0	234	}	0
235		---	235		---
236	void setImmKindConst() const {	0	236	void setImmKindConst() const {	0
237	assert(isImm());	0	237	assert(isImm());	0
238	Imm.Kind = ImmKindTyConst;	0	238	Imm.Kind = ImmKindTyConst;	0
239	}	0	239	}	0
240		---	240		---
241	bool IsImmKindLiteral() const {	0	241	bool IsImmKindLiteral() const {	0
242	return isImm() && Imm.Kind == ImmKindTyLiteral;	0	242	return isImm() && Imm.Kind == ImmKindTyLiteral;	0
243	}	---	243	}	---
244		---	244		---
245	bool IsImmKindMandatoryLiteral() const {	0	245	bool IsImmKindMandatoryLiteral() const {	0
246	return isImm() && Imm.Kind == ImmKindTyMandatoryLiteral;	0	246	return isImm() && Imm.Kind == ImmKindTyMandatoryLiteral;	0
247	}	---	247	}	---
248		---	248		---
249	bool isImmKindConst() const {	0	249	bool isImmKindConst() const {	0
250	return isImm() && Imm.Kind == ImmKindTyConst;	0	250	return isImm() && Imm.Kind == ImmKindTyConst;	0
251	}	---	251	}	---
252		---	252		---
253	bool isInlinableImm(MVT type) const;	---	253	bool isInlinableImm(MVT type) const;	---
254	bool isLiteralImm(MVT type) const;	---	254	bool isLiteralImm(MVT type) const;	---
255		---	255		---
256	bool isRegKind() const {	0	256	bool isRegKind() const {	0
257	return Kind == Register;	0	257	return Kind == Register;	0
258	}	---	258	}	---
259		---	259		---
260	bool isReg() const override {	0	260	bool isReg() const override {	0
261	return isRegKind() && !hasModifiers();	0	261	return isRegKind() && !hasModifiers();	0
262	}	---	262	}	---
263		---	263		---
264	bool isRegOrInline(unsigned RCID, MVT type) const {	0	264	bool isRegOrInline(unsigned RCID, MVT type) const {	0
265	return isRegClass(RCID) \|\| isInlinableImm(type);	0	265	return isRegClass(RCID) \|\| isInlinableImm(type);	0
266	}	---	266	}	---
267		---	267		---
268	bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {	0	268	bool isRegOrImmWithInputMods(unsigned RCID, MVT type) const {	0
269	return isRegOrInline(RCID, type) \|\| isLiteralImm(type);	0	269	return isRegOrInline(RCID, type) \|\| isLiteralImm(type);	0
270	}	---	270	}	---
271		---	271		---
272	bool isRegOrImmWithInt16InputMods() const {	---	272	bool isRegOrImmWithInt16InputMods() const {	---
273	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);	---	273	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i16);	---
274	}	---	274	}	---
275		---	275		---
276	bool isRegOrImmWithInt32InputMods() const {	0	276	bool isRegOrImmWithInt32InputMods() const {	0
277	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);	0	277	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::i32);	0
278	}	---	278	}	---
279		---	279		---
280	bool isRegOrInlineImmWithInt16InputMods() const {	---	280	bool isRegOrInlineImmWithInt16InputMods() const {	---
281	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16);	---	281	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i16);	---
282	}	---	282	}	---
283		---	283		---
284	bool isRegOrInlineImmWithInt32InputMods() const {	0	284	bool isRegOrInlineImmWithInt32InputMods() const {	0
285	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32);	0	285	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::i32);	0
286	}	---	286	}	---
287		---	287		---
288	bool isRegOrImmWithInt64InputMods() const {	0	288	bool isRegOrImmWithInt64InputMods() const {	0
289	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);	0	289	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::i64);	0
290	}	---	290	}	---
291		---	291		---
292	bool isRegOrImmWithFP16InputMods() const {	0	292	bool isRegOrImmWithFP16InputMods() const {	0
293	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);	0	293	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f16);	0
294	}	---	294	}	---
295		---	295		---
296	bool isRegOrImmWithFP32InputMods() const {	0	296	bool isRegOrImmWithFP32InputMods() const {	0
297	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);	0	297	return isRegOrImmWithInputMods(AMDGPU::VS_32RegClassID, MVT::f32);	0
298	}	---	298	}	---
299		---	299		---
300	bool isRegOrImmWithFP64InputMods() const {	0	300	bool isRegOrImmWithFP64InputMods() const {	0
301	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);	0	301	return isRegOrImmWithInputMods(AMDGPU::VS_64RegClassID, MVT::f64);	0
302	}	---	302	}	---
303		---	303		---
304	bool isRegOrInlineImmWithFP16InputMods() const {	0	304	bool isRegOrInlineImmWithFP16InputMods() const {	0
305	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16);	0	305	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f16);	0
306	}	---	306	}	---
307		---	307		---
308	bool isRegOrInlineImmWithFP32InputMods() const {	0	308	bool isRegOrInlineImmWithFP32InputMods() const {	0
309	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32);	0	309	return isRegOrInline(AMDGPU::VS_32RegClassID, MVT::f32);	0
310	}	---	310	}	---
311		---	311		---
312		---	312		---
313	bool isVReg() const {	---	313	bool isVReg() const {	---
314	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	---	314	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	---
315	isRegClass(AMDGPU::VReg_64RegClassID) \|\|	---	315	isRegClass(AMDGPU::VReg_64RegClassID) \|\|	---
316	isRegClass(AMDGPU::VReg_96RegClassID) \|\|	---	316	isRegClass(AMDGPU::VReg_96RegClassID) \|\|	---
317	isRegClass(AMDGPU::VReg_128RegClassID) \|\|	---	317	isRegClass(AMDGPU::VReg_128RegClassID) \|\|	---
318	isRegClass(AMDGPU::VReg_160RegClassID) \|\|	---	318	isRegClass(AMDGPU::VReg_160RegClassID) \|\|	---
319	isRegClass(AMDGPU::VReg_192RegClassID) \|\|	---	319	isRegClass(AMDGPU::VReg_192RegClassID) \|\|	---
320	isRegClass(AMDGPU::VReg_256RegClassID) \|\|	---	320	isRegClass(AMDGPU::VReg_256RegClassID) \|\|	---
321	isRegClass(AMDGPU::VReg_512RegClassID) \|\|	---	321	isRegClass(AMDGPU::VReg_512RegClassID) \|\|	---
322	isRegClass(AMDGPU::VReg_1024RegClassID);	---	322	isRegClass(AMDGPU::VReg_1024RegClassID);	---
323	}	---	323	}	---
324		---	324		---
325	bool isVReg32() const {	0	325	bool isVReg32() const {	0
326	return isRegClass(AMDGPU::VGPR_32RegClassID);	0	326	return isRegClass(AMDGPU::VGPR_32RegClassID);	0
327	}	---	327	}	---
328		---	328		---
329	bool isVReg32OrOff() const {	0	329	bool isVReg32OrOff() const {	0
330	return isOff() \|\| isVReg32();	0	330	return isOff() \|\| isVReg32();	0
331	}	---	331	}	---
332		---	332		---
333	bool isNull() const {	0	333	bool isNull() const {	0
334	return isRegKind() && getReg() == AMDGPU::SGPR_NULL;	0	334	return isRegKind() && getReg() == AMDGPU::SGPR_NULL;	0
335	}	---	335	}	---
336		---	336		---
337	bool isVRegWithInputMods() const;	---	337	bool isVRegWithInputMods() const;	---
338	bool isT16VRegWithInputMods() const;	---	338	bool isT16VRegWithInputMods() const;	---
339		---	339		---
340	bool isSDWAOperand(MVT type) const;	---	340	bool isSDWAOperand(MVT type) const;	---
341	bool isSDWAFP16Operand() const;	---	341	bool isSDWAFP16Operand() const;	---
342	bool isSDWAFP32Operand() const;	---	342	bool isSDWAFP32Operand() const;	---
343	bool isSDWAInt16Operand() const;	---	343	bool isSDWAInt16Operand() const;	---
344	bool isSDWAInt32Operand() const;	---	344	bool isSDWAInt32Operand() const;	---
345		---	345		---
346	bool isImmTy(ImmTy ImmT) const {	0	346	bool isImmTy(ImmTy ImmT) const {	0
347	return isImm() && Imm.Type == ImmT;	0	347	return isImm() && Imm.Type == ImmT;	0
348	}	---	348	}	---
349		---	349		---
350	bool isImmLiteral() const { return isImmTy(ImmTyNone); }	0	350	bool isImmLiteral() const { return isImmTy(ImmTyNone); }	0
351		---	351		---
352	bool isImmModifier() const {	0	352	bool isImmModifier() const {	0
353	return isImm() && Imm.Type != ImmTyNone;	0	353	return isImm() && Imm.Type != ImmTyNone;	0
354	}	---	354	}	---
355		---	355		---
356	bool isClampSI() const { return isImmTy(ImmTyClampSI); }	0	356	bool isClampSI() const { return isImmTy(ImmTyClampSI); }	0
357	bool isOModSI() const { return isImmTy(ImmTyOModSI); }	0	357	bool isOModSI() const { return isImmTy(ImmTyOModSI); }	0
358	bool isDMask() const { return isImmTy(ImmTyDMask); }	0	358	bool isDMask() const { return isImmTy(ImmTyDMask); }	0
359	bool isDim() const { return isImmTy(ImmTyDim); }	0	359	bool isDim() const { return isImmTy(ImmTyDim); }	0
360	bool isUNorm() const { return isImmTy(ImmTyUNorm); }	0	360	bool isUNorm() const { return isImmTy(ImmTyUNorm); }	0
361	bool isDA() const { return isImmTy(ImmTyDA); }	0	361	bool isDA() const { return isImmTy(ImmTyDA); }	0
362	bool isR128A16() const { return isImmTy(ImmTyR128A16); }	0	362	bool isR128A16() const { return isImmTy(ImmTyR128A16); }	0
363	bool isA16() const { return isImmTy(ImmTyA16); }	0	363	bool isA16() const { return isImmTy(ImmTyA16); }	0
364	bool isLWE() const { return isImmTy(ImmTyLWE); }	0	364	bool isLWE() const { return isImmTy(ImmTyLWE); }	0
365	bool isOff() const { return isImmTy(ImmTyOff); }	0	365	bool isOff() const { return isImmTy(ImmTyOff); }	0
366	bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }	0	366	bool isExpTgt() const { return isImmTy(ImmTyExpTgt); }	0
367	bool isExpVM() const { return isImmTy(ImmTyExpVM); }	0	367	bool isExpVM() const { return isImmTy(ImmTyExpVM); }	0
368	bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }	0	368	bool isExpCompr() const { return isImmTy(ImmTyExpCompr); }	0
369	bool isOffen() const { return isImmTy(ImmTyOffen); }	0	369	bool isOffen() const { return isImmTy(ImmTyOffen); }	0
370	bool isIdxen() const { return isImmTy(ImmTyIdxen); }	0	370	bool isIdxen() const { return isImmTy(ImmTyIdxen); }	0
371	bool isAddr64() const { return isImmTy(ImmTyAddr64); }	0	371	bool isAddr64() const { return isImmTy(ImmTyAddr64); }	0
372	bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }	0	372	bool isOffset() const { return isImmTy(ImmTyOffset) && isUInt<16>(getImm()); }	0
373	bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }	0	373	bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); }	0
374	bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }	0	374	bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); }	0
375	bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }	0	375	bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); }	0
376	bool isFlatOffset() const { return isImmTy(ImmTyOffset) \|\| isImmTy(ImmTyInstOffset); }	0	376	bool isFlatOffset() const { return isImmTy(ImmTyOffset) \|\| isImmTy(ImmTyInstOffset); }	0
377	bool isGDS() const { return isImmTy(ImmTyGDS); }	0	377	bool isGDS() const { return isImmTy(ImmTyGDS); }	0
378	bool isLDS() const { return isImmTy(ImmTyLDS); }	0	378	bool isLDS() const { return isImmTy(ImmTyLDS); }	0
379	bool isCPol() const { return isImmTy(ImmTyCPol); }	0	379	bool isCPol() const { return isImmTy(ImmTyCPol); }	0
380	bool isTFE() const { return isImmTy(ImmTyTFE); }	0	380	bool isTFE() const { return isImmTy(ImmTyTFE); }	0
381	bool isD16() const { return isImmTy(ImmTyD16); }	0	381	bool isD16() const { return isImmTy(ImmTyD16); }	0
382	bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }	0	382	bool isFORMAT() const { return isImmTy(ImmTyFORMAT) && isUInt<7>(getImm()); }	0
383	bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }	0	383	bool isDppBankMask() const { return isImmTy(ImmTyDppBankMask); }	0
384	bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }	0	384	bool isDppRowMask() const { return isImmTy(ImmTyDppRowMask); }	0
385	bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }	0	385	bool isDppBoundCtrl() const { return isImmTy(ImmTyDppBoundCtrl); }	0
386	bool isDppFI() const { return isImmTy(ImmTyDppFI); }	0	386	bool isDppFI() const { return isImmTy(ImmTyDppFI); }	0
387	bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }	0	387	bool isSDWADstSel() const { return isImmTy(ImmTySDWADstSel); }	0
388	bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }	0	388	bool isSDWASrc0Sel() const { return isImmTy(ImmTySDWASrc0Sel); }	0
389	bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); }	0	389	bool isSDWASrc1Sel() const { return isImmTy(ImmTySDWASrc1Sel); }	0
390	bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }	0	390	bool isSDWADstUnused() const { return isImmTy(ImmTySDWADstUnused); }	0
391	bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }	0	391	bool isInterpSlot() const { return isImmTy(ImmTyInterpSlot); }	0
392	bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }	0	392	bool isInterpAttr() const { return isImmTy(ImmTyInterpAttr); }	0
393	bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }	0	393	bool isInterpAttrChan() const { return isImmTy(ImmTyInterpAttrChan); }	0
394	bool isOpSel() const { return isImmTy(ImmTyOpSel); }	0	394	bool isOpSel() const { return isImmTy(ImmTyOpSel); }	0
395	bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }	0	395	bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); }	0
396	bool isNegLo() const { return isImmTy(ImmTyNegLo); }	0	396	bool isNegLo() const { return isImmTy(ImmTyNegLo); }	0
397	bool isNegHi() const { return isImmTy(ImmTyNegHi); }	0	397	bool isNegHi() const { return isImmTy(ImmTyNegHi); }	0
398	bool isHigh() const { return isImmTy(ImmTyHigh); }	0	398	bool isHigh() const { return isImmTy(ImmTyHigh); }	0
399		---	399		---
400	bool isRegOrImm() const {	0	400	bool isRegOrImm() const {	0
401	return isReg() \|\| isImm();	0	401	return isReg() \|\| isImm();	0
402	}	---	402	}	---
403		---	403		---
404	bool isRegClass(unsigned RCID) const;	---	404	bool isRegClass(unsigned RCID) const;	---
405		---	405		---
406	bool isInlineValue() const;	---	406	bool isInlineValue() const;	---
407		---	407		---
408	bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {	0	408	bool isRegOrInlineNoMods(unsigned RCID, MVT type) const {	0
409	return isRegOrInline(RCID, type) && !hasModifiers();	0	409	return isRegOrInline(RCID, type) && !hasModifiers();	0
410	}	---	410	}	---
411		---	411		---
412	bool isSCSrcB16() const {	---	412	bool isSCSrcB16() const {	---
413	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);	---	413	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i16);	---
414	}	---	414	}	---
415		---	415		---
416	bool isSCSrcV2B16() const {	---	416	bool isSCSrcV2B16() const {	---
417	return isSCSrcB16();	---	417	return isSCSrcB16();	---
418	}	---	418	}	---
419		---	419		---
420	bool isSCSrcB32() const {	0	420	bool isSCSrcB32() const {	0
421	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);	0	421	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::i32);	0
422	}	---	422	}	---
423		---	423		---
424	bool isSCSrcB64() const {	0	424	bool isSCSrcB64() const {	0
425	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);	0	425	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::i64);	0
426	}	---	426	}	---
427		---	427		---
428	bool isBoolReg() const;	---	428	bool isBoolReg() const;	---
429		---	429		---
430	bool isSCSrcF16() const {	---	430	bool isSCSrcF16() const {	---
431	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);	---	431	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f16);	---
432	}	---	432	}	---
433		---	433		---
434	bool isSCSrcV2F16() const {	---	434	bool isSCSrcV2F16() const {	---
435	return isSCSrcF16();	---	435	return isSCSrcF16();	---
436	}	---	436	}	---
437		---	437		---
438	bool isSCSrcF32() const {	---	438	bool isSCSrcF32() const {	---
439	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);	---	439	return isRegOrInlineNoMods(AMDGPU::SReg_32RegClassID, MVT::f32);	---
440	}	---	440	}	---
441		---	441		---
442	bool isSCSrcF64() const {	---	442	bool isSCSrcF64() const {	---
443	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);	---	443	return isRegOrInlineNoMods(AMDGPU::SReg_64RegClassID, MVT::f64);	---
444	}	---	444	}	---
445		---	445		---
446	bool isSSrcB32() const {	0	446	bool isSSrcB32() const {	0
447	return isSCSrcB32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	0	447	return isSCSrcB32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	0
448	}	---	448	}	---
449		---	449		---
450	bool isSSrcB16() const {	---	450	bool isSSrcB16() const {	---
451	return isSCSrcB16() \|\| isLiteralImm(MVT::i16);	---	451	return isSCSrcB16() \|\| isLiteralImm(MVT::i16);	---
452	}	---	452	}	---
453		---	453		---
454	bool isSSrcV2B16() const {	---	454	bool isSSrcV2B16() const {	---
455	llvm_unreachable("cannot happen");	---	455	llvm_unreachable("cannot happen");	---
456	return isSSrcB16();	---	456	return isSSrcB16();	---
457	}	---	457	}	---
458		---	458		---
459	bool isSSrcB64() const {	0	459	bool isSSrcB64() const {	0
460	// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.	---	460	// TODO: Find out how SALU supports extension of 32-bit literals to 64 bits.	---
461	// See isVSrc64().	---	461	// See isVSrc64().	---
462	return isSCSrcB64() \|\| isLiteralImm(MVT::i64);	0	462	return isSCSrcB64() \|\| isLiteralImm(MVT::i64);	0
463	}	---	463	}	---
464		---	464		---
465	bool isSSrcF32() const {	0	465	bool isSSrcF32() const {	0
466	return isSCSrcB32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	0	466	return isSCSrcB32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	0
467	}	---	467	}	---
468		---	468		---
469	bool isSSrcF64() const {	---	469	bool isSSrcF64() const {	---
470	return isSCSrcB64() \|\| isLiteralImm(MVT::f64);	---	470	return isSCSrcB64() \|\| isLiteralImm(MVT::f64);	---
471	}	---	471	}	---
472		---	472		---
473	bool isSSrcF16() const {	---	473	bool isSSrcF16() const {	---
474	return isSCSrcB16() \|\| isLiteralImm(MVT::f16);	---	474	return isSCSrcB16() \|\| isLiteralImm(MVT::f16);	---
475	}	---	475	}	---
476		---	476		---
477	bool isSSrcV2F16() const {	---	477	bool isSSrcV2F16() const {	---
478	llvm_unreachable("cannot happen");	---	478	llvm_unreachable("cannot happen");	---
479	return isSSrcF16();	---	479	return isSSrcF16();	---
480	}	---	480	}	---
481		---	481		---
482	bool isSSrcV2FP32() const {	---	482	bool isSSrcV2FP32() const {	---
483	llvm_unreachable("cannot happen");	---	483	llvm_unreachable("cannot happen");	---
484	return isSSrcF32();	---	484	return isSSrcF32();	---
485	}	---	485	}	---
486		---	486		---
487	bool isSCSrcV2FP32() const {	---	487	bool isSCSrcV2FP32() const {	---
488	llvm_unreachable("cannot happen");	---	488	llvm_unreachable("cannot happen");	---
489	return isSCSrcF32();	---	489	return isSCSrcF32();	---
490	}	---	490	}	---
491		---	491		---
492	bool isSSrcV2INT32() const {	---	492	bool isSSrcV2INT32() const {	---
493	llvm_unreachable("cannot happen");	---	493	llvm_unreachable("cannot happen");	---
494	return isSSrcB32();	---	494	return isSSrcB32();	---
495	}	---	495	}	---
496		---	496		---
497	bool isSCSrcV2INT32() const {	---	497	bool isSCSrcV2INT32() const {	---
498	llvm_unreachable("cannot happen");	---	498	llvm_unreachable("cannot happen");	---
499	return isSCSrcB32();	---	499	return isSCSrcB32();	---
500	}	---	500	}	---
501		---	501		---
502	bool isSSrcOrLdsB32() const {	0	502	bool isSSrcOrLdsB32() const {	0
503	return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) \|\|	0	503	return isRegOrInlineNoMods(AMDGPU::SRegOrLds_32RegClassID, MVT::i32) \|\|	0
504	isLiteralImm(MVT::i32) \|\| isExpr();	0	504	isLiteralImm(MVT::i32) \|\| isExpr();	0
505	}	---	505	}	---
506		---	506		---
507	bool isVCSrcB32() const {	0	507	bool isVCSrcB32() const {	0
508	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);	0	508	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i32);	0
509	}	---	509	}	---
510		---	510		---
511	bool isVCSrcB64() const {	---	511	bool isVCSrcB64() const {	---
512	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);	---	512	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::i64);	---
513	}	---	513	}	---
514		---	514		---
515	bool isVCSrcTB16_Lo128() const {	0	515	bool isVCSrcTB16_Lo128() const {	0
516	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16);	0	516	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::i16);	0
517	}	---	517	}	---
518		---	518		---
519	bool isVCSrcB16() const {	0	519	bool isVCSrcB16() const {	0
520	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16);	0	520	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::i16);	0
521	}	---	521	}	---
522		---	522		---
523	bool isVCSrcV2B16() const {	0	523	bool isVCSrcV2B16() const {	0
524	return isVCSrcB16();	0	524	return isVCSrcB16();	0
525	}	---	525	}	---
526		---	526		---
527	bool isVCSrcF32() const {	0	527	bool isVCSrcF32() const {	0
528	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);	0	528	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f32);	0
529	}	---	529	}	---
530		---	530		---
531	bool isVCSrcF64() const {	0	531	bool isVCSrcF64() const {	0
532	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);	0	532	return isRegOrInlineNoMods(AMDGPU::VS_64RegClassID, MVT::f64);	0
533	}	---	533	}	---
534		---	534		---
535	bool isVCSrcTF16_Lo128() const {	0	535	bool isVCSrcTF16_Lo128() const {	0
536	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16);	0	536	return isRegOrInlineNoMods(AMDGPU::VS_32_Lo128RegClassID, MVT::f16);	0
537	}	---	537	}	---
538		---	538		---
539	bool isVCSrcF16() const {	0	539	bool isVCSrcF16() const {	0
540	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);	0	540	return isRegOrInlineNoMods(AMDGPU::VS_32RegClassID, MVT::f16);	0
541	}	---	541	}	---
542		---	542		---
543	bool isVCSrcV2F16() const {	0	543	bool isVCSrcV2F16() const {	0
544	return isVCSrcF16();	0	544	return isVCSrcF16();	0
545	}	---	545	}	---
546		---	546		---
547	bool isVSrcB32() const {	0	547	bool isVSrcB32() const {	0
548	return isVCSrcF32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	0	548	return isVCSrcF32() \|\| isLiteralImm(MVT::i32) \|\| isExpr();	0
549	}	---	549	}	---
550		---	550		---
551	bool isVSrcB64() const {	0	551	bool isVSrcB64() const {	0
552	return isVCSrcF64() \|\| isLiteralImm(MVT::i64);	0	552	return isVCSrcF64() \|\| isLiteralImm(MVT::i64);	0
553	}	---	553	}	---
554		---	554		---
555	bool isVSrcTB16_Lo128() const {	0	555	bool isVSrcTB16_Lo128() const {	0
556	return isVCSrcTB16_Lo128() \|\| isLiteralImm(MVT::i16);	0	556	return isVCSrcTB16_Lo128() \|\| isLiteralImm(MVT::i16);	0
557	}	---	557	}	---
558		---	558		---
559	bool isVSrcB16() const {	0	559	bool isVSrcB16() const {	0
560	return isVCSrcB16() \|\| isLiteralImm(MVT::i16);	0	560	return isVCSrcB16() \|\| isLiteralImm(MVT::i16);	0
561	}	---	561	}	---
562		---	562		---
563	bool isVSrcV2B16() const {	0	563	bool isVSrcV2B16() const {	0
564	return isVSrcB16() \|\| isLiteralImm(MVT::v2i16);	0	564	return isVSrcB16() \|\| isLiteralImm(MVT::v2i16);	0
565	}	---	565	}	---
566		---	566		---
567	bool isVCSrcV2FP32() const {	---	567	bool isVCSrcV2FP32() const {	---
568	return isVCSrcF64();	---	568	return isVCSrcF64();	---
569	}	---	569	}	---
570		---	570		---
571	bool isVSrcV2FP32() const {	0	571	bool isVSrcV2FP32() const {	0
572	return isVSrcF64() \|\| isLiteralImm(MVT::v2f32);	0	572	return isVSrcF64() \|\| isLiteralImm(MVT::v2f32);	0
573	}	---	573	}	---
574		---	574		---
575	bool isVCSrcV2INT32() const {	---	575	bool isVCSrcV2INT32() const {	---
576	return isVCSrcB64();	---	576	return isVCSrcB64();	---
577	}	---	577	}	---
578		---	578		---
579	bool isVSrcV2INT32() const {	0	579	bool isVSrcV2INT32() const {	0
580	return isVSrcB64() \|\| isLiteralImm(MVT::v2i32);	0	580	return isVSrcB64() \|\| isLiteralImm(MVT::v2i32);	0
581	}	---	581	}	---
582		---	582		---
583	bool isVSrcF32() const {	0	583	bool isVSrcF32() const {	0
584	return isVCSrcF32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	0	584	return isVCSrcF32() \|\| isLiteralImm(MVT::f32) \|\| isExpr();	0
585	}	---	585	}	---
586		---	586		---
587	bool isVSrcF64() const {	0	587	bool isVSrcF64() const {	0
588	return isVCSrcF64() \|\| isLiteralImm(MVT::f64);	0	588	return isVCSrcF64() \|\| isLiteralImm(MVT::f64);	0
589	}	---	589	}	---
590		---	590		---
591	bool isVSrcTF16_Lo128() const {	0	591	bool isVSrcTF16_Lo128() const {	0
592	return isVCSrcTF16_Lo128() \|\| isLiteralImm(MVT::f16);	0	592	return isVCSrcTF16_Lo128() \|\| isLiteralImm(MVT::f16);	0
593	}	---	593	}	---
594		---	594		---
595	bool isVSrcF16() const {	0	595	bool isVSrcF16() const {	0
596	return isVCSrcF16() \|\| isLiteralImm(MVT::f16);	0	596	return isVCSrcF16() \|\| isLiteralImm(MVT::f16);	0
597	}	---	597	}	---
598		---	598		---
599	bool isVSrcV2F16() const {	0	599	bool isVSrcV2F16() const {	0
600	return isVSrcF16() \|\| isLiteralImm(MVT::v2f16);	0	600	return isVSrcF16() \|\| isLiteralImm(MVT::v2f16);	0
601	}	---	601	}	---
602		---	602		---
603	bool isVISrcB32() const {	---	603	bool isVISrcB32() const {	---
604	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32);	---	604	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i32);	---
605	}	---	605	}	---
606		---	606		---
607	bool isVISrcB16() const {	---	607	bool isVISrcB16() const {	---
608	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16);	---	608	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::i16);	---
609	}	---	609	}	---
610		---	610		---
611	bool isVISrcV2B16() const {	---	611	bool isVISrcV2B16() const {	---
612	return isVISrcB16();	---	612	return isVISrcB16();	---
613	}	---	613	}	---
614		---	614		---
615	bool isVISrcF32() const {	---	615	bool isVISrcF32() const {	---
616	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32);	---	616	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f32);	---
617	}	---	617	}	---
618		---	618		---
619	bool isVISrcF16() const {	---	619	bool isVISrcF16() const {	---
620	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16);	---	620	return isRegOrInlineNoMods(AMDGPU::VGPR_32RegClassID, MVT::f16);	---
621	}	---	621	}	---
622		---	622		---
623	bool isVISrcV2F16() const {	---	623	bool isVISrcV2F16() const {	---
624	return isVISrcF16() \|\| isVISrcB32();	---	624	return isVISrcF16() \|\| isVISrcB32();	---
625	}	---	625	}	---
626		---	626		---
627	bool isVISrc_64B64() const {	---	627	bool isVISrc_64B64() const {	---
628	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64);	---	628	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i64);	---
629	}	---	629	}	---
630		---	630		---
631	bool isVISrc_64F64() const {	0	631	bool isVISrc_64F64() const {	0
632	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64);	0	632	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f64);	0
633	}	---	633	}	---
634		---	634		---
635	bool isVISrc_64V2FP32() const {	---	635	bool isVISrc_64V2FP32() const {	---
636	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32);	---	636	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::f32);	---
637	}	---	637	}	---
638		---	638		---
639	bool isVISrc_64V2INT32() const {	---	639	bool isVISrc_64V2INT32() const {	---
640	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32);	---	640	return isRegOrInlineNoMods(AMDGPU::VReg_64RegClassID, MVT::i32);	---
641	}	---	641	}	---
642		---	642		---
643	bool isVISrc_256B64() const {	---	643	bool isVISrc_256B64() const {	---
644	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64);	---	644	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i64);	---
645	}	---	645	}	---
646		---	646		---
647	bool isVISrc_256F64() const {	0	647	bool isVISrc_256F64() const {	0
648	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64);	0	648	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f64);	0
649	}	---	649	}	---
650		---	650		---
651	bool isVISrc_128B16() const {	---	651	bool isVISrc_128B16() const {	---
652	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16);	---	652	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i16);	---
653	}	---	653	}	---
654		---	654		---
655	bool isVISrc_128V2B16() const {	---	655	bool isVISrc_128V2B16() const {	---
656	return isVISrc_128B16();	---	656	return isVISrc_128B16();	---
657	}	---	657	}	---
658		---	658		---
659	bool isVISrc_128B32() const {	0	659	bool isVISrc_128B32() const {	0
660	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32);	0	660	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::i32);	0
661	}	---	661	}	---
662		---	662		---
663	bool isVISrc_128F32() const {	0	663	bool isVISrc_128F32() const {	0
664	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32);	0	664	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f32);	0
665	}	---	665	}	---
666		---	666		---
667	bool isVISrc_256V2FP32() const {	---	667	bool isVISrc_256V2FP32() const {	---
668	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32);	---	668	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::f32);	---
669	}	---	669	}	---
670		---	670		---
671	bool isVISrc_256V2INT32() const {	---	671	bool isVISrc_256V2INT32() const {	---
672	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32);	---	672	return isRegOrInlineNoMods(AMDGPU::VReg_256RegClassID, MVT::i32);	---
673	}	---	673	}	---
674		---	674		---
675	bool isVISrc_512B32() const {	0	675	bool isVISrc_512B32() const {	0
676	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32);	0	676	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i32);	0
677	}	---	677	}	---
678		---	678		---
679	bool isVISrc_512B16() const {	---	679	bool isVISrc_512B16() const {	---
680	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16);	---	680	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::i16);	---
681	}	---	681	}	---
682		---	682		---
683	bool isVISrc_512V2B16() const {	---	683	bool isVISrc_512V2B16() const {	---
684	return isVISrc_512B16();	---	684	return isVISrc_512B16();	---
685	}	---	685	}	---
686		---	686		---
687	bool isVISrc_512F32() const {	0	687	bool isVISrc_512F32() const {	0
688	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32);	0	688	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f32);	0
689	}	---	689	}	---
690		---	690		---
691	bool isVISrc_512F16() const {	---	691	bool isVISrc_512F16() const {	---
692	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16);	---	692	return isRegOrInlineNoMods(AMDGPU::VReg_512RegClassID, MVT::f16);	---
693	}	---	693	}	---
694		---	694		---
695	bool isVISrc_512V2F16() const {	---	695	bool isVISrc_512V2F16() const {	---
696	return isVISrc_512F16() \|\| isVISrc_512B32();	---	696	return isVISrc_512F16() \|\| isVISrc_512B32();	---
697	}	---	697	}	---
698		---	698		---
699	bool isVISrc_1024B32() const {	0	699	bool isVISrc_1024B32() const {	0
700	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32);	0	700	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i32);	0
701	}	---	701	}	---
702		---	702		---
703	bool isVISrc_1024B16() const {	---	703	bool isVISrc_1024B16() const {	---
704	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16);	---	704	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::i16);	---
705	}	---	705	}	---
706		---	706		---
707	bool isVISrc_1024V2B16() const {	---	707	bool isVISrc_1024V2B16() const {	---
708	return isVISrc_1024B16();	---	708	return isVISrc_1024B16();	---
709	}	---	709	}	---
710		---	710		---
711	bool isVISrc_1024F32() const {	0	711	bool isVISrc_1024F32() const {	0
712	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32);	0	712	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f32);	0
713	}	---	713	}	---
714		---	714		---
715	bool isVISrc_1024F16() const {	---	715	bool isVISrc_1024F16() const {	---
716	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16);	---	716	return isRegOrInlineNoMods(AMDGPU::VReg_1024RegClassID, MVT::f16);	---
717	}	---	717	}	---
718		---	718		---
719	bool isVISrc_1024V2F16() const {	---	719	bool isVISrc_1024V2F16() const {	---
720	return isVISrc_1024F16() \|\| isVISrc_1024B32();	---	720	return isVISrc_1024F16() \|\| isVISrc_1024B32();	---
721	}	---	721	}	---
722		---	722		---
723	bool isAISrcB32() const {	---	723	bool isAISrcB32() const {	---
724	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32);	---	724	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i32);	---
725	}	---	725	}	---
726		---	726		---
727	bool isAISrcB16() const {	---	727	bool isAISrcB16() const {	---
728	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16);	---	728	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::i16);	---
729	}	---	729	}	---
730		---	730		---
731	bool isAISrcV2B16() const {	---	731	bool isAISrcV2B16() const {	---
732	return isAISrcB16();	---	732	return isAISrcB16();	---
733	}	---	733	}	---
734		---	734		---
735	bool isAISrcF32() const {	---	735	bool isAISrcF32() const {	---
736	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);	---	736	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f32);	---
737	}	---	737	}	---
738		---	738		---
739	bool isAISrcF16() const {	---	739	bool isAISrcF16() const {	---
740	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);	---	740	return isRegOrInlineNoMods(AMDGPU::AGPR_32RegClassID, MVT::f16);	---
741	}	---	741	}	---
742		---	742		---
743	bool isAISrcV2F16() const {	---	743	bool isAISrcV2F16() const {	---
744	return isAISrcF16() \|\| isAISrcB32();	---	744	return isAISrcF16() \|\| isAISrcB32();	---
745	}	---	745	}	---
746		---	746		---
747	bool isAISrc_64B64() const {	---	747	bool isAISrc_64B64() const {	---
748	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64);	---	748	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::i64);	---
749	}	---	749	}	---
750		---	750		---
751	bool isAISrc_64F64() const {	0	751	bool isAISrc_64F64() const {	0
752	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64);	0	752	return isRegOrInlineNoMods(AMDGPU::AReg_64RegClassID, MVT::f64);	0
753	}	---	753	}	---
754		---	754		---
755	bool isAISrc_128B32() const {	0	755	bool isAISrc_128B32() const {	0
756	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32);	0	756	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i32);	0
757	}	---	757	}	---
758		---	758		---
759	bool isAISrc_128B16() const {	---	759	bool isAISrc_128B16() const {	---
760	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16);	---	760	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::i16);	---
761	}	---	761	}	---
762		---	762		---
763	bool isAISrc_128V2B16() const {	---	763	bool isAISrc_128V2B16() const {	---
764	return isAISrc_128B16();	---	764	return isAISrc_128B16();	---
765	}	---	765	}	---
766		---	766		---
767	bool isAISrc_128F32() const {	0	767	bool isAISrc_128F32() const {	0
768	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);	0	768	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f32);	0
769	}	---	769	}	---
770		---	770		---
771	bool isAISrc_128F16() const {	---	771	bool isAISrc_128F16() const {	---
772	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);	---	772	return isRegOrInlineNoMods(AMDGPU::AReg_128RegClassID, MVT::f16);	---
773	}	---	773	}	---
774		---	774		---
775	bool isAISrc_128V2F16() const {	---	775	bool isAISrc_128V2F16() const {	---
776	return isAISrc_128F16() \|\| isAISrc_128B32();	---	776	return isAISrc_128F16() \|\| isAISrc_128B32();	---
777	}	---	777	}	---
778		---	778		---
779	bool isVISrc_128F16() const {	---	779	bool isVISrc_128F16() const {	---
780	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16);	---	780	return isRegOrInlineNoMods(AMDGPU::VReg_128RegClassID, MVT::f16);	---
781	}	---	781	}	---
782		---	782		---
783	bool isVISrc_128V2F16() const {	---	783	bool isVISrc_128V2F16() const {	---
784	return isVISrc_128F16() \|\| isVISrc_128B32();	---	784	return isVISrc_128F16() \|\| isVISrc_128B32();	---
785	}	---	785	}	---
786		---	786		---
787	bool isAISrc_256B64() const {	---	787	bool isAISrc_256B64() const {	---
788	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64);	---	788	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::i64);	---
789	}	---	789	}	---
790		---	790		---
791	bool isAISrc_256F64() const {	0	791	bool isAISrc_256F64() const {	0
792	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64);	0	792	return isRegOrInlineNoMods(AMDGPU::AReg_256RegClassID, MVT::f64);	0
793	}	---	793	}	---
794		---	794		---
795	bool isAISrc_512B32() const {	0	795	bool isAISrc_512B32() const {	0
796	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32);	0	796	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i32);	0
797	}	---	797	}	---
798		---	798		---
799	bool isAISrc_512B16() const {	---	799	bool isAISrc_512B16() const {	---
800	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16);	---	800	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::i16);	---
801	}	---	801	}	---
802		---	802		---
803	bool isAISrc_512V2B16() const {	---	803	bool isAISrc_512V2B16() const {	---
804	return isAISrc_512B16();	---	804	return isAISrc_512B16();	---
805	}	---	805	}	---
806		---	806		---
807	bool isAISrc_512F32() const {	0	807	bool isAISrc_512F32() const {	0
808	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);	0	808	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f32);	0
809	}	---	809	}	---
810		---	810		---
811	bool isAISrc_512F16() const {	---	811	bool isAISrc_512F16() const {	---
812	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);	---	812	return isRegOrInlineNoMods(AMDGPU::AReg_512RegClassID, MVT::f16);	---
813	}	---	813	}	---
814		---	814		---
815	bool isAISrc_512V2F16() const {	---	815	bool isAISrc_512V2F16() const {	---
816	return isAISrc_512F16() \|\| isAISrc_512B32();	---	816	return isAISrc_512F16() \|\| isAISrc_512B32();	---
817	}	---	817	}	---
818		---	818		---
819	bool isAISrc_1024B32() const {	0	819	bool isAISrc_1024B32() const {	0
820	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32);	0	820	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i32);	0
821	}	---	821	}	---
822		---	822		---
823	bool isAISrc_1024B16() const {	---	823	bool isAISrc_1024B16() const {	---
824	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16);	---	824	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::i16);	---
825	}	---	825	}	---
826		---	826		---
827	bool isAISrc_1024V2B16() const {	---	827	bool isAISrc_1024V2B16() const {	---
828	return isAISrc_1024B16();	---	828	return isAISrc_1024B16();	---
829	}	---	829	}	---
830		---	830		---
831	bool isAISrc_1024F32() const {	0	831	bool isAISrc_1024F32() const {	0
832	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);	0	832	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f32);	0
833	}	---	833	}	---
834		---	834		---
835	bool isAISrc_1024F16() const {	---	835	bool isAISrc_1024F16() const {	---
836	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);	---	836	return isRegOrInlineNoMods(AMDGPU::AReg_1024RegClassID, MVT::f16);	---
837	}	---	837	}	---
838		---	838		---
839	bool isAISrc_1024V2F16() const {	---	839	bool isAISrc_1024V2F16() const {	---
840	return isAISrc_1024F16() \|\| isAISrc_1024B32();	---	840	return isAISrc_1024F16() \|\| isAISrc_1024B32();	---
841	}	---	841	}	---
842		---	842		---
843	bool isKImmFP32() const {	0	843	bool isKImmFP32() const {	0
844	return isLiteralImm(MVT::f32);	0	844	return isLiteralImm(MVT::f32);	0
845	}	---	845	}	---
846		---	846		---
847	bool isKImmFP16() const {	0	847	bool isKImmFP16() const {	0
848	return isLiteralImm(MVT::f16);	0	848	return isLiteralImm(MVT::f16);	0
849	}	---	849	}	---
850		---	850		---
851	bool isMem() const override {	0	851	bool isMem() const override {	0
852	return false;	0	852	return false;	0
853	}	---	853	}	---
854		---	854		---
855	bool isExpr() const {	0	855	bool isExpr() const {	0
856	return Kind == Expression;	0	856	return Kind == Expression;	0
857	}	---	857	}	---
858		---	858		---
859	bool isSOPPBrTarget() const { return isExpr() \|\| isImm(); }	0	859	bool isSOPPBrTarget() const { return isExpr() \|\| isImm(); }	0
860		---	860		---
861	bool isSWaitCnt() const;	---	861	bool isSWaitCnt() const;	---
862	bool isDepCtr() const;	---	862	bool isDepCtr() const;	---
863	bool isSDelayALU() const;	---	863	bool isSDelayALU() const;	---
864	bool isHwreg() const;	---	864	bool isHwreg() const;	---
865	bool isSendMsg() const;	---	865	bool isSendMsg() const;	---
866	bool isSwizzle() const;	---	866	bool isSwizzle() const;	---
867	bool isSMRDOffset8() const;	---	867	bool isSMRDOffset8() const;	---
868	bool isSMEMOffset() const;	---	868	bool isSMEMOffset() const;	---
869	bool isSMRDLiteralOffset() const;	---	869	bool isSMRDLiteralOffset() const;	---
870	bool isDPP8() const;	---	870	bool isDPP8() const;	---
871	bool isDPPCtrl() const;	---	871	bool isDPPCtrl() const;	---
872	bool isBLGP() const;	---	872	bool isBLGP() const;	---
873	bool isCBSZ() const;	---	873	bool isCBSZ() const;	---
874	bool isABID() const;	---	874	bool isABID() const;	---
875	bool isGPRIdxMode() const;	---	875	bool isGPRIdxMode() const;	---
876	bool isS16Imm() const;	---	876	bool isS16Imm() const;	---
877	bool isU16Imm() const;	---	877	bool isU16Imm() const;	---
878	bool isEndpgm() const;	---	878	bool isEndpgm() const;	---
879	bool isWaitVDST() const;	---	879	bool isWaitVDST() const;	---
880	bool isWaitEXP() const;	---	880	bool isWaitEXP() const;	---
881		---	881		---
882	StringRef getToken() const {	0	882	StringRef getToken() const {	0
883	assert(isToken());	0	883	assert(isToken());	0
884	return StringRef(Tok.Data, Tok.Length);	0	884	return StringRef(Tok.Data, Tok.Length);	0
885	}	---	885	}	---
886		---	886		---
887	int64_t getImm() const {	0	887	int64_t getImm() const {	0
888	assert(isImm());	0	888	assert(isImm());	0
889	return Imm.Val;	0	889	return Imm.Val;	0
890	}	---	890	}	---
891		---	891		---
892	void setImm(int64_t Val) {	0	892	void setImm(int64_t Val) {	0
893	assert(isImm());	0	893	assert(isImm());	0
894	Imm.Val = Val;	0	894	Imm.Val = Val;	0
895	}	0	895	}	0
896		---	896		---
897	ImmTy getImmTy() const {	0	897	ImmTy getImmTy() const {	0
898	assert(isImm());	0	898	assert(isImm());	0
899	return Imm.Type;	0	899	return Imm.Type;	0
900	}	---	900	}	---
901		---	901		---
902	unsigned getReg() const override {	0	902	unsigned getReg() const override {	0
903	assert(isRegKind());	0	903	assert(isRegKind());	0
904	return Reg.RegNo;	0	904	return Reg.RegNo;	0
905	}	---	905	}	---
906		---	906		---
907	SMLoc getStartLoc() const override {	0	907	SMLoc getStartLoc() const override {	0
908	return StartLoc;	0	908	return StartLoc;	0
909	}	---	909	}	---
910		---	910		---
911	SMLoc getEndLoc() const override {	0	911	SMLoc getEndLoc() const override {	0
912	return EndLoc;	0	912	return EndLoc;	0
913	}	---	913	}	---
914		---	914		---
915	SMRange getLocRange() const {	---	915	SMRange getLocRange() const {	---
916	return SMRange(StartLoc, EndLoc);	---	916	return SMRange(StartLoc, EndLoc);	---
917	}	---	917	}	---
918		---	918		---
919	Modifiers getModifiers() const {	0	919	Modifiers getModifiers() const {	0
920	assert(isRegKind() \|\| isImmTy(ImmTyNone));	0	920	assert(isRegKind() \|\| isImmTy(ImmTyNone));	0
921	return isRegKind() ? Reg.Mods : Imm.Mods;	0	921	return isRegKind() ? Reg.Mods : Imm.Mods;	0
922	}	---	922	}	---
923		---	923		---
924	void setModifiers(Modifiers Mods) {	0	924	void setModifiers(Modifiers Mods) {	0
925	assert(isRegKind() \|\| isImmTy(ImmTyNone));	0	925	assert(isRegKind() \|\| isImmTy(ImmTyNone));	0
926	if (isRegKind())	0	926	if (isRegKind())	0
927	Reg.Mods = Mods;	0	927	Reg.Mods = Mods;	0
928	else	---	928	else	---
929	Imm.Mods = Mods;	0	929	Imm.Mods = Mods;	0
930	}	0	930	}	0
931		---	931		---
932	bool hasModifiers() const {	0	932	bool hasModifiers() const {	0
933	return getModifiers().hasModifiers();	0	933	return getModifiers().hasModifiers();	0
934	}	---	934	}	---
935		---	935		---
936	bool hasFPModifiers() const {	0	936	bool hasFPModifiers() const {	0
937	return getModifiers().hasFPModifiers();	0	937	return getModifiers().hasFPModifiers();	0
938	}	---	938	}	---
939		---	939		---
940	bool hasIntModifiers() const {	0	940	bool hasIntModifiers() const {	0
941	return getModifiers().hasIntModifiers();	0	941	return getModifiers().hasIntModifiers();	0
942	}	---	942	}	---
943		---	943		---
944	uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;	---	944	uint64_t applyInputFPModifiers(uint64_t Val, unsigned Size) const;	---
945		---	945		---
946	void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;	---	946	void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const;	---
947		---	947		---
948	void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;	---	948	void addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const;	---
949		---	949		---
950	void addRegOperands(MCInst &Inst, unsigned N) const;	---	950	void addRegOperands(MCInst &Inst, unsigned N) const;	---
951		---	951		---
952	void addRegOrImmOperands(MCInst &Inst, unsigned N) const {	0	952	void addRegOrImmOperands(MCInst &Inst, unsigned N) const {	0
953	if (isRegKind())	0	953	if (isRegKind())	0
954	addRegOperands(Inst, N);	0	954	addRegOperands(Inst, N);	0
955	else	---	955	else	---
956	addImmOperands(Inst, N);	0	956	addImmOperands(Inst, N);	0
957	}	0	957	}	0
958		---	958		---
959	void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {	0	959	void addRegOrImmWithInputModsOperands(MCInst &Inst, unsigned N) const {	0
960	Modifiers Mods = getModifiers();	0	960	Modifiers Mods = getModifiers();	0
961	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	0	961	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	0
962	if (isRegKind()) {	0	962	if (isRegKind()) {	0
963	addRegOperands(Inst, N);	0	963	addRegOperands(Inst, N);	0
964	} else {	---	964	} else {	---
965	addImmOperands(Inst, N, false);	0	965	addImmOperands(Inst, N, false);	0
966	}	---	966	}	---
967	}	0	967	}	0
968		---	968		---
969	void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	0	969	void addRegOrImmWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	0
970	assert(!hasIntModifiers());	0	970	assert(!hasIntModifiers());	0
971	addRegOrImmWithInputModsOperands(Inst, N);	0	971	addRegOrImmWithInputModsOperands(Inst, N);	0
972	}	0	972	}	0
973		---	973		---
974	void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	---	974	void addRegOrImmWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	---
975	assert(!hasFPModifiers());	---	975	assert(!hasFPModifiers());	---
976	addRegOrImmWithInputModsOperands(Inst, N);	---	976	addRegOrImmWithInputModsOperands(Inst, N);	---
977	}	---	977	}	---
978		---	978		---
979	void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {	0	979	void addRegWithInputModsOperands(MCInst &Inst, unsigned N) const {	0
980	Modifiers Mods = getModifiers();	0	980	Modifiers Mods = getModifiers();	0
981	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	0	981	Inst.addOperand(MCOperand::createImm(Mods.getModifiersOperand()));	0
982	assert(isRegKind());	0	982	assert(isRegKind());	0
983	addRegOperands(Inst, N);	0	983	addRegOperands(Inst, N);	0
984	}	0	984	}	0
985		---	985		---
986	void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	0	986	void addRegWithFPInputModsOperands(MCInst &Inst, unsigned N) const {	0
987	assert(!hasIntModifiers());	0	987	assert(!hasIntModifiers());	0
988	addRegWithInputModsOperands(Inst, N);	0	988	addRegWithInputModsOperands(Inst, N);	0
989	}	0	989	}	0
990		---	990		---
991	void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	---	991	void addRegWithIntInputModsOperands(MCInst &Inst, unsigned N) const {	---
992	assert(!hasFPModifiers());	---	992	assert(!hasFPModifiers());	---
993	addRegWithInputModsOperands(Inst, N);	---	993	addRegWithInputModsOperands(Inst, N);	---
994	}	---	994	}	---
995		---	995		---
996	static void printImmTy(raw_ostream& OS, ImmTy Type) {	0	996	static void printImmTy(raw_ostream& OS, ImmTy Type) {	0
997	switch (Type) {	0	997	switch (Type) {	0
998	case ImmTyNone: OS << "None"; break;	0	998	case ImmTyNone: OS << "None"; break;	0
999	case ImmTyGDS: OS << "GDS"; break;	0	999	case ImmTyGDS: OS << "GDS"; break;	0
1000	case ImmTyLDS: OS << "LDS"; break;	0	1000	case ImmTyLDS: OS << "LDS"; break;	0
1001	case ImmTyOffen: OS << "Offen"; break;	0	1001	case ImmTyOffen: OS << "Offen"; break;	0
1002	case ImmTyIdxen: OS << "Idxen"; break;	0	1002	case ImmTyIdxen: OS << "Idxen"; break;	0
1003	case ImmTyAddr64: OS << "Addr64"; break;	0	1003	case ImmTyAddr64: OS << "Addr64"; break;	0
1004	case ImmTyOffset: OS << "Offset"; break;	0	1004	case ImmTyOffset: OS << "Offset"; break;	0
1005	case ImmTyInstOffset: OS << "InstOffset"; break;	0	1005	case ImmTyInstOffset: OS << "InstOffset"; break;	0
1006	case ImmTyOffset0: OS << "Offset0"; break;	0	1006	case ImmTyOffset0: OS << "Offset0"; break;	0
1007	case ImmTyOffset1: OS << "Offset1"; break;	0	1007	case ImmTyOffset1: OS << "Offset1"; break;	0
1008	case ImmTySMEMOffsetMod: OS << "SMEMOffsetMod"; break;	0	1008	case ImmTySMEMOffsetMod: OS << "SMEMOffsetMod"; break;	0
1009	case ImmTyCPol: OS << "CPol"; break;	0	1009	case ImmTyCPol: OS << "CPol"; break;	0
1010	case ImmTyTFE: OS << "TFE"; break;	0	1010	case ImmTyTFE: OS << "TFE"; break;	0
1011	case ImmTyD16: OS << "D16"; break;	0	1011	case ImmTyD16: OS << "D16"; break;	0
1012	case ImmTyFORMAT: OS << "FORMAT"; break;	0	1012	case ImmTyFORMAT: OS << "FORMAT"; break;	0
1013	case ImmTyClampSI: OS << "ClampSI"; break;	0	1013	case ImmTyClampSI: OS << "ClampSI"; break;	0
1014	case ImmTyOModSI: OS << "OModSI"; break;	0	1014	case ImmTyOModSI: OS << "OModSI"; break;	0
1015	case ImmTyDPP8: OS << "DPP8"; break;	0	1015	case ImmTyDPP8: OS << "DPP8"; break;	0
1016	case ImmTyDppCtrl: OS << "DppCtrl"; break;	0	1016	case ImmTyDppCtrl: OS << "DppCtrl"; break;	0
1017	case ImmTyDppRowMask: OS << "DppRowMask"; break;	0	1017	case ImmTyDppRowMask: OS << "DppRowMask"; break;	0
1018	case ImmTyDppBankMask: OS << "DppBankMask"; break;	0	1018	case ImmTyDppBankMask: OS << "DppBankMask"; break;	0
1019	case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;	0	1019	case ImmTyDppBoundCtrl: OS << "DppBoundCtrl"; break;	0
1020	case ImmTyDppFI: OS << "DppFI"; break;	0	1020	case ImmTyDppFI: OS << "DppFI"; break;	0
1021	case ImmTySDWADstSel: OS << "SDWADstSel"; break;	0	1021	case ImmTySDWADstSel: OS << "SDWADstSel"; break;	0
1022	case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break;	0	1022	case ImmTySDWASrc0Sel: OS << "SDWASrc0Sel"; break;	0
1023	case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break;	0	1023	case ImmTySDWASrc1Sel: OS << "SDWASrc1Sel"; break;	0
1024	case ImmTySDWADstUnused: OS << "SDWADstUnused"; break;	0	1024	case ImmTySDWADstUnused: OS << "SDWADstUnused"; break;	0
1025	case ImmTyDMask: OS << "DMask"; break;	0	1025	case ImmTyDMask: OS << "DMask"; break;	0
1026	case ImmTyDim: OS << "Dim"; break;	0	1026	case ImmTyDim: OS << "Dim"; break;	0
1027	case ImmTyUNorm: OS << "UNorm"; break;	0	1027	case ImmTyUNorm: OS << "UNorm"; break;	0
1028	case ImmTyDA: OS << "DA"; break;	0	1028	case ImmTyDA: OS << "DA"; break;	0
1029	case ImmTyR128A16: OS << "R128A16"; break;	0	1029	case ImmTyR128A16: OS << "R128A16"; break;	0
1030	case ImmTyA16: OS << "A16"; break;	0	1030	case ImmTyA16: OS << "A16"; break;	0
1031	case ImmTyLWE: OS << "LWE"; break;	0	1031	case ImmTyLWE: OS << "LWE"; break;	0
1032	case ImmTyOff: OS << "Off"; break;	0	1032	case ImmTyOff: OS << "Off"; break;	0
1033	case ImmTyExpTgt: OS << "ExpTgt"; break;	0	1033	case ImmTyExpTgt: OS << "ExpTgt"; break;	0
1034	case ImmTyExpCompr: OS << "ExpCompr"; break;	0	1034	case ImmTyExpCompr: OS << "ExpCompr"; break;	0
1035	case ImmTyExpVM: OS << "ExpVM"; break;	0	1035	case ImmTyExpVM: OS << "ExpVM"; break;	0
1036	case ImmTyHwreg: OS << "Hwreg"; break;	0	1036	case ImmTyHwreg: OS << "Hwreg"; break;	0
1037	case ImmTySendMsg: OS << "SendMsg"; break;	0	1037	case ImmTySendMsg: OS << "SendMsg"; break;	0
1038	case ImmTyInterpSlot: OS << "InterpSlot"; break;	0	1038	case ImmTyInterpSlot: OS << "InterpSlot"; break;	0
1039	case ImmTyInterpAttr: OS << "InterpAttr"; break;	0	1039	case ImmTyInterpAttr: OS << "InterpAttr"; break;	0
1040	case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;	0	1040	case ImmTyInterpAttrChan: OS << "InterpAttrChan"; break;	0
1041	case ImmTyOpSel: OS << "OpSel"; break;	0	1041	case ImmTyOpSel: OS << "OpSel"; break;	0
1042	case ImmTyOpSelHi: OS << "OpSelHi"; break;	0	1042	case ImmTyOpSelHi: OS << "OpSelHi"; break;	0
1043	case ImmTyNegLo: OS << "NegLo"; break;	0	1043	case ImmTyNegLo: OS << "NegLo"; break;	0
1044	case ImmTyNegHi: OS << "NegHi"; break;	0	1044	case ImmTyNegHi: OS << "NegHi"; break;	0
1045	case ImmTySwizzle: OS << "Swizzle"; break;	0	1045	case ImmTySwizzle: OS << "Swizzle"; break;	0
1046	case ImmTyGprIdxMode: OS << "GprIdxMode"; break;	0	1046	case ImmTyGprIdxMode: OS << "GprIdxMode"; break;	0
1047	case ImmTyHigh: OS << "High"; break;	0	1047	case ImmTyHigh: OS << "High"; break;	0
1048	case ImmTyBLGP: OS << "BLGP"; break;	0	1048	case ImmTyBLGP: OS << "BLGP"; break;	0
1049	case ImmTyCBSZ: OS << "CBSZ"; break;	0	1049	case ImmTyCBSZ: OS << "CBSZ"; break;	0
1050	case ImmTyABID: OS << "ABID"; break;	0	1050	case ImmTyABID: OS << "ABID"; break;	0
1051	case ImmTyEndpgm: OS << "Endpgm"; break;	0	1051	case ImmTyEndpgm: OS << "Endpgm"; break;	0
1052	case ImmTyWaitVDST: OS << "WaitVDST"; break;	0	1052	case ImmTyWaitVDST: OS << "WaitVDST"; break;	0
1053	case ImmTyWaitEXP: OS << "WaitEXP"; break;	0	1053	case ImmTyWaitEXP: OS << "WaitEXP"; break;	0
1054	}	---	1054	}	---
1055	}	0	1055	}	0
1056		---	1056		---
1057	void print(raw_ostream &OS) const override {	0	1057	void print(raw_ostream &OS) const override {	0
1058	switch (Kind) {	0	1058	switch (Kind) {	0
1059	case Register:	0	1059	case Register:	0
1060	OS << "';	0	1060	OS << "';	0
1061	break;	0	1061	break;	0
1062	case Immediate:	0	1062	case Immediate:	0
1063	OS << '<' << getImm();	0	1063	OS << '<' << getImm();	0
1064	if (getImmTy() != ImmTyNone) {	0	1064	if (getImmTy() != ImmTyNone) {	0
1065	OS << " type: "; printImmTy(OS, getImmTy());	0	1065	OS << " type: "; printImmTy(OS, getImmTy());	0
1066	}	---	1066	}	---
1067	OS << " mods: " << Imm.Mods << '>';	0	1067	OS << " mods: " << Imm.Mods << '>';	0
1068	break;	0	1068	break;	0
1069	case Token:	0	1069	case Token:	0
1070	OS << '\'' << getToken() << '\'';	0	1070	OS << '\'' << getToken() << '\'';	0
1071	break;	0	1071	break;	0
1072	case Expression:	0	1072	case Expression:	0
1073	OS << "';	0	1073	OS << "';	0
1074	break;	0	1074	break;	0
1075	}	---	1075	}	---
1076	}	0	1076	}	0
1077		---	1077		---
1078	static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,	0	1078	static AMDGPUOperand::Ptr CreateImm(const AMDGPUAsmParser *AsmParser,	0
1079	int64_t Val, SMLoc Loc,	---	1079	int64_t Val, SMLoc Loc,	---
1080	ImmTy Type = ImmTyNone,	---	1080	ImmTy Type = ImmTyNone,	---
1081	bool IsFPImm = false) {	---	1081	bool IsFPImm = false) {	---
1082	auto Op = std::make_unique(Immediate, AsmParser);	0	1082	auto Op = std::make_unique(Immediate, AsmParser);	0
1083	Op->Imm.Val = Val;	0	1083	Op->Imm.Val = Val;	0
1084	Op->Imm.IsFPImm = IsFPImm;	0	1084	Op->Imm.IsFPImm = IsFPImm;	0
1085	Op->Imm.Kind = ImmKindTyNone;	0	1085	Op->Imm.Kind = ImmKindTyNone;	0
1086	Op->Imm.Type = Type;	0	1086	Op->Imm.Type = Type;	0
1087	Op->Imm.Mods = Modifiers();	0	1087	Op->Imm.Mods = Modifiers();	0
1088	Op->StartLoc = Loc;	0	1088	Op->StartLoc = Loc;	0
1089	Op->EndLoc = Loc;	0	1089	Op->EndLoc = Loc;	0
1090	return Op;	0	1090	return Op;	0
1091	}	---	1091	}	---
1092		---	1092		---
1093	static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,	0	1093	static AMDGPUOperand::Ptr CreateToken(const AMDGPUAsmParser *AsmParser,	0
1094	StringRef Str, SMLoc Loc,	---	1094	StringRef Str, SMLoc Loc,	---
1095	bool HasExplicitEncodingSize = true) {	---	1095	bool HasExplicitEncodingSize = true) {	---
1096	auto Res = std::make_unique(Token, AsmParser);	0	1096	auto Res = std::make_unique(Token, AsmParser);	0
1097	Res->Tok.Data = Str.data();	0	1097	Res->Tok.Data = Str.data();	0
1098	Res->Tok.Length = Str.size();	0	1098	Res->Tok.Length = Str.size();	0
1099	Res->StartLoc = Loc;	0	1099	Res->StartLoc = Loc;	0
1100	Res->EndLoc = Loc;	0	1100	Res->EndLoc = Loc;	0
1101	return Res;	0	1101	return Res;	0
1102	}	---	1102	}	---
1103		---	1103		---
1104	static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,	0	1104	static AMDGPUOperand::Ptr CreateReg(const AMDGPUAsmParser *AsmParser,	0
1105	unsigned RegNo, SMLoc S,	---	1105	unsigned RegNo, SMLoc S,	---
1106	SMLoc E) {	---	1106	SMLoc E) {	---
1107	auto Op = std::make_unique(Register, AsmParser);	0	1107	auto Op = std::make_unique(Register, AsmParser);	0
1108	Op->Reg.RegNo = RegNo;	0	1108	Op->Reg.RegNo = RegNo;	0
1109	Op->Reg.Mods = Modifiers();	0	1109	Op->Reg.Mods = Modifiers();	0
1110	Op->StartLoc = S;	0	1110	Op->StartLoc = S;	0
1111	Op->EndLoc = E;	0	1111	Op->EndLoc = E;	0
1112	return Op;	0	1112	return Op;	0
1113	}	---	1113	}	---
1114		---	1114		---
1115	static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,	0	1115	static AMDGPUOperand::Ptr CreateExpr(const AMDGPUAsmParser *AsmParser,	0
1116	const class MCExpr *Expr, SMLoc S) {	---	1116	const class MCExpr *Expr, SMLoc S) {	---
1117	auto Op = std::make_unique(Expression, AsmParser);	0	1117	auto Op = std::make_unique(Expression, AsmParser);	0
1118	Op->Expr = Expr;	0	1118	Op->Expr = Expr;	0
1119	Op->StartLoc = S;	0	1119	Op->StartLoc = S;	0
1120	Op->EndLoc = S;	0	1120	Op->EndLoc = S;	0
1121	return Op;	0	1121	return Op;	0
1122	}	---	1122	}	---
1123	};	---	1123	};	---
1124		---	1124		---
1125	raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) {	0	1125	raw_ostream &operator <<(raw_ostream &OS, AMDGPUOperand::Modifiers Mods) {	0
1126	OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;	0	1126	OS << "abs:" << Mods.Abs << " neg: " << Mods.Neg << " sext:" << Mods.Sext;	0
1127	return OS;	0	1127	return OS;	0
1128	}	---	1128	}	---
1129		---	1129		---
1130	//===----------------------------------------------------------------------===//	---	1130	//===----------------------------------------------------------------------===//	---
1131	// AsmParser	---	1131	// AsmParser	---
1132	//===----------------------------------------------------------------------===//	---	1132	//===----------------------------------------------------------------------===//	---
1133		---	1133		---
1134	// Holds info related to the current kernel, e.g. count of SGPRs used.	---	1134	// Holds info related to the current kernel, e.g. count of SGPRs used.	---
1135	// Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next	---	1135	// Kernel scope begins at .amdgpu_hsa_kernel directive, ends at next	---
1136	// .amdgpu_hsa_kernel or at EOF.	---	1136	// .amdgpu_hsa_kernel or at EOF.	---
1137	class KernelScopeInfo {	---	1137	class KernelScopeInfo {	---
1138	int SgprIndexUnusedMin = -1;	---	1138	int SgprIndexUnusedMin = -1;	---
1139	int VgprIndexUnusedMin = -1;	---	1139	int VgprIndexUnusedMin = -1;	---
1140	int AgprIndexUnusedMin = -1;	---	1140	int AgprIndexUnusedMin = -1;	---
1141	MCContext *Ctx = nullptr;	---	1141	MCContext *Ctx = nullptr;	---
1142	MCSubtargetInfo const *MSTI = nullptr;	---	1142	MCSubtargetInfo const *MSTI = nullptr;	---
1143		---	1143		---
1144	void usesSgprAt(int i) {	0	1144	void usesSgprAt(int i) {	0
1145	if (i >= SgprIndexUnusedMin) {	0	1145	if (i >= SgprIndexUnusedMin) {	0
1146	SgprIndexUnusedMin = ++i;	0	1146	SgprIndexUnusedMin = ++i;	0
1147	if (Ctx) {	0	1147	if (Ctx) {	0
1148	MCSymbol* const Sym =	---	1148	MCSymbol* const Sym =	---
1149	Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));	0	1149	Ctx->getOrCreateSymbol(Twine(".kernel.sgpr_count"));	0
1150	Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));	0	1150	Sym->setVariableValue(MCConstantExpr::create(SgprIndexUnusedMin, *Ctx));	0
1151	}	---	1151	}	---
1152	}	---	1152	}	---
1153	}	0	1153	}	0
1154		---	1154		---
1155	void usesVgprAt(int i) {	0	1155	void usesVgprAt(int i) {	0
1156	if (i >= VgprIndexUnusedMin) {	0	1156	if (i >= VgprIndexUnusedMin) {	0
1157	VgprIndexUnusedMin = ++i;	0	1157	VgprIndexUnusedMin = ++i;	0
1158	if (Ctx) {	0	1158	if (Ctx) {	0
1159	MCSymbol* const Sym =	---	1159	MCSymbol* const Sym =	---
1160	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	0	1160	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	0
1161	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	0	1161	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	0
1162	VgprIndexUnusedMin);	---	1162	VgprIndexUnusedMin);	---
1163	Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	0	1163	Sym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	0
1164	}	---	1164	}	---
1165	}	---	1165	}	---
1166	}	0	1166	}	0
1167		---	1167		---
1168	void usesAgprAt(int i) {	0	1168	void usesAgprAt(int i) {	0
1169	// Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction	---	1169	// Instruction will error in AMDGPUAsmParser::MatchAndEmitInstruction	---
1170	if (!hasMAIInsts(*MSTI))	0	1170	if (!hasMAIInsts(*MSTI))	0
1171	return;	0	1171	return;	0
1172		---	1172		---
1173	if (i >= AgprIndexUnusedMin) {	0	1173	if (i >= AgprIndexUnusedMin) {	0
1174	AgprIndexUnusedMin = ++i;	0	1174	AgprIndexUnusedMin = ++i;	0
1175	if (Ctx) {	0	1175	if (Ctx) {	0
1176	MCSymbol* const Sym =	---	1176	MCSymbol* const Sym =	---
1177	Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count"));	0	1177	Ctx->getOrCreateSymbol(Twine(".kernel.agpr_count"));	0
1178	Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx));	0	1178	Sym->setVariableValue(MCConstantExpr::create(AgprIndexUnusedMin, *Ctx));	0
1179		---	1179		---
1180	// Also update vgpr_count (dependent on agpr_count for gfx908/gfx90a)	---	1180	// Also update vgpr_count (dependent on agpr_count for gfx908/gfx90a)	---
1181	MCSymbol* const vSym =	---	1181	MCSymbol* const vSym =	---
1182	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	0	1182	Ctx->getOrCreateSymbol(Twine(".kernel.vgpr_count"));	0
1183	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	0	1183	int totalVGPR = getTotalNumVGPRs(isGFX90A(*MSTI), AgprIndexUnusedMin,	0
1184	VgprIndexUnusedMin);	---	1184	VgprIndexUnusedMin);	---
1185	vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	0	1185	vSym->setVariableValue(MCConstantExpr::create(totalVGPR, *Ctx));	0
1186	}	---	1186	}	---
1187	}	---	1187	}	---
1188	}	---	1188	}	---
1189		---	1189		---
1190	public:	---	1190	public:	---
1191	KernelScopeInfo() = default;	0	1191	KernelScopeInfo() = default;	0
1192		---	1192		---
1193	void initialize(MCContext &Context) {	0	1193	void initialize(MCContext &Context) {	0
1194	Ctx = &Context;	0	1194	Ctx = &Context;	0
1195	MSTI = Ctx->getSubtargetInfo();	0	1195	MSTI = Ctx->getSubtargetInfo();	0
1196		---	1196		---
1197	usesSgprAt(SgprIndexUnusedMin = -1);	0	1197	usesSgprAt(SgprIndexUnusedMin = -1);	0
1198	usesVgprAt(VgprIndexUnusedMin = -1);	0	1198	usesVgprAt(VgprIndexUnusedMin = -1);	0
1199	if (hasMAIInsts(*MSTI)) {	0	1199	if (hasMAIInsts(*MSTI)) {	0
1200	usesAgprAt(AgprIndexUnusedMin = -1);	0	1200	usesAgprAt(AgprIndexUnusedMin = -1);	0
1201	}	---	1201	}	---
1202	}	0	1202	}	0
1203		---	1203		---
1204	void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex,	0	1204	void usesRegister(RegisterKind RegKind, unsigned DwordRegIndex,	0
1205	unsigned RegWidth) {	---	1205	unsigned RegWidth) {	---
1206	switch (RegKind) {	0	1206	switch (RegKind) {	0
1207	case IS_SGPR:	0	1207	case IS_SGPR:	0
1208	usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0	1208	usesSgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0
1209	break;	0	1209	break;	0
1210	case IS_AGPR:	0	1210	case IS_AGPR:	0
1211	usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0	1211	usesAgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0
1212	break;	0	1212	break;	0
1213	case IS_VGPR:	0	1213	case IS_VGPR:	0
1214	usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0	1214	usesVgprAt(DwordRegIndex + divideCeil(RegWidth, 32) - 1);	0
1215	break;	0	1215	break;	0
1216	default:	0	1216	default:	0
1217	break;	0	1217	break;	0
1218	}	---	1218	}	---
1219	}	0	1219	}	0
1220	};	---	1220	};	---
1221		---	1221		---
1222	class AMDGPUAsmParser : public MCTargetAsmParser {	---	1222	class AMDGPUAsmParser : public MCTargetAsmParser {	---
1223	MCAsmParser &Parser;	---	1223	MCAsmParser &Parser;	---
1224		---	1224		---
1225	unsigned ForcedEncodingSize = 0;	---	1225	unsigned ForcedEncodingSize = 0;	---
1226	bool ForcedDPP = false;	---	1226	bool ForcedDPP = false;	---
1227	bool ForcedSDWA = false;	---	1227	bool ForcedSDWA = false;	---
1228	KernelScopeInfo KernelScope;	---	1228	KernelScopeInfo KernelScope;	---
1229		---	1229		---
1230	/// @name Auto-generated Match Functions	---	1230	/// @name Auto-generated Match Functions	---
1231	/// {	---	1231	/// {	---
1232		---	1232		---
1233	#define GET_ASSEMBLER_HEADER	---	1233	#define GET_ASSEMBLER_HEADER	---
1234	#include "AMDGPUGenAsmMatcher.inc"	---	1234	#include "AMDGPUGenAsmMatcher.inc"	---
1235		---	1235		---
1236	/// }	---	1236	/// }	---
1237		---	1237		---
1238	private:	---	1238	private:	---
1239	bool ParseAsAbsoluteExpression(uint32_t &Ret);	---	1239	bool ParseAsAbsoluteExpression(uint32_t &Ret);	---
1240	bool OutOfRangeError(SMRange Range);	---	1240	bool OutOfRangeError(SMRange Range);	---
1241	/// Calculate VGPR/SGPR blocks required for given target, reserved	---	1241	/// Calculate VGPR/SGPR blocks required for given target, reserved	---
1242	/// registers, and user-specified NextFreeXGPR values.	---	1242	/// registers, and user-specified NextFreeXGPR values.	---
1243	///	---	1243	///	---
1244	/// \param Features [in] Target features, used for bug corrections.	---	1244	/// \param Features [in] Target features, used for bug corrections.	---
1245	/// \param VCCUsed [in] Whether VCC special SGPR is reserved.	---	1245	/// \param VCCUsed [in] Whether VCC special SGPR is reserved.	---
1246	/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.	---	1246	/// \param FlatScrUsed [in] Whether FLAT_SCRATCH special SGPR is reserved.	---
1247	/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.	---	1247	/// \param XNACKUsed [in] Whether XNACK_MASK special SGPR is reserved.	---
1248	/// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel	---	1248	/// \param EnableWavefrontSize32 [in] Value of ENABLE_WAVEFRONT_SIZE32 kernel	---
1249	/// descriptor field, if valid.	---	1249	/// descriptor field, if valid.	---
1250	/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.	---	1250	/// \param NextFreeVGPR [in] Max VGPR number referenced, plus one.	---
1251	/// \param VGPRRange [in] Token range, used for VGPR diagnostics.	---	1251	/// \param VGPRRange [in] Token range, used for VGPR diagnostics.	---
1252	/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.	---	1252	/// \param NextFreeSGPR [in] Max SGPR number referenced, plus one.	---
1253	/// \param SGPRRange [in] Token range, used for SGPR diagnostics.	---	1253	/// \param SGPRRange [in] Token range, used for SGPR diagnostics.	---
1254	/// \param VGPRBlocks [out] Result VGPR block count.	---	1254	/// \param VGPRBlocks [out] Result VGPR block count.	---
1255	/// \param SGPRBlocks [out] Result SGPR block count.	---	1255	/// \param SGPRBlocks [out] Result SGPR block count.	---
1256	bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,	---	1256	bool calculateGPRBlocks(const FeatureBitset &Features, bool VCCUsed,	---
1257	bool FlatScrUsed, bool XNACKUsed,	---	1257	bool FlatScrUsed, bool XNACKUsed,	---
1258	std::optional EnableWavefrontSize32,	---	1258	std::optional EnableWavefrontSize32,	---
1259	unsigned NextFreeVGPR, SMRange VGPRRange,	---	1259	unsigned NextFreeVGPR, SMRange VGPRRange,	---
1260	unsigned NextFreeSGPR, SMRange SGPRRange,	---	1260	unsigned NextFreeSGPR, SMRange SGPRRange,	---
1261	unsigned &VGPRBlocks, unsigned &SGPRBlocks);	---	1261	unsigned &VGPRBlocks, unsigned &SGPRBlocks);	---
1262	bool ParseDirectiveAMDGCNTarget();	---	1262	bool ParseDirectiveAMDGCNTarget();	---
1263	bool ParseDirectiveAMDHSAKernel();	---	1263	bool ParseDirectiveAMDHSAKernel();	---
1264	bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);	---	1264	bool ParseDirectiveMajorMinor(uint32_t &Major, uint32_t &Minor);	---
1265	bool ParseDirectiveHSACodeObjectVersion();	---	1265	bool ParseDirectiveHSACodeObjectVersion();	---
1266	bool ParseDirectiveHSACodeObjectISA();	---	1266	bool ParseDirectiveHSACodeObjectISA();	---
1267	bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);	---	1267	bool ParseAMDKernelCodeTValue(StringRef ID, amd_kernel_code_t &Header);	---
1268	bool ParseDirectiveAMDKernelCodeT();	---	1268	bool ParseDirectiveAMDKernelCodeT();	---
1269	// TODO: Possibly make subtargetHasRegister const.	---	1269	// TODO: Possibly make subtargetHasRegister const.	---
1270	bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);	---	1270	bool subtargetHasRegister(const MCRegisterInfo &MRI, unsigned RegNo);	---
1271	bool ParseDirectiveAMDGPUHsaKernel();	---	1271	bool ParseDirectiveAMDGPUHsaKernel();	---
1272		---	1272		---
1273	bool ParseDirectiveISAVersion();	---	1273	bool ParseDirectiveISAVersion();	---
1274	bool ParseDirectiveHSAMetadata();	---	1274	bool ParseDirectiveHSAMetadata();	---
1275	bool ParseDirectivePALMetadataBegin();	---	1275	bool ParseDirectivePALMetadataBegin();	---
1276	bool ParseDirectivePALMetadata();	---	1276	bool ParseDirectivePALMetadata();	---
1277	bool ParseDirectiveAMDGPULDS();	---	1277	bool ParseDirectiveAMDGPULDS();	---
1278		---	1278		---
1279	/// Common code to parse out a block of text (typically YAML) between start and	---	1279	/// Common code to parse out a block of text (typically YAML) between start and	---
1280	/// end directives.	---	1280	/// end directives.	---
1281	bool ParseToEndDirective(const char *AssemblerDirectiveBegin,	---	1281	bool ParseToEndDirective(const char *AssemblerDirectiveBegin,	---
1282	const char *AssemblerDirectiveEnd,	---	1282	const char *AssemblerDirectiveEnd,	---
1283	std::string &CollectString);	---	1283	std::string &CollectString);	---
1284		---	1284		---
1285	bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,	---	1285	bool AddNextRegisterToList(unsigned& Reg, unsigned& RegWidth,	---
1286	RegisterKind RegKind, unsigned Reg1, SMLoc Loc);	---	1286	RegisterKind RegKind, unsigned Reg1, SMLoc Loc);	---
1287	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	---	1287	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	---
1288	unsigned &RegNum, unsigned &RegWidth,	---	1288	unsigned &RegNum, unsigned &RegWidth,	---
1289	bool RestoreOnFailure = false);	---	1289	bool RestoreOnFailure = false);	---
1290	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	---	1290	bool ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	---
1291	unsigned &RegNum, unsigned &RegWidth,	---	1291	unsigned &RegNum, unsigned &RegWidth,	---
1292	SmallVectorImpl &Tokens);	---	1292	SmallVectorImpl &Tokens);	---
1293	unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,	---	1293	unsigned ParseRegularReg(RegisterKind &RegKind, unsigned &RegNum,	---
1294	unsigned &RegWidth,	---	1294	unsigned &RegWidth,	---
1295	SmallVectorImpl &Tokens);	---	1295	SmallVectorImpl &Tokens);	---
1296	unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,	---	1296	unsigned ParseSpecialReg(RegisterKind &RegKind, unsigned &RegNum,	---
1297	unsigned &RegWidth,	---	1297	unsigned &RegWidth,	---
1298	SmallVectorImpl &Tokens);	---	1298	SmallVectorImpl &Tokens);	---
1299	unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	---	1299	unsigned ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	---
1300	unsigned &RegWidth, SmallVectorImpl &Tokens);	---	1300	unsigned &RegWidth, SmallVectorImpl &Tokens);	---
1301	bool ParseRegRange(unsigned& Num, unsigned& Width);	---	1301	bool ParseRegRange(unsigned& Num, unsigned& Width);	---
1302	unsigned getRegularReg(RegisterKind RegKind,	---	1302	unsigned getRegularReg(RegisterKind RegKind,	---
1303	unsigned RegNum,	---	1303	unsigned RegNum,	---
1304	unsigned RegWidth,	---	1304	unsigned RegWidth,	---
1305	SMLoc Loc);	---	1305	SMLoc Loc);	---
1306		---	1306		---
1307	bool isRegister();	---	1307	bool isRegister();	---
1308	bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;	---	1308	bool isRegister(const AsmToken &Token, const AsmToken &NextToken) const;	---
1309	std::optional getGprCountSymbolName(RegisterKind RegKind);	---	1309	std::optional getGprCountSymbolName(RegisterKind RegKind);	---
1310	void initializeGprCountSymbol(RegisterKind RegKind);	---	1310	void initializeGprCountSymbol(RegisterKind RegKind);	---
1311	bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,	---	1311	bool updateGprCountSymbols(RegisterKind RegKind, unsigned DwordRegIndex,	---
1312	unsigned RegWidth);	---	1312	unsigned RegWidth);	---
1313	void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,	---	1313	void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,	---
1314	bool IsAtomic);	---	1314	bool IsAtomic);	---
1315		---	1315		---
1316	public:	---	1316	public:	---
1317	enum AMDGPUMatchResultTy {	---	1317	enum AMDGPUMatchResultTy {	---
1318	Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY	---	1318	Match_PreferE32 = FIRST_TARGET_MATCH_RESULT_TY	---
1319	};	---	1319	};	---
1320	enum OperandMode {	---	1320	enum OperandMode {	---
1321	OperandMode_Default,	---	1321	OperandMode_Default,	---
1322	OperandMode_NSA,	---	1322	OperandMode_NSA,	---
1323	};	---	1323	};	---
1324		---	1324		---
1325	using OptionalImmIndexMap = std::map;	---	1325	using OptionalImmIndexMap = std::map;	---
1326		---	1326		---
1327	AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,	0	1327	AMDGPUAsmParser(const MCSubtargetInfo &STI, MCAsmParser &_Parser,	0
1328	const MCInstrInfo &MII,	---	1328	const MCInstrInfo &MII,	---
1329	const MCTargetOptions &Options)	---	1329	const MCTargetOptions &Options)	---
1330	: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {	0	1330	: MCTargetAsmParser(Options, STI, MII), Parser(_Parser) {	0
1331	MCAsmParserExtension::Initialize(Parser);	0	1331	MCAsmParserExtension::Initialize(Parser);	0
1332		---	1332		---
1333	if (getFeatureBits().none()) {	0	1333	if (getFeatureBits().none()) {	0
1334	// Set default features.	---	1334	// Set default features.	---
1335	copySTI().ToggleFeature("southern-islands");	0	1335	copySTI().ToggleFeature("southern-islands");	0
1336	}	---	1336	}	---
1337		---	1337		---
1338	setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));	0	1338	setAvailableFeatures(ComputeAvailableFeatures(getFeatureBits()));	0
1339		---	1339		---
1340	{	---	1340	{	---
1341	// TODO: make those pre-defined variables read-only.	---	1341	// TODO: make those pre-defined variables read-only.	---
1342	// Currently there is none suitable machinery in the core llvm-mc for this.	---	1342	// Currently there is none suitable machinery in the core llvm-mc for this.	---
1343	// MCSymbol::isRedefinable is intended for another purpose, and	---	1343	// MCSymbol::isRedefinable is intended for another purpose, and	---
1344	// AsmParser::parseDirectiveSet() cannot be specialized for specific target.	---	1344	// AsmParser::parseDirectiveSet() cannot be specialized for specific target.	---
1345	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0	1345	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
1346	MCContext &Ctx = getContext();	0	1346	MCContext &Ctx = getContext();	0
1347	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	0	1347	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	0
1348	MCSymbol *Sym =	---	1348	MCSymbol *Sym =	---
1349	Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));	0	1349	Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_number"));	0
1350	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	0	1350	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	0
1351	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));	0	1351	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_minor"));	0
1352	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	0	1352	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	0
1353	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));	0	1353	Sym = Ctx.getOrCreateSymbol(Twine(".amdgcn.gfx_generation_stepping"));	0
1354	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	0	1354	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	0
1355	} else {	---	1355	} else {	---
1356	MCSymbol *Sym =	---	1356	MCSymbol *Sym =	---
1357	Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));	0	1357	Ctx.getOrCreateSymbol(Twine(".option.machine_version_major"));	0
1358	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	0	1358	Sym->setVariableValue(MCConstantExpr::create(ISA.Major, Ctx));	0
1359	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));	0	1359	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_minor"));	0
1360	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	0	1360	Sym->setVariableValue(MCConstantExpr::create(ISA.Minor, Ctx));	0
1361	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));	0	1361	Sym = Ctx.getOrCreateSymbol(Twine(".option.machine_version_stepping"));	0
1362	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	0	1362	Sym->setVariableValue(MCConstantExpr::create(ISA.Stepping, Ctx));	0
1363	}	---	1363	}	---
1364	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	0	1364	if (ISA.Major >= 6 && isHsaAbiVersion3AndAbove(&getSTI())) {	0
1365	initializeGprCountSymbol(IS_VGPR);	0	1365	initializeGprCountSymbol(IS_VGPR);	0
1366	initializeGprCountSymbol(IS_SGPR);	0	1366	initializeGprCountSymbol(IS_SGPR);	0
1367	} else	---	1367	} else	---
1368	KernelScope.initialize(getContext());	0	1368	KernelScope.initialize(getContext());	0
1369	}	---	1369	}	---
1370	}	0	1370	}	0
1371		---	1371		---
1372	bool hasMIMG_R128() const {	0	1372	bool hasMIMG_R128() const {	0
1373	return AMDGPU::hasMIMG_R128(getSTI());	0	1373	return AMDGPU::hasMIMG_R128(getSTI());	0
1374	}	---	1374	}	---
1375		---	1375		---
1376	bool hasPackedD16() const {	0	1376	bool hasPackedD16() const {	0
1377	return AMDGPU::hasPackedD16(getSTI());	0	1377	return AMDGPU::hasPackedD16(getSTI());	0
1378	}	---	1378	}	---
1379		---	1379		---
1380	bool hasA16() const { return AMDGPU::hasA16(getSTI()); }	0	1380	bool hasA16() const { return AMDGPU::hasA16(getSTI()); }	0
1381		---	1381		---
1382	bool hasG16() const { return AMDGPU::hasG16(getSTI()); }	0	1382	bool hasG16() const { return AMDGPU::hasG16(getSTI()); }	0
1383		---	1383		---
1384	bool isSI() const {	0	1384	bool isSI() const {	0
1385	return AMDGPU::isSI(getSTI());	0	1385	return AMDGPU::isSI(getSTI());	0
1386	}	---	1386	}	---
1387		---	1387		---
1388	bool isCI() const {	0	1388	bool isCI() const {	0
1389	return AMDGPU::isCI(getSTI());	0	1389	return AMDGPU::isCI(getSTI());	0
1390	}	---	1390	}	---
1391		---	1391		---
1392	bool isVI() const {	0	1392	bool isVI() const {	0
1393	return AMDGPU::isVI(getSTI());	0	1393	return AMDGPU::isVI(getSTI());	0
1394	}	---	1394	}	---
1395		---	1395		---
1396	bool isGFX9() const {	0	1396	bool isGFX9() const {	0
1397	return AMDGPU::isGFX9(getSTI());	0	1397	return AMDGPU::isGFX9(getSTI());	0
1398	}	---	1398	}	---
1399		---	1399		---
1400	// TODO: isGFX90A is also true for GFX940. We need to clean it.	---	1400	// TODO: isGFX90A is also true for GFX940. We need to clean it.	---
1401	bool isGFX90A() const {	0	1401	bool isGFX90A() const {	0
1402	return AMDGPU::isGFX90A(getSTI());	0	1402	return AMDGPU::isGFX90A(getSTI());	0
1403	}	---	1403	}	---
1404		---	1404		---
1405	bool isGFX940() const {	0	1405	bool isGFX940() const {	0
1406	return AMDGPU::isGFX940(getSTI());	0	1406	return AMDGPU::isGFX940(getSTI());	0
1407	}	---	1407	}	---
1408		---	1408		---
1409	bool isGFX9Plus() const {	0	1409	bool isGFX9Plus() const {	0
1410	return AMDGPU::isGFX9Plus(getSTI());	0	1410	return AMDGPU::isGFX9Plus(getSTI());	0
1411	}	---	1411	}	---
1412		---	1412		---
1413	bool isGFX10() const {	---	1413	bool isGFX10() const {	---
1414	return AMDGPU::isGFX10(getSTI());	---	1414	return AMDGPU::isGFX10(getSTI());	---
1415	}	---	1415	}	---
1416		---	1416		---
1417	bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); }	0	1417	bool isGFX10Plus() const { return AMDGPU::isGFX10Plus(getSTI()); }	0
1418		---	1418		---
1419	bool isGFX11() const {	---	1419	bool isGFX11() const {	---
1420	return AMDGPU::isGFX11(getSTI());	---	1420	return AMDGPU::isGFX11(getSTI());	---
1421	}	---	1421	}	---
1422		---	1422		---
1423	bool isGFX11Plus() const {	0	1423	bool isGFX11Plus() const {	0
1424	return AMDGPU::isGFX11Plus(getSTI());	0	1424	return AMDGPU::isGFX11Plus(getSTI());	0
1425	}	---	1425	}	---
1426		---	1426		---
1427	bool isGFX10_AEncoding() const { return AMDGPU::isGFX10_AEncoding(getSTI()); }	0	1427	bool isGFX10_AEncoding() const { return AMDGPU::isGFX10_AEncoding(getSTI()); }	0
1428		---	1428		---
1429	bool isGFX10_BEncoding() const {	---	1429	bool isGFX10_BEncoding() const {	---
1430	return AMDGPU::isGFX10_BEncoding(getSTI());	---	1430	return AMDGPU::isGFX10_BEncoding(getSTI());	---
1431	}	---	1431	}	---
1432		---	1432		---
1433	bool hasInv2PiInlineImm() const {	0	1433	bool hasInv2PiInlineImm() const {	0
1434	return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];	0	1434	return getFeatureBits()[AMDGPU::FeatureInv2PiInlineImm];	0
1435	}	---	1435	}	---
1436		---	1436		---
1437	bool hasFlatOffsets() const {	0	1437	bool hasFlatOffsets() const {	0
1438	return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];	0	1438	return getFeatureBits()[AMDGPU::FeatureFlatInstOffsets];	0
1439	}	---	1439	}	---
1440		---	1440		---
1441	bool hasArchitectedFlatScratch() const {	0	1441	bool hasArchitectedFlatScratch() const {	0
1442	return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];	0	1442	return getFeatureBits()[AMDGPU::FeatureArchitectedFlatScratch];	0
1443	}	---	1443	}	---
1444		---	1444		---
1445	bool hasSGPR102_SGPR103() const {	0	1445	bool hasSGPR102_SGPR103() const {	0
1446	return !isVI() && !isGFX9();	0	1446	return !isVI() && !isGFX9();	0
1447	}	---	1447	}	---
1448		---	1448		---
1449	bool hasSGPR104_SGPR105() const { return isGFX10Plus(); }	0	1449	bool hasSGPR104_SGPR105() const { return isGFX10Plus(); }	0
1450		---	1450		---
1451	bool hasIntClamp() const {	0	1451	bool hasIntClamp() const {	0
1452	return getFeatureBits()[AMDGPU::FeatureIntClamp];	0	1452	return getFeatureBits()[AMDGPU::FeatureIntClamp];	0
1453	}	---	1453	}	---
1454		---	1454		---
1455	bool hasPartialNSAEncoding() const {	0	1455	bool hasPartialNSAEncoding() const {	0
1456	return getFeatureBits()[AMDGPU::FeaturePartialNSAEncoding];	0	1456	return getFeatureBits()[AMDGPU::FeaturePartialNSAEncoding];	0
1457	}	---	1457	}	---
1458		---	1458		---
1459	unsigned getNSAMaxSize() const {	0	1459	unsigned getNSAMaxSize() const {	0
1460	return AMDGPU::getNSAMaxSize(getSTI());	0	1460	return AMDGPU::getNSAMaxSize(getSTI());	0
1461	}	---	1461	}	---
1462		---	1462		---
1463	AMDGPUTargetStreamer &getTargetStreamer() {	0	1463	AMDGPUTargetStreamer &getTargetStreamer() {	0
1464	MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();	0	1464	MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();	0
1465	return static_cast(TS);	0	1465	return static_cast(TS);	0
1466	}	---	1466	}	---
1467		---	1467		---
1468	const MCRegisterInfo *getMRI() const {	0	1468	const MCRegisterInfo *getMRI() const {	0
1469	// We need this const_cast because for some reason getContext() is not const	---	1469	// We need this const_cast because for some reason getContext() is not const	---
1470	// in MCAsmParser.	---	1470	// in MCAsmParser.	---
1471	return const_cast(this)->getContext().getRegisterInfo();	0	1471	return const_cast(this)->getContext().getRegisterInfo();	0
1472	}	---	1472	}	---
1473		---	1473		---
1474	const MCInstrInfo *getMII() const {	0	1474	const MCInstrInfo *getMII() const {	0
1475	return &MII;	0	1475	return &MII;	0
1476	}	---	1476	}	---
1477		---	1477		---
1478	const FeatureBitset &getFeatureBits() const {	0	1478	const FeatureBitset &getFeatureBits() const {	0
1479	return getSTI().getFeatureBits();	0	1479	return getSTI().getFeatureBits();	0
1480	}	---	1480	}	---
1481		---	1481		---
1482	void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }	0	1482	void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }	0
1483	void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }	0	1483	void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }	0
1484	void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }	0	1484	void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }	0
1485		---	1485		---
1486	unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }	0	1486	unsigned getForcedEncodingSize() const { return ForcedEncodingSize; }	0
1487	bool isForcedVOP3() const { return ForcedEncodingSize == 64; }	0	1487	bool isForcedVOP3() const { return ForcedEncodingSize == 64; }	0
1488	bool isForcedDPP() const { return ForcedDPP; }	0	1488	bool isForcedDPP() const { return ForcedDPP; }	0
1489	bool isForcedSDWA() const { return ForcedSDWA; }	0	1489	bool isForcedSDWA() const { return ForcedSDWA; }	0
1490	ArrayRef getMatchedVariants() const;	---	1490	ArrayRef getMatchedVariants() const;	---
1491	StringRef getMatchedVariantName() const;	---	1491	StringRef getMatchedVariantName() const;	---
1492		---	1492		---
1493	std::unique_ptr parseRegister(bool RestoreOnFailure = false);	---	1493	std::unique_ptr parseRegister(bool RestoreOnFailure = false);	---
1494	bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,	---	1494	bool ParseRegister(MCRegister &RegNo, SMLoc &StartLoc, SMLoc &EndLoc,	---
1495	bool RestoreOnFailure);	---	1495	bool RestoreOnFailure);	---
1496	bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	---	1496	bool parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	---
1497	SMLoc &EndLoc) override;	---	1497	SMLoc &EndLoc) override;	---
1498	OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	---	1498	OperandMatchResultTy tryParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	---
1499	SMLoc &EndLoc) override;	---	1499	SMLoc &EndLoc) override;	---
1500	unsigned checkTargetMatchPredicate(MCInst &Inst) override;	---	1500	unsigned checkTargetMatchPredicate(MCInst &Inst) override;	---
1501	unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,	---	1501	unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,	---
1502	unsigned Kind) override;	---	1502	unsigned Kind) override;	---
1503	bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	---	1503	bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	---
1504	OperandVector &Operands, MCStreamer &Out,	---	1504	OperandVector &Operands, MCStreamer &Out,	---
1505	uint64_t &ErrorInfo,	---	1505	uint64_t &ErrorInfo,	---
1506	bool MatchingInlineAsm) override;	---	1506	bool MatchingInlineAsm) override;	---
1507	bool ParseDirective(AsmToken DirectiveID) override;	---	1507	bool ParseDirective(AsmToken DirectiveID) override;	---
1508	ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,	---	1508	ParseStatus parseOperand(OperandVector &Operands, StringRef Mnemonic,	---
1509	OperandMode Mode = OperandMode_Default);	---	1509	OperandMode Mode = OperandMode_Default);	---
1510	StringRef parseMnemonicSuffix(StringRef Name);	---	1510	StringRef parseMnemonicSuffix(StringRef Name);	---
1511	bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,	---	1511	bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,	---
1512	SMLoc NameLoc, OperandVector &Operands) override;	---	1512	SMLoc NameLoc, OperandVector &Operands) override;	---
1513	//bool ProcessInstruction(MCInst &Inst);	---	1513	//bool ProcessInstruction(MCInst &Inst);	---
1514		---	1514		---
1515	ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);	---	1515	ParseStatus parseTokenOp(StringRef Name, OperandVector &Operands);	---
1516		---	1516		---
1517	ParseStatus parseIntWithPrefix(const char *Prefix, int64_t &Int);	---	1517	ParseStatus parseIntWithPrefix(const char *Prefix, int64_t &Int);	---
1518		---	1518		---
1519	ParseStatus	---	1519	ParseStatus	---
1520	parseIntWithPrefix(const char *Prefix, OperandVector &Operands,	---	1520	parseIntWithPrefix(const char *Prefix, OperandVector &Operands,	---
1521	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	---	1521	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	---
1522	std::function ConvertResult = nullptr);	---	1522	std::function ConvertResult = nullptr);	---
1523		---	1523		---
1524	ParseStatus parseOperandArrayWithPrefix(	---	1524	ParseStatus parseOperandArrayWithPrefix(	---
1525	const char *Prefix, OperandVector &Operands,	---	1525	const char *Prefix, OperandVector &Operands,	---
1526	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	---	1526	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,	---
1527	bool (*ConvertResult)(int64_t &) = nullptr);	---	1527	bool (*ConvertResult)(int64_t &) = nullptr);	---
1528		---	1528		---
1529	ParseStatus	---	1529	ParseStatus	---
1530	parseNamedBit(StringRef Name, OperandVector &Operands,	---	1530	parseNamedBit(StringRef Name, OperandVector &Operands,	---
1531	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);	---	1531	AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);	---
1532	unsigned getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const;	---	1532	unsigned getCPolKind(StringRef Id, StringRef Mnemo, bool &Disabling) const;	---
1533	ParseStatus parseCPol(OperandVector &Operands);	---	1533	ParseStatus parseCPol(OperandVector &Operands);	---
1534	ParseStatus parseStringWithPrefix(StringRef Prefix, StringRef &Value,	---	1534	ParseStatus parseStringWithPrefix(StringRef Prefix, StringRef &Value,	---
1535	SMLoc &StringLoc);	---	1535	SMLoc &StringLoc);	---
1536		---	1536		---
1537	bool isModifier();	---	1537	bool isModifier();	---
1538	bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	---	1538	bool isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	---
1539	bool isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	---	1539	bool isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	---
1540	bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	---	1540	bool isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const;	---
1541	bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;	---	1541	bool isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const;	---
1542	bool parseSP3NegModifier();	---	1542	bool parseSP3NegModifier();	---
1543	ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);	---	1543	ParseStatus parseImm(OperandVector &Operands, bool HasSP3AbsModifier = false);	---
1544	ParseStatus parseReg(OperandVector &Operands);	---	1544	ParseStatus parseReg(OperandVector &Operands);	---
1545	ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);	---	1545	ParseStatus parseRegOrImm(OperandVector &Operands, bool HasSP3AbsMod = false);	---
1546	ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,	---	1546	ParseStatus parseRegOrImmWithFPInputMods(OperandVector &Operands,	---
1547	bool AllowImm = true);	---	1547	bool AllowImm = true);	---
1548	ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,	---	1548	ParseStatus parseRegOrImmWithIntInputMods(OperandVector &Operands,	---
1549	bool AllowImm = true);	---	1549	bool AllowImm = true);	---
1550	ParseStatus parseRegWithFPInputMods(OperandVector &Operands);	---	1550	ParseStatus parseRegWithFPInputMods(OperandVector &Operands);	---
1551	ParseStatus parseRegWithIntInputMods(OperandVector &Operands);	---	1551	ParseStatus parseRegWithIntInputMods(OperandVector &Operands);	---
1552	ParseStatus parseVReg32OrOff(OperandVector &Operands);	---	1552	ParseStatus parseVReg32OrOff(OperandVector &Operands);	---
1553	ParseStatus parseDfmtNfmt(int64_t &Format);	---	1553	ParseStatus parseDfmtNfmt(int64_t &Format);	---
1554	ParseStatus parseUfmt(int64_t &Format);	---	1554	ParseStatus parseUfmt(int64_t &Format);	---
1555	ParseStatus parseSymbolicSplitFormat(StringRef FormatStr, SMLoc Loc,	---	1555	ParseStatus parseSymbolicSplitFormat(StringRef FormatStr, SMLoc Loc,	---
1556	int64_t &Format);	---	1556	int64_t &Format);	---
1557	ParseStatus parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc,	---	1557	ParseStatus parseSymbolicUnifiedFormat(StringRef FormatStr, SMLoc Loc,	---
1558	int64_t &Format);	---	1558	int64_t &Format);	---
1559	ParseStatus parseFORMAT(OperandVector &Operands);	---	1559	ParseStatus parseFORMAT(OperandVector &Operands);	---
1560	ParseStatus parseSymbolicOrNumericFormat(int64_t &Format);	---	1560	ParseStatus parseSymbolicOrNumericFormat(int64_t &Format);	---
1561	ParseStatus parseNumericFormat(int64_t &Format);	---	1561	ParseStatus parseNumericFormat(int64_t &Format);	---
1562	ParseStatus parseFlatOffset(OperandVector &Operands);	---	1562	ParseStatus parseFlatOffset(OperandVector &Operands);	---
1563	ParseStatus parseR128A16(OperandVector &Operands);	---	1563	ParseStatus parseR128A16(OperandVector &Operands);	---
1564	ParseStatus parseBLGP(OperandVector &Operands);	---	1564	ParseStatus parseBLGP(OperandVector &Operands);	---
1565	bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);	---	1565	bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);	---
1566	bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);	---	1566	bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);	---
1567		---	1567		---
1568	void cvtExp(MCInst &Inst, const OperandVector &Operands);	---	1568	void cvtExp(MCInst &Inst, const OperandVector &Operands);	---
1569		---	1569		---
1570	bool parseCnt(int64_t &IntVal);	---	1570	bool parseCnt(int64_t &IntVal);	---
1571	ParseStatus parseSWaitCnt(OperandVector &Operands);	---	1571	ParseStatus parseSWaitCnt(OperandVector &Operands);	---
1572		---	1572		---
1573	bool parseDepCtr(int64_t &IntVal, unsigned &Mask);	---	1573	bool parseDepCtr(int64_t &IntVal, unsigned &Mask);	---
1574	void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);	---	1574	void depCtrError(SMLoc Loc, int ErrorId, StringRef DepCtrName);	---
1575	ParseStatus parseDepCtr(OperandVector &Operands);	---	1575	ParseStatus parseDepCtr(OperandVector &Operands);	---
1576		---	1576		---
1577	bool parseDelay(int64_t &Delay);	---	1577	bool parseDelay(int64_t &Delay);	---
1578	ParseStatus parseSDelayALU(OperandVector &Operands);	---	1578	ParseStatus parseSDelayALU(OperandVector &Operands);	---
1579		---	1579		---
1580	ParseStatus parseHwreg(OperandVector &Operands);	---	1580	ParseStatus parseHwreg(OperandVector &Operands);	---
1581		---	1581		---
1582	private:	---	1582	private:	---
1583	struct OperandInfoTy {	---	1583	struct OperandInfoTy {	---
1584	SMLoc Loc;	---	1584	SMLoc Loc;	---
1585	int64_t Id;	---	1585	int64_t Id;	---
1586	bool IsSymbolic = false;	---	1586	bool IsSymbolic = false;	---
1587	bool IsDefined = false;	---	1587	bool IsDefined = false;	---
1588		---	1588		---
1589	OperandInfoTy(int64_t Id_) : Id(Id_) {}	0	1589	OperandInfoTy(int64_t Id_) : Id(Id_) {}	0
1590	};	---	1590	};	---
1591		---	1591		---
1592	bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);	---	1592	bool parseSendMsgBody(OperandInfoTy &Msg, OperandInfoTy &Op, OperandInfoTy &Stream);	---
1593	bool validateSendMsg(const OperandInfoTy &Msg,	---	1593	bool validateSendMsg(const OperandInfoTy &Msg,	---
1594	const OperandInfoTy &Op,	---	1594	const OperandInfoTy &Op,	---
1595	const OperandInfoTy &Stream);	---	1595	const OperandInfoTy &Stream);	---
1596		---	1596		---
1597	bool parseHwregBody(OperandInfoTy &HwReg,	---	1597	bool parseHwregBody(OperandInfoTy &HwReg,	---
1598	OperandInfoTy &Offset,	---	1598	OperandInfoTy &Offset,	---
1599	OperandInfoTy &Width);	---	1599	OperandInfoTy &Width);	---
1600	bool validateHwreg(const OperandInfoTy &HwReg,	---	1600	bool validateHwreg(const OperandInfoTy &HwReg,	---
1601	const OperandInfoTy &Offset,	---	1601	const OperandInfoTy &Offset,	---
1602	const OperandInfoTy &Width);	---	1602	const OperandInfoTy &Width);	---
1603		---	1603		---
1604	SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;	---	1604	SMLoc getFlatOffsetLoc(const OperandVector &Operands) const;	---
1605	SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;	---	1605	SMLoc getSMEMOffsetLoc(const OperandVector &Operands) const;	---
1606	SMLoc getBLGPLoc(const OperandVector &Operands) const;	---	1606	SMLoc getBLGPLoc(const OperandVector &Operands) const;	---
1607		---	1607		---
1608	SMLoc getOperandLoc(std::function Test,	---	1608	SMLoc getOperandLoc(std::function Test,	---
1609	const OperandVector &Operands) const;	---	1609	const OperandVector &Operands) const;	---
1610	SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;	---	1610	SMLoc getImmLoc(AMDGPUOperand::ImmTy Type, const OperandVector &Operands) const;	---
1611	SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;	---	1611	SMLoc getRegLoc(unsigned Reg, const OperandVector &Operands) const;	---
1612	SMLoc getLitLoc(const OperandVector &Operands,	---	1612	SMLoc getLitLoc(const OperandVector &Operands,	---
1613	bool SearchMandatoryLiterals = false) const;	---	1613	bool SearchMandatoryLiterals = false) const;	---
1614	SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;	---	1614	SMLoc getMandatoryLitLoc(const OperandVector &Operands) const;	---
1615	SMLoc getConstLoc(const OperandVector &Operands) const;	---	1615	SMLoc getConstLoc(const OperandVector &Operands) const;	---
1616	SMLoc getInstLoc(const OperandVector &Operands) const;	---	1616	SMLoc getInstLoc(const OperandVector &Operands) const;	---
1617		---	1617		---
1618	bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);	---	1618	bool validateInstruction(const MCInst &Inst, const SMLoc &IDLoc, const OperandVector &Operands);	---
1619	bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);	---	1619	bool validateFlatOffset(const MCInst &Inst, const OperandVector &Operands);	---
1620	bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);	---	1620	bool validateSMEMOffset(const MCInst &Inst, const OperandVector &Operands);	---
1621	bool validateSOPLiteral(const MCInst &Inst) const;	---	1621	bool validateSOPLiteral(const MCInst &Inst) const;	---
1622	bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);	---	1622	bool validateConstantBusLimitations(const MCInst &Inst, const OperandVector &Operands);	---
1623	bool validateVOPDRegBankConstraints(const MCInst &Inst,	---	1623	bool validateVOPDRegBankConstraints(const MCInst &Inst,	---
1624	const OperandVector &Operands);	---	1624	const OperandVector &Operands);	---
1625	bool validateIntClampSupported(const MCInst &Inst);	---	1625	bool validateIntClampSupported(const MCInst &Inst);	---
1626	bool validateMIMGAtomicDMask(const MCInst &Inst);	---	1626	bool validateMIMGAtomicDMask(const MCInst &Inst);	---
1627	bool validateMIMGGatherDMask(const MCInst &Inst);	---	1627	bool validateMIMGGatherDMask(const MCInst &Inst);	---
1628	bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);	---	1628	bool validateMovrels(const MCInst &Inst, const OperandVector &Operands);	---
1629	bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);	---	1629	bool validateMIMGDataSize(const MCInst &Inst, const SMLoc &IDLoc);	---
1630	bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);	---	1630	bool validateMIMGAddrSize(const MCInst &Inst, const SMLoc &IDLoc);	---
1631	bool validateMIMGD16(const MCInst &Inst);	---	1631	bool validateMIMGD16(const MCInst &Inst);	---
1632	bool validateMIMGMSAA(const MCInst &Inst);	---	1632	bool validateMIMGMSAA(const MCInst &Inst);	---
1633	bool validateOpSel(const MCInst &Inst);	---	1633	bool validateOpSel(const MCInst &Inst);	---
1634	bool validateDPP(const MCInst &Inst, const OperandVector &Operands);	---	1634	bool validateDPP(const MCInst &Inst, const OperandVector &Operands);	---
1635	bool validateVccOperand(unsigned Reg) const;	---	1635	bool validateVccOperand(unsigned Reg) const;	---
1636	bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);	---	1636	bool validateVOPLiteral(const MCInst &Inst, const OperandVector &Operands);	---
1637	bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);	---	1637	bool validateMAIAccWrite(const MCInst &Inst, const OperandVector &Operands);	---
1638	bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);	---	1638	bool validateMAISrc2(const MCInst &Inst, const OperandVector &Operands);	---
1639	bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);	---	1639	bool validateMFMA(const MCInst &Inst, const OperandVector &Operands);	---
1640	bool validateAGPRLdSt(const MCInst &Inst) const;	---	1640	bool validateAGPRLdSt(const MCInst &Inst) const;	---
1641	bool validateVGPRAlign(const MCInst &Inst) const;	---	1641	bool validateVGPRAlign(const MCInst &Inst) const;	---
1642	bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);	---	1642	bool validateBLGP(const MCInst &Inst, const OperandVector &Operands);	---
1643	bool validateGWS(const MCInst &Inst, const OperandVector &Operands);	---	1643	bool validateGWS(const MCInst &Inst, const OperandVector &Operands);	---
1644	bool validateDivScale(const MCInst &Inst);	---	1644	bool validateDivScale(const MCInst &Inst);	---
1645	bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);	---	1645	bool validateWaitCnt(const MCInst &Inst, const OperandVector &Operands);	---
1646	bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,	---	1646	bool validateCoherencyBits(const MCInst &Inst, const OperandVector &Operands,	---
1647	const SMLoc &IDLoc);	---	1647	const SMLoc &IDLoc);	---
1648	bool validateExeczVcczOperands(const OperandVector &Operands);	---	1648	bool validateExeczVcczOperands(const OperandVector &Operands);	---
1649	bool validateTFE(const MCInst &Inst, const OperandVector &Operands);	---	1649	bool validateTFE(const MCInst &Inst, const OperandVector &Operands);	---
1650	std::optional validateLdsDirect(const MCInst &Inst);	---	1650	std::optional validateLdsDirect(const MCInst &Inst);	---
1651	unsigned getConstantBusLimit(unsigned Opcode) const;	---	1651	unsigned getConstantBusLimit(unsigned Opcode) const;	---
1652	bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);	---	1652	bool usesConstantBus(const MCInst &Inst, unsigned OpIdx);	---
1653	bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;	---	1653	bool isInlineConstant(const MCInst &Inst, unsigned OpIdx) const;	---
1654	unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;	---	1654	unsigned findImplicitSGPRReadInVOP(const MCInst &Inst) const;	---
1655		---	1655		---
1656	bool isSupportedMnemo(StringRef Mnemo,	---	1656	bool isSupportedMnemo(StringRef Mnemo,	---
1657	const FeatureBitset &FBS);	---	1657	const FeatureBitset &FBS);	---
1658	bool isSupportedMnemo(StringRef Mnemo,	---	1658	bool isSupportedMnemo(StringRef Mnemo,	---
1659	const FeatureBitset &FBS,	---	1659	const FeatureBitset &FBS,	---
1660	ArrayRef Variants);	---	1660	ArrayRef Variants);	---
1661	bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);	---	1661	bool checkUnsupportedInstruction(StringRef Name, const SMLoc &IDLoc);	---
1662		---	1662		---
1663	bool isId(const StringRef Id) const;	---	1663	bool isId(const StringRef Id) const;	---
1664	bool isId(const AsmToken &Token, const StringRef Id) const;	---	1664	bool isId(const AsmToken &Token, const StringRef Id) const;	---
1665	bool isToken(const AsmToken::TokenKind Kind) const;	---	1665	bool isToken(const AsmToken::TokenKind Kind) const;	---
1666	StringRef getId() const;	---	1666	StringRef getId() const;	---
1667	bool trySkipId(const StringRef Id);	---	1667	bool trySkipId(const StringRef Id);	---
1668	bool trySkipId(const StringRef Pref, const StringRef Id);	---	1668	bool trySkipId(const StringRef Pref, const StringRef Id);	---
1669	bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind);	---	1669	bool trySkipId(const StringRef Id, const AsmToken::TokenKind Kind);	---
1670	bool trySkipToken(const AsmToken::TokenKind Kind);	---	1670	bool trySkipToken(const AsmToken::TokenKind Kind);	---
1671	bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);	---	1671	bool skipToken(const AsmToken::TokenKind Kind, const StringRef ErrMsg);	---
1672	bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");	---	1672	bool parseString(StringRef &Val, const StringRef ErrMsg = "expected a string");	---
1673	bool parseId(StringRef &Val, const StringRef ErrMsg = "");	---	1673	bool parseId(StringRef &Val, const StringRef ErrMsg = "");	---
1674		---	1674		---
1675	void peekTokens(MutableArrayRef Tokens);	---	1675	void peekTokens(MutableArrayRef Tokens);	---
1676	AsmToken::TokenKind getTokenKind() const;	---	1676	AsmToken::TokenKind getTokenKind() const;	---
1677	bool parseExpr(int64_t &Imm, StringRef Expected = "");	---	1677	bool parseExpr(int64_t &Imm, StringRef Expected = "");	---
1678	bool parseExpr(OperandVector &Operands);	---	1678	bool parseExpr(OperandVector &Operands);	---
1679	StringRef getTokenStr() const;	---	1679	StringRef getTokenStr() const;	---
1680	AsmToken peekToken(bool ShouldSkipSpace = true);	---	1680	AsmToken peekToken(bool ShouldSkipSpace = true);	---
1681	AsmToken getToken() const;	---	1681	AsmToken getToken() const;	---
1682	SMLoc getLoc() const;	---	1682	SMLoc getLoc() const;	---
1683	void lex();	---	1683	void lex();	---
1684		---	1684		---
1685	public:	---	1685	public:	---
1686	void onBeginOfFile() override;	---	1686	void onBeginOfFile() override;	---
1687		---	1687		---
1688	ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);	---	1688	ParseStatus parseCustomOperand(OperandVector &Operands, unsigned MCK);	---
1689		---	1689		---
1690	ParseStatus parseExpTgt(OperandVector &Operands);	---	1690	ParseStatus parseExpTgt(OperandVector &Operands);	---
1691	ParseStatus parseSendMsg(OperandVector &Operands);	---	1691	ParseStatus parseSendMsg(OperandVector &Operands);	---
1692	ParseStatus parseInterpSlot(OperandVector &Operands);	---	1692	ParseStatus parseInterpSlot(OperandVector &Operands);	---
1693	ParseStatus parseInterpAttr(OperandVector &Operands);	---	1693	ParseStatus parseInterpAttr(OperandVector &Operands);	---
1694	ParseStatus parseSOPPBrTarget(OperandVector &Operands);	---	1694	ParseStatus parseSOPPBrTarget(OperandVector &Operands);	---
1695	ParseStatus parseBoolReg(OperandVector &Operands);	---	1695	ParseStatus parseBoolReg(OperandVector &Operands);	---
1696		---	1696		---
1697	bool parseSwizzleOperand(int64_t &Op,	---	1697	bool parseSwizzleOperand(int64_t &Op,	---
1698	const unsigned MinVal,	---	1698	const unsigned MinVal,	---
1699	const unsigned MaxVal,	---	1699	const unsigned MaxVal,	---
1700	const StringRef ErrMsg,	---	1700	const StringRef ErrMsg,	---
1701	SMLoc &Loc);	---	1701	SMLoc &Loc);	---
1702	bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	---	1702	bool parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	---
1703	const unsigned MinVal,	---	1703	const unsigned MinVal,	---
1704	const unsigned MaxVal,	---	1704	const unsigned MaxVal,	---
1705	const StringRef ErrMsg);	---	1705	const StringRef ErrMsg);	---
1706	ParseStatus parseSwizzle(OperandVector &Operands);	---	1706	ParseStatus parseSwizzle(OperandVector &Operands);	---
1707	bool parseSwizzleOffset(int64_t &Imm);	---	1707	bool parseSwizzleOffset(int64_t &Imm);	---
1708	bool parseSwizzleMacro(int64_t &Imm);	---	1708	bool parseSwizzleMacro(int64_t &Imm);	---
1709	bool parseSwizzleQuadPerm(int64_t &Imm);	---	1709	bool parseSwizzleQuadPerm(int64_t &Imm);	---
1710	bool parseSwizzleBitmaskPerm(int64_t &Imm);	---	1710	bool parseSwizzleBitmaskPerm(int64_t &Imm);	---
1711	bool parseSwizzleBroadcast(int64_t &Imm);	---	1711	bool parseSwizzleBroadcast(int64_t &Imm);	---
1712	bool parseSwizzleSwap(int64_t &Imm);	---	1712	bool parseSwizzleSwap(int64_t &Imm);	---
1713	bool parseSwizzleReverse(int64_t &Imm);	---	1713	bool parseSwizzleReverse(int64_t &Imm);	---
1714		---	1714		---
1715	ParseStatus parseGPRIdxMode(OperandVector &Operands);	---	1715	ParseStatus parseGPRIdxMode(OperandVector &Operands);	---
1716	int64_t parseGPRIdxMacro();	---	1716	int64_t parseGPRIdxMacro();	---
1717		---	1717		---
1718	void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }	0	1718	void cvtMubuf(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, false); }	0
1719	void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }	0	1719	void cvtMubufAtomic(MCInst &Inst, const OperandVector &Operands) { cvtMubufImpl(Inst, Operands, true); }	0
1720		---	1720		---
1721	ParseStatus parseOModSI(OperandVector &Operands);	---	1721	ParseStatus parseOModSI(OperandVector &Operands);	---
1722		---	1722		---
1723	void cvtVOP3(MCInst &Inst, const OperandVector &Operands,	---	1723	void cvtVOP3(MCInst &Inst, const OperandVector &Operands,	---
1724	OptionalImmIndexMap &OptionalIdx);	---	1724	OptionalImmIndexMap &OptionalIdx);	---
1725	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);	---	1725	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands);	---
1726	void cvtVOP3(MCInst &Inst, const OperandVector &Operands);	---	1726	void cvtVOP3(MCInst &Inst, const OperandVector &Operands);	---
1727	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);	---	1727	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands);	---
1728	void cvtVOPD(MCInst &Inst, const OperandVector &Operands);	---	1728	void cvtVOPD(MCInst &Inst, const OperandVector &Operands);	---
1729	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	---	1729	void cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	---
1730	OptionalImmIndexMap &OptionalIdx);	---	1730	OptionalImmIndexMap &OptionalIdx);	---
1731	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	---	1731	void cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	---
1732	OptionalImmIndexMap &OptionalIdx);	---	1732	OptionalImmIndexMap &OptionalIdx);	---
1733		---	1733		---
1734	void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);	---	1734	void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);	---
1735	void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);	---	1735	void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);	---
1736	void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);	---	1736	void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);	---
1737		---	1737		---
1738	bool parseDimId(unsigned &Encoding);	---	1738	bool parseDimId(unsigned &Encoding);	---
1739	ParseStatus parseDim(OperandVector &Operands);	---	1739	ParseStatus parseDim(OperandVector &Operands);	---
1740	bool convertDppBoundCtrl(int64_t &BoundCtrl);	---	1740	bool convertDppBoundCtrl(int64_t &BoundCtrl);	---
1741	ParseStatus parseDPP8(OperandVector &Operands);	---	1741	ParseStatus parseDPP8(OperandVector &Operands);	---
1742	ParseStatus parseDPPCtrl(OperandVector &Operands);	---	1742	ParseStatus parseDPPCtrl(OperandVector &Operands);	---
1743	bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);	---	1743	bool isSupportedDPPCtrl(StringRef Ctrl, const OperandVector &Operands);	---
1744	int64_t parseDPPCtrlSel(StringRef Ctrl);	---	1744	int64_t parseDPPCtrlSel(StringRef Ctrl);	---
1745	int64_t parseDPPCtrlPerm();	---	1745	int64_t parseDPPCtrlPerm();	---
1746	void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);	---	1746	void cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8 = false);	---
1747	void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {	0	1747	void cvtDPP8(MCInst &Inst, const OperandVector &Operands) {	0
1748	cvtDPP(Inst, Operands, true);	0	1748	cvtDPP(Inst, Operands, true);	0
1749	}	0	1749	}	0
1750	void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	---	1750	void cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	---
1751	bool IsDPP8 = false);	---	1751	bool IsDPP8 = false);	---
1752	void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {	0	1752	void cvtVOP3DPP8(MCInst &Inst, const OperandVector &Operands) {	0
1753	cvtVOP3DPP(Inst, Operands, true);	0	1753	cvtVOP3DPP(Inst, Operands, true);	0
1754	}	0	1754	}	0
1755		---	1755		---
1756	ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,	---	1756	ParseStatus parseSDWASel(OperandVector &Operands, StringRef Prefix,	---
1757	AMDGPUOperand::ImmTy Type);	---	1757	AMDGPUOperand::ImmTy Type);	---
1758	ParseStatus parseSDWADstUnused(OperandVector &Operands);	---	1758	ParseStatus parseSDWADstUnused(OperandVector &Operands);	---
1759	void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);	---	1759	void cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands);	---
1760	void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);	---	1760	void cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands);	---
1761	void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);	---	1761	void cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands);	---
1762	void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);	---	1762	void cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands);	---
1763	void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);	---	1763	void cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands);	---
1764	void cvtSDWA(MCInst &Inst, const OperandVector &Operands,	---	1764	void cvtSDWA(MCInst &Inst, const OperandVector &Operands,	---
1765	uint64_t BasicInstType,	---	1765	uint64_t BasicInstType,	---
1766	bool SkipDstVcc = false,	---	1766	bool SkipDstVcc = false,	---
1767	bool SkipSrcVcc = false);	---	1767	bool SkipSrcVcc = false);	---
1768		---	1768		---
1769	ParseStatus parseEndpgm(OperandVector &Operands);	---	1769	ParseStatus parseEndpgm(OperandVector &Operands);	---
1770		---	1770		---
1771	ParseStatus parseVOPD(OperandVector &Operands);	---	1771	ParseStatus parseVOPD(OperandVector &Operands);	---
1772	};	---	1772	};	---
1773		---	1773		---
1774	} // end anonymous namespace	---	1774	} // end anonymous namespace	---
1775		---	1775		---
1776	// May be called with integer type with equivalent bitwidth.	---	1776	// May be called with integer type with equivalent bitwidth.	---
1777	static const fltSemantics *getFltSemantics(unsigned Size) {	0	1777	static const fltSemantics *getFltSemantics(unsigned Size) {	0
1778	switch (Size) {	0	1778	switch (Size) {	0
1779	case 4:	0	1779	case 4:	0
1780	return &APFloat::IEEEsingle();	0	1780	return &APFloat::IEEEsingle();	0
1781	case 8:	0	1781	case 8:	0
1782	return &APFloat::IEEEdouble();	0	1782	return &APFloat::IEEEdouble();	0
1783	case 2:	0	1783	case 2:	0
1784	return &APFloat::IEEEhalf();	0	1784	return &APFloat::IEEEhalf();	0
1785	default:	0	1785	default:	0
1786	llvm_unreachable("unsupported fp type");	0	1786	llvm_unreachable("unsupported fp type");	0
1787	}	---	1787	}	---
1788	}	---	1788	}	---
1789		---	1789		---
1790	static const fltSemantics *getFltSemantics(MVT VT) {	0	1790	static const fltSemantics *getFltSemantics(MVT VT) {	0
1791	return getFltSemantics(VT.getSizeInBits() / 8);	0	1791	return getFltSemantics(VT.getSizeInBits() / 8);	0
1792	}	---	1792	}	---
1793		---	1793		---
1794	static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {	0	1794	static const fltSemantics *getOpFltSemantics(uint8_t OperandType) {	0
1795	switch (OperandType) {	0	1795	switch (OperandType) {	0
1796	case AMDGPU::OPERAND_REG_IMM_INT32:	0	1796	case AMDGPU::OPERAND_REG_IMM_INT32:	0
1797	case AMDGPU::OPERAND_REG_IMM_FP32:	---	1797	case AMDGPU::OPERAND_REG_IMM_FP32:	---
1798	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	---	1798	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	---
1799	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	---	1799	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	---
1800	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	---	1800	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	---
1801	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	---	1801	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	---
1802	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	---	1802	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	---
1803	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	---	1803	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	---
1804	case AMDGPU::OPERAND_REG_IMM_V2FP32:	---	1804	case AMDGPU::OPERAND_REG_IMM_V2FP32:	---
1805	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	---	1805	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	---
1806	case AMDGPU::OPERAND_REG_IMM_V2INT32:	---	1806	case AMDGPU::OPERAND_REG_IMM_V2INT32:	---
1807	case AMDGPU::OPERAND_KIMM32:	---	1807	case AMDGPU::OPERAND_KIMM32:	---
1808	return &APFloat::IEEEsingle();	0	1808	return &APFloat::IEEEsingle();	0
1809	case AMDGPU::OPERAND_REG_IMM_INT64:	0	1809	case AMDGPU::OPERAND_REG_IMM_INT64:	0
1810	case AMDGPU::OPERAND_REG_IMM_FP64:	---	1810	case AMDGPU::OPERAND_REG_IMM_FP64:	---
1811	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	---	1811	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	---
1812	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	---	1812	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	---
1813	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	---	1813	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	---
1814	return &APFloat::IEEEdouble();	0	1814	return &APFloat::IEEEdouble();	0
1815	case AMDGPU::OPERAND_REG_IMM_INT16:	0	1815	case AMDGPU::OPERAND_REG_IMM_INT16:	0
1816	case AMDGPU::OPERAND_REG_IMM_FP16:	---	1816	case AMDGPU::OPERAND_REG_IMM_FP16:	---
1817	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	---	1817	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	---
1818	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	---	1818	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	---
1819	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	---	1819	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	---
1820	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	---	1820	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	---
1821	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	---	1821	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	---
1822	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	---	1822	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	---
1823	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	---	1823	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	---
1824	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	---	1824	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	---
1825	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	---	1825	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	---
1826	case AMDGPU::OPERAND_REG_IMM_V2INT16:	---	1826	case AMDGPU::OPERAND_REG_IMM_V2INT16:	---
1827	case AMDGPU::OPERAND_REG_IMM_V2FP16:	---	1827	case AMDGPU::OPERAND_REG_IMM_V2FP16:	---
1828	case AMDGPU::OPERAND_KIMM16:	---	1828	case AMDGPU::OPERAND_KIMM16:	---
1829	return &APFloat::IEEEhalf();	0	1829	return &APFloat::IEEEhalf();	0
1830	default:	0	1830	default:	0
1831	llvm_unreachable("unsupported fp type");	0	1831	llvm_unreachable("unsupported fp type");	0
1832	}	---	1832	}	---
1833	}	---	1833	}	---
1834		---	1834		---
1835	//===----------------------------------------------------------------------===//	---	1835	//===----------------------------------------------------------------------===//	---
1836	// Operand	---	1836	// Operand	---
1837	//===----------------------------------------------------------------------===//	---	1837	//===----------------------------------------------------------------------===//	---
1838		---	1838		---
1839	static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) {	0	1839	static bool canLosslesslyConvertToFPType(APFloat &FPLiteral, MVT VT) {	0
1840	bool Lost;	---	1840	bool Lost;	---
1841		---	1841		---
1842	// Convert literal to single precision	---	1842	// Convert literal to single precision	---
1843	APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT),	0	1843	APFloat::opStatus Status = FPLiteral.convert(*getFltSemantics(VT),	0
1844	APFloat::rmNearestTiesToEven,	---	1844	APFloat::rmNearestTiesToEven,	---
1845	&Lost);	---	1845	&Lost);	---
1846	// We allow precision lost but not overflow or underflow	---	1846	// We allow precision lost but not overflow or underflow	---
1847	if (Status != APFloat::opOK &&	0	1847	if (Status != APFloat::opOK &&	0
1848	Lost &&	0	1848	Lost &&	0
1849	((Status & APFloat::opOverflow) != 0 \|\|	0	1849	((Status & APFloat::opOverflow) != 0 \|\|	0
1850	(Status & APFloat::opUnderflow) != 0)) {	0	1850	(Status & APFloat::opUnderflow) != 0)) {	0
1851	return false;	0	1851	return false;	0
1852	}	---	1852	}	---
1853		---	1853		---
1854	return true;	0	1854	return true;	0
1855	}	---	1855	}	---
1856		---	1856		---
1857	static bool isSafeTruncation(int64_t Val, unsigned Size) {	0	1857	static bool isSafeTruncation(int64_t Val, unsigned Size) {	0
1858	return isUIntN(Size, Val) \|\| isIntN(Size, Val);	0	1858	return isUIntN(Size, Val) \|\| isIntN(Size, Val);	0
1859	}	---	1859	}	---
1860		---	1860		---
1861	static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) {	0	1861	static bool isInlineableLiteralOp16(int64_t Val, MVT VT, bool HasInv2Pi) {	0
1862	if (VT.getScalarType() == MVT::i16) {	0	1862	if (VT.getScalarType() == MVT::i16) {	0
1863	// FP immediate values are broken.	---	1863	// FP immediate values are broken.	---
1864	return isInlinableIntLiteral(Val);	0	1864	return isInlinableIntLiteral(Val);	0
1865	}	---	1865	}	---
1866		---	1866		---
1867	// f16/v2f16 operands work correctly for all values.	---	1867	// f16/v2f16 operands work correctly for all values.	---
1868	return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi);	0	1868	return AMDGPU::isInlinableLiteral16(Val, HasInv2Pi);	0
1869	}	---	1869	}	---
1870		---	1870		---
1871	bool AMDGPUOperand::isInlinableImm(MVT type) const {	0	1871	bool AMDGPUOperand::isInlinableImm(MVT type) const {	0
1872		---	1872		---
1873	// This is a hack to enable named inline values like	---	1873	// This is a hack to enable named inline values like	---
1874	// shared_base with both 32-bit and 64-bit operands.	---	1874	// shared_base with both 32-bit and 64-bit operands.	---
1875	// Note that these values are defined as	---	1875	// Note that these values are defined as	---
1876	// 32-bit operands only.	---	1876	// 32-bit operands only.	---
1877	if (isInlineValue()) {	0	1877	if (isInlineValue()) {	0
1878	return true;	0	1878	return true;	0
1879	}	---	1879	}	---
1880		---	1880		---
1881	if (!isImmTy(ImmTyNone)) {	0	1881	if (!isImmTy(ImmTyNone)) {	0
1882	// Only plain immediates are inlinable (e.g. "clamp" attribute is not)	---	1882	// Only plain immediates are inlinable (e.g. "clamp" attribute is not)	---
1883	return false;	0	1883	return false;	0
1884	}	---	1884	}	---
1885	// TODO: We should avoid using host float here. It would be better to	---	1885	// TODO: We should avoid using host float here. It would be better to	---
1886	// check the float bit values which is what a few other places do.	---	1886	// check the float bit values which is what a few other places do.	---
1887	// We've had bot failures before due to weird NaN support on mips hosts.	---	1887	// We've had bot failures before due to weird NaN support on mips hosts.	---
1888		---	1888		---
1889	APInt Literal(64, Imm.Val);	0	1889	APInt Literal(64, Imm.Val);	0
1890		---	1890		---
1891	if (Imm.IsFPImm) { // We got fp literal token	0	1891	if (Imm.IsFPImm) { // We got fp literal token	0
1892	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	0	1892	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	0
1893	return AMDGPU::isInlinableLiteral64(Imm.Val,	0	1893	return AMDGPU::isInlinableLiteral64(Imm.Val,	0
1894	AsmParser->hasInv2PiInlineImm());	0	1894	AsmParser->hasInv2PiInlineImm());	0
1895	}	---	1895	}	---
1896		---	1896		---
1897	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	0	1897	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	0
1898	if (!canLosslesslyConvertToFPType(FPLiteral, type))	0	1898	if (!canLosslesslyConvertToFPType(FPLiteral, type))	0
1899	return false;	0	1899	return false;	0
1900		---	1900		---
1901	if (type.getScalarSizeInBits() == 16) {	0	1901	if (type.getScalarSizeInBits() == 16) {	0
1902	return isInlineableLiteralOp16(	0	1902	return isInlineableLiteralOp16(	0
1903	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	0	1903	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	0
1904	type, AsmParser->hasInv2PiInlineImm());	0	1904	type, AsmParser->hasInv2PiInlineImm());	0
1905	}	---	1905	}	---
1906		---	1906		---
1907	// Check if single precision literal is inlinable	---	1907	// Check if single precision literal is inlinable	---
1908	return AMDGPU::isInlinableLiteral32(	0	1908	return AMDGPU::isInlinableLiteral32(	0
1909	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	0	1909	static_cast(FPLiteral.bitcastToAPInt().getZExtValue()),	0
1910	AsmParser->hasInv2PiInlineImm());	0	1910	AsmParser->hasInv2PiInlineImm());	0
1911	}	0	1911	}	0
1912		---	1912		---
1913	// We got int literal token.	---	1913	// We got int literal token.	---
1914	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	0	1914	if (type == MVT::f64 \|\| type == MVT::i64) { // Expected 64-bit operand	0
1915	return AMDGPU::isInlinableLiteral64(Imm.Val,	0	1915	return AMDGPU::isInlinableLiteral64(Imm.Val,	0
1916	AsmParser->hasInv2PiInlineImm());	0	1916	AsmParser->hasInv2PiInlineImm());	0
1917	}	---	1917	}	---
1918		---	1918		---
1919	if (!isSafeTruncation(Imm.Val, type.getScalarSizeInBits())) {	0	1919	if (!isSafeTruncation(Imm.Val, type.getScalarSizeInBits())) {	0
1920	return false;	0	1920	return false;	0
1921	}	---	1921	}	---
1922		---	1922		---
1923	if (type.getScalarSizeInBits() == 16) {	0	1923	if (type.getScalarSizeInBits() == 16) {	0
1924	return isInlineableLiteralOp16(	0	1924	return isInlineableLiteralOp16(	0
1925	static_cast(Literal.getLoBits(16).getSExtValue()),	0	1925	static_cast(Literal.getLoBits(16).getSExtValue()),	0
1926	type, AsmParser->hasInv2PiInlineImm());	0	1926	type, AsmParser->hasInv2PiInlineImm());	0
1927	}	---	1927	}	---
1928		---	1928		---
1929	return AMDGPU::isInlinableLiteral32(	0	1929	return AMDGPU::isInlinableLiteral32(	0
1930	static_cast(Literal.getLoBits(32).getZExtValue()),	0	1930	static_cast(Literal.getLoBits(32).getZExtValue()),	0
1931	AsmParser->hasInv2PiInlineImm());	0	1931	AsmParser->hasInv2PiInlineImm());	0
1932	}	0	1932	}	0
1933		---	1933		---
1934	bool AMDGPUOperand::isLiteralImm(MVT type) const {	0	1934	bool AMDGPUOperand::isLiteralImm(MVT type) const {	0
1935	// Check that this immediate can be added as literal	---	1935	// Check that this immediate can be added as literal	---
1936	if (!isImmTy(ImmTyNone)) {	0	1936	if (!isImmTy(ImmTyNone)) {	0
1937	return false;	0	1937	return false;	0
1938	}	---	1938	}	---
1939		---	1939		---
1940	if (!Imm.IsFPImm) {	0	1940	if (!Imm.IsFPImm) {	0
1941	// We got int literal token.	---	1941	// We got int literal token.	---
1942		---	1942		---
1943	if (type == MVT::f64 && hasFPModifiers()) {	0	1943	if (type == MVT::f64 && hasFPModifiers()) {	0
1944	// Cannot apply fp modifiers to int literals preserving the same semantics	---	1944	// Cannot apply fp modifiers to int literals preserving the same semantics	---
1945	// for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,	---	1945	// for VOP1/2/C and VOP3 because of integer truncation. To avoid ambiguity,	---
1946	// disable these cases.	---	1946	// disable these cases.	---
1947	return false;	0	1947	return false;	0
1948	}	---	1948	}	---
1949		---	1949		---
1950	unsigned Size = type.getSizeInBits();	0	1950	unsigned Size = type.getSizeInBits();	0
1951	if (Size == 64)	0	1951	if (Size == 64)	0
1952	Size = 32;	0	1952	Size = 32;	0
1953		---	1953		---
1954	// FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP	---	1954	// FIXME: 64-bit operands can zero extend, sign extend, or pad zeroes for FP	---
1955	// types.	---	1955	// types.	---
1956	return isSafeTruncation(Imm.Val, Size);	0	1956	return isSafeTruncation(Imm.Val, Size);	0
1957	}	---	1957	}	---
1958		---	1958		---
1959	// We got fp literal token	---	1959	// We got fp literal token	---
1960	if (type == MVT::f64) { // Expected 64-bit fp operand	0	1960	if (type == MVT::f64) { // Expected 64-bit fp operand	0
1961	// We would set low 64-bits of literal to zeroes but we accept this literals	---	1961	// We would set low 64-bits of literal to zeroes but we accept this literals	---
1962	return true;	0	1962	return true;	0
1963	}	---	1963	}	---
1964		---	1964		---
1965	if (type == MVT::i64) { // Expected 64-bit int operand	0	1965	if (type == MVT::i64) { // Expected 64-bit int operand	0
1966	// We don't allow fp literals in 64-bit integer instructions. It is	---	1966	// We don't allow fp literals in 64-bit integer instructions. It is	---
1967	// unclear how we should encode them.	---	1967	// unclear how we should encode them.	---
1968	return false;	0	1968	return false;	0
1969	}	---	1969	}	---
1970		---	1970		---
1971	// We allow fp literals with f16x2 operands assuming that the specified	---	1971	// We allow fp literals with f16x2 operands assuming that the specified	---
1972	// literal goes into the lower half and the upper half is zero. We also	---	1972	// literal goes into the lower half and the upper half is zero. We also	---
1973	// require that the literal may be losslessly converted to f16.	---	1973	// require that the literal may be losslessly converted to f16.	---
1974	MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :	0	1974	MVT ExpectedType = (type == MVT::v2f16)? MVT::f16 :	0
1975	(type == MVT::v2i16)? MVT::i16 :	0	1975	(type == MVT::v2i16)? MVT::i16 :	0
1976	(type == MVT::v2f32)? MVT::f32 : type;	0	1976	(type == MVT::v2f32)? MVT::f32 : type;	0
1977		---	1977		---
1978	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	0	1978	APFloat FPLiteral(APFloat::IEEEdouble(), APInt(64, Imm.Val));	0
1979	return canLosslesslyConvertToFPType(FPLiteral, ExpectedType);	0	1979	return canLosslesslyConvertToFPType(FPLiteral, ExpectedType);	0
1980	}	0	1980	}	0
1981		---	1981		---
1982	bool AMDGPUOperand::isRegClass(unsigned RCID) const {	0	1982	bool AMDGPUOperand::isRegClass(unsigned RCID) const {	0
1983	return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());	0	1983	return isRegKind() && AsmParser->getMRI()->getRegClass(RCID).contains(getReg());	0
1984	}	---	1984	}	---
1985		---	1985		---
1986	bool AMDGPUOperand::isVRegWithInputMods() const {	0	1986	bool AMDGPUOperand::isVRegWithInputMods() const {	0
1987	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	0	1987	return isRegClass(AMDGPU::VGPR_32RegClassID) \|\|	0
1988	// GFX90A allows DPP on 64-bit operands.	---	1988	// GFX90A allows DPP on 64-bit operands.	---
1989	(isRegClass(AMDGPU::VReg_64RegClassID) &&	0	1989	(isRegClass(AMDGPU::VReg_64RegClassID) &&	0
1990	AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]);	0	1990	AsmParser->getFeatureBits()[AMDGPU::Feature64BitDPP]);	0
1991	}	---	1991	}	---
1992		---	1992		---
1993	bool AMDGPUOperand::isT16VRegWithInputMods() const {	0	1993	bool AMDGPUOperand::isT16VRegWithInputMods() const {	0
1994	return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID);	0	1994	return isRegClass(AMDGPU::VGPR_32_Lo128RegClassID);	0
1995	}	---	1995	}	---
1996		---	1996		---
1997	bool AMDGPUOperand::isSDWAOperand(MVT type) const {	0	1997	bool AMDGPUOperand::isSDWAOperand(MVT type) const {	0
1998	if (AsmParser->isVI())	0	1998	if (AsmParser->isVI())	0
1999	return isVReg32();	0	1999	return isVReg32();	0
2000	else if (AsmParser->isGFX9Plus())	0	2000	else if (AsmParser->isGFX9Plus())	0
2001	return isRegClass(AMDGPU::VS_32RegClassID) \|\| isInlinableImm(type);	0	2001	return isRegClass(AMDGPU::VS_32RegClassID) \|\| isInlinableImm(type);	0
2002	else	---	2002	else	---
2003	return false;	0	2003	return false;	0
2004	}	---	2004	}	---
2005		---	2005		---
2006	bool AMDGPUOperand::isSDWAFP16Operand() const {	0	2006	bool AMDGPUOperand::isSDWAFP16Operand() const {	0
2007	return isSDWAOperand(MVT::f16);	0	2007	return isSDWAOperand(MVT::f16);	0
2008	}	---	2008	}	---
2009		---	2009		---
2010	bool AMDGPUOperand::isSDWAFP32Operand() const {	0	2010	bool AMDGPUOperand::isSDWAFP32Operand() const {	0
2011	return isSDWAOperand(MVT::f32);	0	2011	return isSDWAOperand(MVT::f32);	0
2012	}	---	2012	}	---
2013		---	2013		---
2014	bool AMDGPUOperand::isSDWAInt16Operand() const {	0	2014	bool AMDGPUOperand::isSDWAInt16Operand() const {	0
2015	return isSDWAOperand(MVT::i16);	0	2015	return isSDWAOperand(MVT::i16);	0
2016	}	---	2016	}	---
2017		---	2017		---
2018	bool AMDGPUOperand::isSDWAInt32Operand() const {	0	2018	bool AMDGPUOperand::isSDWAInt32Operand() const {	0
2019	return isSDWAOperand(MVT::i32);	0	2019	return isSDWAOperand(MVT::i32);	0
2020	}	---	2020	}	---
2021		---	2021		---
2022	bool AMDGPUOperand::isBoolReg() const {	0	2022	bool AMDGPUOperand::isBoolReg() const {	0
2023	auto FB = AsmParser->getFeatureBits();	0	2023	auto FB = AsmParser->getFeatureBits();	0
2024	return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) \|\|	0	2024	return isReg() && ((FB[AMDGPU::FeatureWavefrontSize64] && isSCSrcB64()) \|\|	0
2025	(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));	0	2025	(FB[AMDGPU::FeatureWavefrontSize32] && isSCSrcB32()));	0
2026	}	---	2026	}	---
2027		---	2027		---
2028	uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const	0	2028	uint64_t AMDGPUOperand::applyInputFPModifiers(uint64_t Val, unsigned Size) const	0
2029	{	---	2029	{	---
2030	assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	0	2030	assert(isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	0
2031	assert(Size == 2 \|\| Size == 4 \|\| Size == 8);	0	2031	assert(Size == 2 \|\| Size == 4 \|\| Size == 8);	0
2032		---	2032		---
2033	const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));	0	2033	const uint64_t FpSignMask = (1ULL << (Size * 8 - 1));	0
2034		---	2034		---
2035	if (Imm.Mods.Abs) {	0	2035	if (Imm.Mods.Abs) {	0
2036	Val &= ~FpSignMask;	0	2036	Val &= ~FpSignMask;	0
2037	}	---	2037	}	---
2038	if (Imm.Mods.Neg) {	0	2038	if (Imm.Mods.Neg) {	0
2039	Val ^= FpSignMask;	0	2039	Val ^= FpSignMask;	0
2040	}	---	2040	}	---
2041		---	2041		---
2042	return Val;	0	2042	return Val;	0
2043	}	---	2043	}	---
2044		---	2044		---
2045	void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {	0	2045	void AMDGPUOperand::addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers) const {	0
2046	if (isExpr()) {	0	2046	if (isExpr()) {	0
2047	Inst.addOperand(MCOperand::createExpr(Expr));	0	2047	Inst.addOperand(MCOperand::createExpr(Expr));	0
2048	return;	0	2048	return;	0
2049	}	---	2049	}	---
2050		---	2050		---
2051	if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),	0	2051	if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),	0
2052	Inst.getNumOperands())) {	---	2052	Inst.getNumOperands())) {	---
2053	addLiteralImmOperand(Inst, Imm.Val,	0	2053	addLiteralImmOperand(Inst, Imm.Val,	0
2054	ApplyModifiers &	0	2054	ApplyModifiers &	0
2055	isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	0	2055	isImmTy(ImmTyNone) && Imm.Mods.hasFPModifiers());	0
2056	} else {	---	2056	} else {	---
2057	assert(!isImmTy(ImmTyNone) \|\| !hasModifiers());	0	2057	assert(!isImmTy(ImmTyNone) \|\| !hasModifiers());	0
2058	Inst.addOperand(MCOperand::createImm(Imm.Val));	0	2058	Inst.addOperand(MCOperand::createImm(Imm.Val));	0
2059	setImmKindNone();	0	2059	setImmKindNone();	0
2060	}	---	2060	}	---
2061	}	---	2061	}	---
2062		---	2062		---
2063	void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {	0	2063	void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyModifiers) const {	0
2064	const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());	0	2064	const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());	0
2065	auto OpNum = Inst.getNumOperands();	0	2065	auto OpNum = Inst.getNumOperands();	0
2066	// Check that this operand accepts literals	---	2066	// Check that this operand accepts literals	---
2067	assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));	0	2067	assert(AMDGPU::isSISrcOperand(InstDesc, OpNum));	0
2068		---	2068		---
2069	if (ApplyModifiers) {	0	2069	if (ApplyModifiers) {	0
2070	assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));	0	2070	assert(AMDGPU::isSISrcFPOperand(InstDesc, OpNum));	0
2071	const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);	0	2071	const unsigned Size = Imm.IsFPImm ? sizeof(double) : getOperandSize(InstDesc, OpNum);	0
2072	Val = applyInputFPModifiers(Val, Size);	0	2072	Val = applyInputFPModifiers(Val, Size);	0
2073	}	---	2073	}	---
2074		---	2074		---
2075	APInt Literal(64, Val);	0	2075	APInt Literal(64, Val);	0
2076	uint8_t OpTy = InstDesc.operands()[OpNum].OperandType;	0	2076	uint8_t OpTy = InstDesc.operands()[OpNum].OperandType;	0
2077		---	2077		---
2078	if (Imm.IsFPImm) { // We got fp literal token	0	2078	if (Imm.IsFPImm) { // We got fp literal token	0
2079	switch (OpTy) {	0	2079	switch (OpTy) {	0
2080	case AMDGPU::OPERAND_REG_IMM_INT64:	0	2080	case AMDGPU::OPERAND_REG_IMM_INT64:	0
2081	case AMDGPU::OPERAND_REG_IMM_FP64:	---	2081	case AMDGPU::OPERAND_REG_IMM_FP64:	---
2082	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	---	2082	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	---
2083	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	---	2083	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	---
2084	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	---	2084	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	---
2085	if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),	0	2085	if (AMDGPU::isInlinableLiteral64(Literal.getZExtValue(),	0
2086	AsmParser->hasInv2PiInlineImm())) {	0	2086	AsmParser->hasInv2PiInlineImm())) {	0
2087	Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));	0	2087	Inst.addOperand(MCOperand::createImm(Literal.getZExtValue()));	0
2088	setImmKindConst();	0	2088	setImmKindConst();	0
2089	return;	0	2089	return;	0
2090	}	---	2090	}	---
2091		---	2091		---
2092	// Non-inlineable	---	2092	// Non-inlineable	---
2093	if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand	0	2093	if (AMDGPU::isSISrcFPOperand(InstDesc, OpNum)) { // Expected 64-bit fp operand	0
2094	// For fp operands we check if low 32 bits are zeros	---	2094	// For fp operands we check if low 32 bits are zeros	---
2095	if (Literal.getLoBits(32) != 0) {	0	2095	if (Literal.getLoBits(32) != 0) {	0
2096	const_cast(AsmParser)->Warning(Inst.getLoc(),	0	2096	const_cast(AsmParser)->Warning(Inst.getLoc(),	0
2097	"Can't encode literal as exact 64-bit floating-point operand. "	---	2097	"Can't encode literal as exact 64-bit floating-point operand. "	---
2098	"Low 32-bits will be set to zero");	---	2098	"Low 32-bits will be set to zero");	---
2099	}	---	2099	}	---
2100		---	2100		---
2101	Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue()));	0	2101	Inst.addOperand(MCOperand::createImm(Literal.lshr(32).getZExtValue()));	0
2102	setImmKindLiteral();	0	2102	setImmKindLiteral();	0
2103	return;	0	2103	return;	0
2104	}	---	2104	}	---
2105		---	2105		---
2106	// We don't allow fp literals in 64-bit integer instructions. It is	---	2106	// We don't allow fp literals in 64-bit integer instructions. It is	---
2107	// unclear how we should encode them. This case should be checked earlier	---	2107	// unclear how we should encode them. This case should be checked earlier	---
2108	// in predicate methods (isLiteralImm())	---	2108	// in predicate methods (isLiteralImm())	---
2109	llvm_unreachable("fp literal in 64-bit integer instruction.");	0	2109	llvm_unreachable("fp literal in 64-bit integer instruction.");	0
2110		---	2110		---
2111	case AMDGPU::OPERAND_REG_IMM_INT32:	0	2111	case AMDGPU::OPERAND_REG_IMM_INT32:	0
2112	case AMDGPU::OPERAND_REG_IMM_FP32:	---	2112	case AMDGPU::OPERAND_REG_IMM_FP32:	---
2113	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	---	2113	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	---
2114	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	---	2114	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	---
2115	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	---	2115	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	---
2116	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	---	2116	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	---
2117	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	---	2117	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	---
2118	case AMDGPU::OPERAND_REG_IMM_INT16:	---	2118	case AMDGPU::OPERAND_REG_IMM_INT16:	---
2119	case AMDGPU::OPERAND_REG_IMM_FP16:	---	2119	case AMDGPU::OPERAND_REG_IMM_FP16:	---
2120	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	---	2120	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	---
2121	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	---	2121	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	---
2122	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	---	2122	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	---
2123	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	---	2123	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	---
2124	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	---	2124	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	---
2125	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	---	2125	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	---
2126	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	---	2126	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	---
2127	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	---	2127	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	---
2128	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	---	2128	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:	---
2129	case AMDGPU::OPERAND_REG_IMM_V2INT16:	---	2129	case AMDGPU::OPERAND_REG_IMM_V2INT16:	---
2130	case AMDGPU::OPERAND_REG_IMM_V2FP16:	---	2130	case AMDGPU::OPERAND_REG_IMM_V2FP16:	---
2131	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	---	2131	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	---
2132	case AMDGPU::OPERAND_REG_IMM_V2FP32:	---	2132	case AMDGPU::OPERAND_REG_IMM_V2FP32:	---
2133	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	---	2133	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	---
2134	case AMDGPU::OPERAND_REG_IMM_V2INT32:	---	2134	case AMDGPU::OPERAND_REG_IMM_V2INT32:	---
2135	case AMDGPU::OPERAND_KIMM32:	---	2135	case AMDGPU::OPERAND_KIMM32:	---
2136	case AMDGPU::OPERAND_KIMM16: {	---	2136	case AMDGPU::OPERAND_KIMM16: {	---
2137	bool lost;	---	2137	bool lost;	---
2138	APFloat FPLiteral(APFloat::IEEEdouble(), Literal);	0	2138	APFloat FPLiteral(APFloat::IEEEdouble(), Literal);	0
2139	// Convert literal to single precision	---	2139	// Convert literal to single precision	---
2140	FPLiteral.convert(*getOpFltSemantics(OpTy),	0	2140	FPLiteral.convert(*getOpFltSemantics(OpTy),	0
2141	APFloat::rmNearestTiesToEven, &lost);	---	2141	APFloat::rmNearestTiesToEven, &lost);	---
2142	// We allow precision lost but not overflow or underflow. This should be	---	2142	// We allow precision lost but not overflow or underflow. This should be	---
2143	// checked earlier in isLiteralImm()	---	2143	// checked earlier in isLiteralImm()	---
2144		---	2144		---
2145	uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();	0	2145	uint64_t ImmVal = FPLiteral.bitcastToAPInt().getZExtValue();	0
2146	Inst.addOperand(MCOperand::createImm(ImmVal));	0	2146	Inst.addOperand(MCOperand::createImm(ImmVal));	0
2147	if (OpTy == AMDGPU::OPERAND_KIMM32 \|\| OpTy == AMDGPU::OPERAND_KIMM16) {	0	2147	if (OpTy == AMDGPU::OPERAND_KIMM32 \|\| OpTy == AMDGPU::OPERAND_KIMM16) {	0
2148	setImmKindMandatoryLiteral();	0	2148	setImmKindMandatoryLiteral();	0
2149	} else {	---	2149	} else {	---
2150	setImmKindLiteral();	0	2150	setImmKindLiteral();	0
2151	}	---	2151	}	---
2152	return;	0	2152	return;	0
2153	}	0	2153	}	0
2154	default:	0	2154	default:	0
2155	llvm_unreachable("invalid operand size");	0	2155	llvm_unreachable("invalid operand size");	0
2156	}	---	2156	}	---
2157		---	2157		---
2158	return;	---	2158	return;	---
2159	}	---	2159	}	---
2160		---	2160		---
2161	// We got int literal token.	---	2161	// We got int literal token.	---
2162	// Only sign extend inline immediates.	---	2162	// Only sign extend inline immediates.	---
2163	switch (OpTy) {	0	2163	switch (OpTy) {	0
2164	case AMDGPU::OPERAND_REG_IMM_INT32:	0	2164	case AMDGPU::OPERAND_REG_IMM_INT32:	0
2165	case AMDGPU::OPERAND_REG_IMM_FP32:	---	2165	case AMDGPU::OPERAND_REG_IMM_FP32:	---
2166	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	---	2166	case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:	---
2167	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	---	2167	case AMDGPU::OPERAND_REG_INLINE_C_INT32:	---
2168	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	---	2168	case AMDGPU::OPERAND_REG_INLINE_C_FP32:	---
2169	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	---	2169	case AMDGPU::OPERAND_REG_INLINE_AC_INT32:	---
2170	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	---	2170	case AMDGPU::OPERAND_REG_INLINE_AC_FP32:	---
2171	case AMDGPU::OPERAND_REG_IMM_V2INT16:	---	2171	case AMDGPU::OPERAND_REG_IMM_V2INT16:	---
2172	case AMDGPU::OPERAND_REG_IMM_V2FP16:	---	2172	case AMDGPU::OPERAND_REG_IMM_V2FP16:	---
2173	case AMDGPU::OPERAND_REG_IMM_V2FP32:	---	2173	case AMDGPU::OPERAND_REG_IMM_V2FP32:	---
2174	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	---	2174	case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:	---
2175	case AMDGPU::OPERAND_REG_IMM_V2INT32:	---	2175	case AMDGPU::OPERAND_REG_IMM_V2INT32:	---
2176	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	---	2176	case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:	---
2177	if (isSafeTruncation(Val, 32) &&	0	2177	if (isSafeTruncation(Val, 32) &&	0
2178	AMDGPU::isInlinableLiteral32(static_cast(Val),	0	2178	AMDGPU::isInlinableLiteral32(static_cast(Val),	0
2179	AsmParser->hasInv2PiInlineImm())) {	0	2179	AsmParser->hasInv2PiInlineImm())) {	0
2180	Inst.addOperand(MCOperand::createImm(Val));	0	2180	Inst.addOperand(MCOperand::createImm(Val));	0
2181	setImmKindConst();	0	2181	setImmKindConst();	0
2182	return;	0	2182	return;	0
2183	}	---	2183	}	---
2184		---	2184		---
2185	Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));	0	2185	Inst.addOperand(MCOperand::createImm(Val & 0xffffffff));	0
2186	setImmKindLiteral();	0	2186	setImmKindLiteral();	0
2187	return;	0	2187	return;	0
2188		---	2188		---
2189	case AMDGPU::OPERAND_REG_IMM_INT64:	0	2189	case AMDGPU::OPERAND_REG_IMM_INT64:	0
2190	case AMDGPU::OPERAND_REG_IMM_FP64:	---	2190	case AMDGPU::OPERAND_REG_IMM_FP64:	---
2191	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	---	2191	case AMDGPU::OPERAND_REG_INLINE_C_INT64:	---
2192	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	---	2192	case AMDGPU::OPERAND_REG_INLINE_C_FP64:	---
2193	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	---	2193	case AMDGPU::OPERAND_REG_INLINE_AC_FP64:	---
2194	if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {	0	2194	if (AMDGPU::isInlinableLiteral64(Val, AsmParser->hasInv2PiInlineImm())) {	0
2195	Inst.addOperand(MCOperand::createImm(Val));	0	2195	Inst.addOperand(MCOperand::createImm(Val));	0
2196	setImmKindConst();	0	2196	setImmKindConst();	0
2197	return;	0	2197	return;	0
2198	}	---	2198	}	---
2199		---	2199		---
2200	Inst.addOperand(MCOperand::createImm(Lo_32(Val)));	0	2200	Inst.addOperand(MCOperand::createImm(Lo_32(Val)));	0
2201	setImmKindLiteral();	0	2201	setImmKindLiteral();	0
2202	return;	0	2202	return;	0
2203		---	2203		---
2204	case AMDGPU::OPERAND_REG_IMM_INT16:	0	2204	case AMDGPU::OPERAND_REG_IMM_INT16:	0
2205	case AMDGPU::OPERAND_REG_IMM_FP16:	---	2205	case AMDGPU::OPERAND_REG_IMM_FP16:	---
2206	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	---	2206	case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:	---
2207	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	---	2207	case AMDGPU::OPERAND_REG_INLINE_C_INT16:	---
2208	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	---	2208	case AMDGPU::OPERAND_REG_INLINE_C_FP16:	---
2209	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	---	2209	case AMDGPU::OPERAND_REG_INLINE_AC_INT16:	---
2210	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	---	2210	case AMDGPU::OPERAND_REG_INLINE_AC_FP16:	---
2211	if (isSafeTruncation(Val, 16) &&	0	2211	if (isSafeTruncation(Val, 16) &&	0
2212	AMDGPU::isInlinableLiteral16(static_cast(Val),	0	2212	AMDGPU::isInlinableLiteral16(static_cast(Val),	0
2213	AsmParser->hasInv2PiInlineImm())) {	0	2213	AsmParser->hasInv2PiInlineImm())) {	0
2214	Inst.addOperand(MCOperand::createImm(Val));	0	2214	Inst.addOperand(MCOperand::createImm(Val));	0
2215	setImmKindConst();	0	2215	setImmKindConst();	0
2216	return;	0	2216	return;	0
2217	}	---	2217	}	---
2218		---	2218		---
2219	Inst.addOperand(MCOperand::createImm(Val & 0xffff));	0	2219	Inst.addOperand(MCOperand::createImm(Val & 0xffff));	0
2220	setImmKindLiteral();	0	2220	setImmKindLiteral();	0
2221	return;	0	2221	return;	0
2222		---	2222		---
2223	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	0	2223	case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:	0
2224	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	---	2224	case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:	---
2225	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	---	2225	case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:	---
2226	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {	---	2226	case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16: {	---
2227	assert(isSafeTruncation(Val, 16));	0	2227	assert(isSafeTruncation(Val, 16));	0
2228	assert(AMDGPU::isInlinableLiteral16(static_cast(Val),	0	2228	assert(AMDGPU::isInlinableLiteral16(static_cast(Val),	0
2229	AsmParser->hasInv2PiInlineImm()));	---	2229	AsmParser->hasInv2PiInlineImm()));	---
2230		---	2230		---
2231	Inst.addOperand(MCOperand::createImm(Val));	0	2231	Inst.addOperand(MCOperand::createImm(Val));	0
2232	return;	0	2232	return;	0
2233	}	---	2233	}	---
2234	case AMDGPU::OPERAND_KIMM32:	0	2234	case AMDGPU::OPERAND_KIMM32:	0
2235	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));	0	2235	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));	0
2236	setImmKindMandatoryLiteral();	0	2236	setImmKindMandatoryLiteral();	0
2237	return;	0	2237	return;	0
2238	case AMDGPU::OPERAND_KIMM16:	0	2238	case AMDGPU::OPERAND_KIMM16:	0
2239	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));	0	2239	Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));	0
2240	setImmKindMandatoryLiteral();	0	2240	setImmKindMandatoryLiteral();	0
2241	return;	0	2241	return;	0
2242	default:	0	2242	default:	0
2243	llvm_unreachable("invalid operand size");	0	2243	llvm_unreachable("invalid operand size");	0
2244	}	---	2244	}	---
2245	}	0	2245	}	0
2246		---	2246		---
2247	void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {	0	2247	void AMDGPUOperand::addRegOperands(MCInst &Inst, unsigned N) const {	0
2248	Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));	0	2248	Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(getReg(), AsmParser->getSTI())));	0
2249	}	0	2249	}	0
2250		---	2250		---
2251	bool AMDGPUOperand::isInlineValue() const {	0	2251	bool AMDGPUOperand::isInlineValue() const {	0
2252	return isRegKind() && ::isInlineValue(getReg());	0	2252	return isRegKind() && ::isInlineValue(getReg());	0
2253	}	---	2253	}	---
2254		---	2254		---
2255	//===----------------------------------------------------------------------===//	---	2255	//===----------------------------------------------------------------------===//	---
2256	// AsmParser	---	2256	// AsmParser	---
2257	//===----------------------------------------------------------------------===//	---	2257	//===----------------------------------------------------------------------===//	---
2258		---	2258		---
2259	static int getRegClass(RegisterKind Is, unsigned RegWidth) {	0	2259	static int getRegClass(RegisterKind Is, unsigned RegWidth) {	0
2260	if (Is == IS_VGPR) {	0	2260	if (Is == IS_VGPR) {	0
2261	switch (RegWidth) {	0	2261	switch (RegWidth) {	0
2262	default: return -1;	0	2262	default: return -1;	0
2263	case 32:	0	2263	case 32:	0
2264	return AMDGPU::VGPR_32RegClassID;	0	2264	return AMDGPU::VGPR_32RegClassID;	0
2265	case 64:	0	2265	case 64:	0
2266	return AMDGPU::VReg_64RegClassID;	0	2266	return AMDGPU::VReg_64RegClassID;	0
2267	case 96:	0	2267	case 96:	0
2268	return AMDGPU::VReg_96RegClassID;	0	2268	return AMDGPU::VReg_96RegClassID;	0
2269	case 128:	0	2269	case 128:	0
2270	return AMDGPU::VReg_128RegClassID;	0	2270	return AMDGPU::VReg_128RegClassID;	0
2271	case 160:	0	2271	case 160:	0
2272	return AMDGPU::VReg_160RegClassID;	0	2272	return AMDGPU::VReg_160RegClassID;	0
2273	case 192:	0	2273	case 192:	0
2274	return AMDGPU::VReg_192RegClassID;	0	2274	return AMDGPU::VReg_192RegClassID;	0
2275	case 224:	0	2275	case 224:	0
2276	return AMDGPU::VReg_224RegClassID;	0	2276	return AMDGPU::VReg_224RegClassID;	0
2277	case 256:	0	2277	case 256:	0
2278	return AMDGPU::VReg_256RegClassID;	0	2278	return AMDGPU::VReg_256RegClassID;	0
2279	case 288:	0	2279	case 288:	0
2280	return AMDGPU::VReg_288RegClassID;	0	2280	return AMDGPU::VReg_288RegClassID;	0
2281	case 320:	0	2281	case 320:	0
2282	return AMDGPU::VReg_320RegClassID;	0	2282	return AMDGPU::VReg_320RegClassID;	0
2283	case 352:	0	2283	case 352:	0
2284	return AMDGPU::VReg_352RegClassID;	0	2284	return AMDGPU::VReg_352RegClassID;	0
2285	case 384:	0	2285	case 384:	0
2286	return AMDGPU::VReg_384RegClassID;	0	2286	return AMDGPU::VReg_384RegClassID;	0
2287	case 512:	0	2287	case 512:	0
2288	return AMDGPU::VReg_512RegClassID;	0	2288	return AMDGPU::VReg_512RegClassID;	0
2289	case 1024:	0	2289	case 1024:	0
2290	return AMDGPU::VReg_1024RegClassID;	0	2290	return AMDGPU::VReg_1024RegClassID;	0
2291	}	---	2291	}	---
2292	} else if (Is == IS_TTMP) {	0	2292	} else if (Is == IS_TTMP) {	0
2293	switch (RegWidth) {	0	2293	switch (RegWidth) {	0
2294	default: return -1;	0	2294	default: return -1;	0
2295	case 32:	0	2295	case 32:	0
2296	return AMDGPU::TTMP_32RegClassID;	0	2296	return AMDGPU::TTMP_32RegClassID;	0
2297	case 64:	0	2297	case 64:	0
2298	return AMDGPU::TTMP_64RegClassID;	0	2298	return AMDGPU::TTMP_64RegClassID;	0
2299	case 128:	0	2299	case 128:	0
2300	return AMDGPU::TTMP_128RegClassID;	0	2300	return AMDGPU::TTMP_128RegClassID;	0
2301	case 256:	0	2301	case 256:	0
2302	return AMDGPU::TTMP_256RegClassID;	0	2302	return AMDGPU::TTMP_256RegClassID;	0
2303	case 512:	0	2303	case 512:	0
2304	return AMDGPU::TTMP_512RegClassID;	0	2304	return AMDGPU::TTMP_512RegClassID;	0
2305	}	---	2305	}	---
2306	} else if (Is == IS_SGPR) {	0	2306	} else if (Is == IS_SGPR) {	0
2307	switch (RegWidth) {	0	2307	switch (RegWidth) {	0
2308	default: return -1;	0	2308	default: return -1;	0
2309	case 32:	0	2309	case 32:	0
2310	return AMDGPU::SGPR_32RegClassID;	0	2310	return AMDGPU::SGPR_32RegClassID;	0
2311	case 64:	0	2311	case 64:	0
2312	return AMDGPU::SGPR_64RegClassID;	0	2312	return AMDGPU::SGPR_64RegClassID;	0
2313	case 96:	0	2313	case 96:	0
2314	return AMDGPU::SGPR_96RegClassID;	0	2314	return AMDGPU::SGPR_96RegClassID;	0
2315	case 128:	0	2315	case 128:	0
2316	return AMDGPU::SGPR_128RegClassID;	0	2316	return AMDGPU::SGPR_128RegClassID;	0
2317	case 160:	0	2317	case 160:	0
2318	return AMDGPU::SGPR_160RegClassID;	0	2318	return AMDGPU::SGPR_160RegClassID;	0
2319	case 192:	0	2319	case 192:	0
2320	return AMDGPU::SGPR_192RegClassID;	0	2320	return AMDGPU::SGPR_192RegClassID;	0
2321	case 224:	0	2321	case 224:	0
2322	return AMDGPU::SGPR_224RegClassID;	0	2322	return AMDGPU::SGPR_224RegClassID;	0
2323	case 256:	0	2323	case 256:	0
2324	return AMDGPU::SGPR_256RegClassID;	0	2324	return AMDGPU::SGPR_256RegClassID;	0
2325	case 288:	0	2325	case 288:	0
2326	return AMDGPU::SGPR_288RegClassID;	0	2326	return AMDGPU::SGPR_288RegClassID;	0
2327	case 320:	0	2327	case 320:	0
2328	return AMDGPU::SGPR_320RegClassID;	0	2328	return AMDGPU::SGPR_320RegClassID;	0
2329	case 352:	0	2329	case 352:	0
2330	return AMDGPU::SGPR_352RegClassID;	0	2330	return AMDGPU::SGPR_352RegClassID;	0
2331	case 384:	0	2331	case 384:	0
2332	return AMDGPU::SGPR_384RegClassID;	0	2332	return AMDGPU::SGPR_384RegClassID;	0
2333	case 512:	0	2333	case 512:	0
2334	return AMDGPU::SGPR_512RegClassID;	0	2334	return AMDGPU::SGPR_512RegClassID;	0
2335	}	---	2335	}	---
2336	} else if (Is == IS_AGPR) {	0	2336	} else if (Is == IS_AGPR) {	0
2337	switch (RegWidth) {	0	2337	switch (RegWidth) {	0
2338	default: return -1;	0	2338	default: return -1;	0
2339	case 32:	0	2339	case 32:	0
2340	return AMDGPU::AGPR_32RegClassID;	0	2340	return AMDGPU::AGPR_32RegClassID;	0
2341	case 64:	0	2341	case 64:	0
2342	return AMDGPU::AReg_64RegClassID;	0	2342	return AMDGPU::AReg_64RegClassID;	0
2343	case 96:	0	2343	case 96:	0
2344	return AMDGPU::AReg_96RegClassID;	0	2344	return AMDGPU::AReg_96RegClassID;	0
2345	case 128:	0	2345	case 128:	0
2346	return AMDGPU::AReg_128RegClassID;	0	2346	return AMDGPU::AReg_128RegClassID;	0
2347	case 160:	0	2347	case 160:	0
2348	return AMDGPU::AReg_160RegClassID;	0	2348	return AMDGPU::AReg_160RegClassID;	0
2349	case 192:	0	2349	case 192:	0
2350	return AMDGPU::AReg_192RegClassID;	0	2350	return AMDGPU::AReg_192RegClassID;	0
2351	case 224:	0	2351	case 224:	0
2352	return AMDGPU::AReg_224RegClassID;	0	2352	return AMDGPU::AReg_224RegClassID;	0
2353	case 256:	0	2353	case 256:	0
2354	return AMDGPU::AReg_256RegClassID;	0	2354	return AMDGPU::AReg_256RegClassID;	0
2355	case 288:	0	2355	case 288:	0
2356	return AMDGPU::AReg_288RegClassID;	0	2356	return AMDGPU::AReg_288RegClassID;	0
2357	case 320:	0	2357	case 320:	0
2358	return AMDGPU::AReg_320RegClassID;	0	2358	return AMDGPU::AReg_320RegClassID;	0
2359	case 352:	0	2359	case 352:	0
2360	return AMDGPU::AReg_352RegClassID;	0	2360	return AMDGPU::AReg_352RegClassID;	0
2361	case 384:	0	2361	case 384:	0
2362	return AMDGPU::AReg_384RegClassID;	0	2362	return AMDGPU::AReg_384RegClassID;	0
2363	case 512:	0	2363	case 512:	0
2364	return AMDGPU::AReg_512RegClassID;	0	2364	return AMDGPU::AReg_512RegClassID;	0
2365	case 1024:	0	2365	case 1024:	0
2366	return AMDGPU::AReg_1024RegClassID;	0	2366	return AMDGPU::AReg_1024RegClassID;	0
2367	}	---	2367	}	---
2368	}	---	2368	}	---
2369	return -1;	0	2369	return -1;	0
2370	}	---	2370	}	---
2371		---	2371		---
2372	static unsigned getSpecialRegForName(StringRef RegName) {	0	2372	static unsigned getSpecialRegForName(StringRef RegName) {	0
2373	return StringSwitch(RegName)	0	2373	return StringSwitch(RegName)	0
2374	.Case("exec", AMDGPU::EXEC)	0	2374	.Case("exec", AMDGPU::EXEC)	0
2375	.Case("vcc", AMDGPU::VCC)	0	2375	.Case("vcc", AMDGPU::VCC)	0
2376	.Case("flat_scratch", AMDGPU::FLAT_SCR)	0	2376	.Case("flat_scratch", AMDGPU::FLAT_SCR)	0
2377	.Case("xnack_mask", AMDGPU::XNACK_MASK)	0	2377	.Case("xnack_mask", AMDGPU::XNACK_MASK)	0
2378	.Case("shared_base", AMDGPU::SRC_SHARED_BASE)	0	2378	.Case("shared_base", AMDGPU::SRC_SHARED_BASE)	0
2379	.Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)	0	2379	.Case("src_shared_base", AMDGPU::SRC_SHARED_BASE)	0
2380	.Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT)	0	2380	.Case("shared_limit", AMDGPU::SRC_SHARED_LIMIT)	0
2381	.Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)	0	2381	.Case("src_shared_limit", AMDGPU::SRC_SHARED_LIMIT)	0
2382	.Case("private_base", AMDGPU::SRC_PRIVATE_BASE)	0	2382	.Case("private_base", AMDGPU::SRC_PRIVATE_BASE)	0
2383	.Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)	0	2383	.Case("src_private_base", AMDGPU::SRC_PRIVATE_BASE)	0
2384	.Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	0	2384	.Case("private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	0
2385	.Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	0	2385	.Case("src_private_limit", AMDGPU::SRC_PRIVATE_LIMIT)	0
2386	.Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	0	2386	.Case("pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	0
2387	.Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	0	2387	.Case("src_pops_exiting_wave_id", AMDGPU::SRC_POPS_EXITING_WAVE_ID)	0
2388	.Case("lds_direct", AMDGPU::LDS_DIRECT)	0	2388	.Case("lds_direct", AMDGPU::LDS_DIRECT)	0
2389	.Case("src_lds_direct", AMDGPU::LDS_DIRECT)	0	2389	.Case("src_lds_direct", AMDGPU::LDS_DIRECT)	0
2390	.Case("m0", AMDGPU::M0)	0	2390	.Case("m0", AMDGPU::M0)	0
2391	.Case("vccz", AMDGPU::SRC_VCCZ)	0	2391	.Case("vccz", AMDGPU::SRC_VCCZ)	0
2392	.Case("src_vccz", AMDGPU::SRC_VCCZ)	0	2392	.Case("src_vccz", AMDGPU::SRC_VCCZ)	0
2393	.Case("execz", AMDGPU::SRC_EXECZ)	0	2393	.Case("execz", AMDGPU::SRC_EXECZ)	0
2394	.Case("src_execz", AMDGPU::SRC_EXECZ)	0	2394	.Case("src_execz", AMDGPU::SRC_EXECZ)	0
2395	.Case("scc", AMDGPU::SRC_SCC)	0	2395	.Case("scc", AMDGPU::SRC_SCC)	0
2396	.Case("src_scc", AMDGPU::SRC_SCC)	0	2396	.Case("src_scc", AMDGPU::SRC_SCC)	0
2397	.Case("tba", AMDGPU::TBA)	0	2397	.Case("tba", AMDGPU::TBA)	0
2398	.Case("tma", AMDGPU::TMA)	0	2398	.Case("tma", AMDGPU::TMA)	0
2399	.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)	0	2399	.Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)	0
2400	.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)	0	2400	.Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)	0
2401	.Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)	0	2401	.Case("xnack_mask_lo", AMDGPU::XNACK_MASK_LO)	0
2402	.Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)	0	2402	.Case("xnack_mask_hi", AMDGPU::XNACK_MASK_HI)	0
2403	.Case("vcc_lo", AMDGPU::VCC_LO)	0	2403	.Case("vcc_lo", AMDGPU::VCC_LO)	0
2404	.Case("vcc_hi", AMDGPU::VCC_HI)	0	2404	.Case("vcc_hi", AMDGPU::VCC_HI)	0
2405	.Case("exec_lo", AMDGPU::EXEC_LO)	0	2405	.Case("exec_lo", AMDGPU::EXEC_LO)	0
2406	.Case("exec_hi", AMDGPU::EXEC_HI)	0	2406	.Case("exec_hi", AMDGPU::EXEC_HI)	0
2407	.Case("tma_lo", AMDGPU::TMA_LO)	0	2407	.Case("tma_lo", AMDGPU::TMA_LO)	0
2408	.Case("tma_hi", AMDGPU::TMA_HI)	0	2408	.Case("tma_hi", AMDGPU::TMA_HI)	0
2409	.Case("tba_lo", AMDGPU::TBA_LO)	0	2409	.Case("tba_lo", AMDGPU::TBA_LO)	0
2410	.Case("tba_hi", AMDGPU::TBA_HI)	0	2410	.Case("tba_hi", AMDGPU::TBA_HI)	0
2411	.Case("pc", AMDGPU::PC_REG)	0	2411	.Case("pc", AMDGPU::PC_REG)	0
2412	.Case("null", AMDGPU::SGPR_NULL)	0	2412	.Case("null", AMDGPU::SGPR_NULL)	0
2413	.Default(AMDGPU::NoRegister);	0	2413	.Default(AMDGPU::NoRegister);	0
2414	}	---	2414	}	---
2415		---	2415		---
2416	bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	0	2416	bool AMDGPUAsmParser::ParseRegister(MCRegister &RegNo, SMLoc &StartLoc,	0
2417	SMLoc &EndLoc, bool RestoreOnFailure) {	---	2417	SMLoc &EndLoc, bool RestoreOnFailure) {	---
2418	auto R = parseRegister();	0	2418	auto R = parseRegister();	0
2419	if (!R) return true;	0	2419	if (!R) return true;	0
2420	assert(R->isReg());	0	2420	assert(R->isReg());	0
2421	RegNo = R->getReg();	0	2421	RegNo = R->getReg();	0
2422	StartLoc = R->getStartLoc();	0	2422	StartLoc = R->getStartLoc();	0
2423	EndLoc = R->getEndLoc();	0	2423	EndLoc = R->getEndLoc();	0
2424	return false;	0	2424	return false;	0
2425	}	0	2425	}	0
2426		---	2426		---
2427	bool AMDGPUAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	0	2427	bool AMDGPUAsmParser::parseRegister(MCRegister &RegNo, SMLoc &StartLoc,	0
2428	SMLoc &EndLoc) {	---	2428	SMLoc &EndLoc) {	---
2429	return ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/false);	0	2429	return ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/false);	0
2430	}	---	2430	}	---
2431		---	2431		---
2432	OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(MCRegister &RegNo,	0	2432	OperandMatchResultTy AMDGPUAsmParser::tryParseRegister(MCRegister &RegNo,	0
2433	SMLoc &StartLoc,	---	2433	SMLoc &StartLoc,	---
2434	SMLoc &EndLoc) {	---	2434	SMLoc &EndLoc) {	---
2435	bool Result =	---	2435	bool Result =	---
2436	ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/true);	0	2436	ParseRegister(RegNo, StartLoc, EndLoc, /RestoreOnFailure=/true);	0
2437	bool PendingErrors = getParser().hasPendingError();	0	2437	bool PendingErrors = getParser().hasPendingError();	0
2438	getParser().clearPendingErrors();	0	2438	getParser().clearPendingErrors();	0
2439	if (PendingErrors)	0	2439	if (PendingErrors)	0
2440	return MatchOperand_ParseFail;	0	2440	return MatchOperand_ParseFail;	0
2441	if (Result)	0	2441	if (Result)	0
2442	return MatchOperand_NoMatch;	0	2442	return MatchOperand_NoMatch;	0
2443	return MatchOperand_Success;	0	2443	return MatchOperand_Success;	0
2444	}	---	2444	}	---
2445		---	2445		---
2446	bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,	0	2446	bool AMDGPUAsmParser::AddNextRegisterToList(unsigned &Reg, unsigned &RegWidth,	0
2447	RegisterKind RegKind, unsigned Reg1,	---	2447	RegisterKind RegKind, unsigned Reg1,	---
2448	SMLoc Loc) {	---	2448	SMLoc Loc) {	---
2449	switch (RegKind) {	0	2449	switch (RegKind) {	0
2450	case IS_SPECIAL:	0	2450	case IS_SPECIAL:	0
2451	if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {	0	2451	if (Reg == AMDGPU::EXEC_LO && Reg1 == AMDGPU::EXEC_HI) {	0
2452	Reg = AMDGPU::EXEC;	0	2452	Reg = AMDGPU::EXEC;	0
2453	RegWidth = 64;	0	2453	RegWidth = 64;	0
2454	return true;	0	2454	return true;	0
2455	}	---	2455	}	---
2456	if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {	0	2456	if (Reg == AMDGPU::FLAT_SCR_LO && Reg1 == AMDGPU::FLAT_SCR_HI) {	0
2457	Reg = AMDGPU::FLAT_SCR;	0	2457	Reg = AMDGPU::FLAT_SCR;	0
2458	RegWidth = 64;	0	2458	RegWidth = 64;	0
2459	return true;	0	2459	return true;	0
2460	}	---	2460	}	---
2461	if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {	0	2461	if (Reg == AMDGPU::XNACK_MASK_LO && Reg1 == AMDGPU::XNACK_MASK_HI) {	0
2462	Reg = AMDGPU::XNACK_MASK;	0	2462	Reg = AMDGPU::XNACK_MASK;	0
2463	RegWidth = 64;	0	2463	RegWidth = 64;	0
2464	return true;	0	2464	return true;	0
2465	}	---	2465	}	---
2466	if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {	0	2466	if (Reg == AMDGPU::VCC_LO && Reg1 == AMDGPU::VCC_HI) {	0
2467	Reg = AMDGPU::VCC;	0	2467	Reg = AMDGPU::VCC;	0
2468	RegWidth = 64;	0	2468	RegWidth = 64;	0
2469	return true;	0	2469	return true;	0
2470	}	---	2470	}	---
2471	if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {	0	2471	if (Reg == AMDGPU::TBA_LO && Reg1 == AMDGPU::TBA_HI) {	0
2472	Reg = AMDGPU::TBA;	0	2472	Reg = AMDGPU::TBA;	0
2473	RegWidth = 64;	0	2473	RegWidth = 64;	0
2474	return true;	0	2474	return true;	0
2475	}	---	2475	}	---
2476	if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {	0	2476	if (Reg == AMDGPU::TMA_LO && Reg1 == AMDGPU::TMA_HI) {	0
2477	Reg = AMDGPU::TMA;	0	2477	Reg = AMDGPU::TMA;	0
2478	RegWidth = 64;	0	2478	RegWidth = 64;	0
2479	return true;	0	2479	return true;	0
2480	}	---	2480	}	---
2481	Error(Loc, "register does not fit in the list");	0	2481	Error(Loc, "register does not fit in the list");	0
2482	return false;	0	2482	return false;	0
2483	case IS_VGPR:	0	2483	case IS_VGPR:	0
2484	case IS_SGPR:	---	2484	case IS_SGPR:	---
2485	case IS_AGPR:	---	2485	case IS_AGPR:	---
2486	case IS_TTMP:	---	2486	case IS_TTMP:	---
2487	if (Reg1 != Reg + RegWidth / 32) {	0	2487	if (Reg1 != Reg + RegWidth / 32) {	0
2488	Error(Loc, "registers in a list must have consecutive indices");	0	2488	Error(Loc, "registers in a list must have consecutive indices");	0
2489	return false;	0	2489	return false;	0
2490	}	---	2490	}	---
2491	RegWidth += 32;	0	2491	RegWidth += 32;	0
2492	return true;	0	2492	return true;	0
2493	default:	0	2493	default:	0
2494	llvm_unreachable("unexpected register kind");	0	2494	llvm_unreachable("unexpected register kind");	0
2495	}	---	2495	}	---
2496	}	---	2496	}	---
2497		---	2497		---
2498	struct RegInfo {	---	2498	struct RegInfo {	---
2499	StringLiteral Name;	---	2499	StringLiteral Name;	---
2500	RegisterKind Kind;	---	2500	RegisterKind Kind;	---
2501	};	---	2501	};	---
2502		---	2502		---
2503	static constexpr RegInfo RegularRegisters[] = {	---	2503	static constexpr RegInfo RegularRegisters[] = {	---
2504	{{"v"}, IS_VGPR},	---	2504	{{"v"}, IS_VGPR},	---
2505	{{"s"}, IS_SGPR},	---	2505	{{"s"}, IS_SGPR},	---
2506	{{"ttmp"}, IS_TTMP},	---	2506	{{"ttmp"}, IS_TTMP},	---
2507	{{"acc"}, IS_AGPR},	---	2507	{{"acc"}, IS_AGPR},	---
2508	{{"a"}, IS_AGPR},	---	2508	{{"a"}, IS_AGPR},	---
2509	};	---	2509	};	---
2510		---	2510		---
2511	static bool isRegularReg(RegisterKind Kind) {	0	2511	static bool isRegularReg(RegisterKind Kind) {	0
2512	return Kind == IS_VGPR \|\|	0	2512	return Kind == IS_VGPR \|\|	0
2513	Kind == IS_SGPR \|\|	0	2513	Kind == IS_SGPR \|\|	0
2514	Kind == IS_TTMP \|\|	0	2514	Kind == IS_TTMP \|\|	0
2515	Kind == IS_AGPR;	0	2515	Kind == IS_AGPR;	0
2516	}	---	2516	}	---
2517		---	2517		---
2518	static const RegInfo* getRegularRegInfo(StringRef Str) {	0	2518	static const RegInfo* getRegularRegInfo(StringRef Str) {	0
2519	for (const RegInfo &Reg : RegularRegisters)	0	2519	for (const RegInfo &Reg : RegularRegisters)	0
2520	if (Str.startswith(Reg.Name))	0	2520	if (Str.startswith(Reg.Name))	0
2521	return &Reg;	0	2521	return &Reg;	0
2522	return nullptr;	0	2522	return nullptr;	0
2523	}	---	2523	}	---
2524		---	2524		---
2525	static bool getRegNum(StringRef Str, unsigned& Num) {	0	2525	static bool getRegNum(StringRef Str, unsigned& Num) {	0
2526	return !Str.getAsInteger(10, Num);	0	2526	return !Str.getAsInteger(10, Num);	0
2527	}	---	2527	}	---
2528		---	2528		---
2529	bool	---	2529	bool	---
2530	AMDGPUAsmParser::isRegister(const AsmToken &Token,	0	2530	AMDGPUAsmParser::isRegister(const AsmToken &Token,	0
2531	const AsmToken &NextToken) const {	---	2531	const AsmToken &NextToken) const {	---
2532		---	2532		---
2533	// A list of consecutive registers: [s0,s1,s2,s3]	---	2533	// A list of consecutive registers: [s0,s1,s2,s3]	---
2534	if (Token.is(AsmToken::LBrac))	0	2534	if (Token.is(AsmToken::LBrac))	0
2535	return true;	0	2535	return true;	0
2536		---	2536		---
2537	if (!Token.is(AsmToken::Identifier))	0	2537	if (!Token.is(AsmToken::Identifier))	0
2538	return false;	0	2538	return false;	0
2539		---	2539		---
2540	// A single register like s0 or a range of registers like s[0:1]	---	2540	// A single register like s0 or a range of registers like s[0:1]	---
2541		---	2541		---
2542	StringRef Str = Token.getString();	0	2542	StringRef Str = Token.getString();	0
2543	const RegInfo *Reg = getRegularRegInfo(Str);	0	2543	const RegInfo *Reg = getRegularRegInfo(Str);	0
2544	if (Reg) {	0	2544	if (Reg) {	0
2545	StringRef RegName = Reg->Name;	0	2545	StringRef RegName = Reg->Name;	0
2546	StringRef RegSuffix = Str.substr(RegName.size());	0	2546	StringRef RegSuffix = Str.substr(RegName.size());	0
2547	if (!RegSuffix.empty()) {	0	2547	if (!RegSuffix.empty()) {	0
2548	unsigned Num;	---	2548	unsigned Num;	---
2549	// A single register with an index: rXX	---	2549	// A single register with an index: rXX	---
2550	if (getRegNum(RegSuffix, Num))	0	2550	if (getRegNum(RegSuffix, Num))	0
2551	return true;	0	2551	return true;	0
2552	} else {	---	2552	} else {	---
2553	// A range of registers: r[XX:YY].	---	2553	// A range of registers: r[XX:YY].	---
2554	if (NextToken.is(AsmToken::LBrac))	0	2554	if (NextToken.is(AsmToken::LBrac))	0
2555	return true;	0	2555	return true;	0
2556	}	---	2556	}	---
2557	}	---	2557	}	---
2558		---	2558		---
2559	return getSpecialRegForName(Str) != AMDGPU::NoRegister;	0	2559	return getSpecialRegForName(Str) != AMDGPU::NoRegister;	0
2560	}	---	2560	}	---
2561		---	2561		---
2562	bool	---	2562	bool	---
2563	AMDGPUAsmParser::isRegister()	0	2563	AMDGPUAsmParser::isRegister()	0
2564	{	---	2564	{	---
2565	return isRegister(getToken(), peekToken());	0	2565	return isRegister(getToken(), peekToken());	0
2566	}	---	2566	}	---
2567		---	2567		---
2568	unsigned	---	2568	unsigned	---
2569	AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,	0	2569	AMDGPUAsmParser::getRegularReg(RegisterKind RegKind,	0
2570	unsigned RegNum,	---	2570	unsigned RegNum,	---
2571	unsigned RegWidth,	---	2571	unsigned RegWidth,	---
2572	SMLoc Loc) {	---	2572	SMLoc Loc) {	---
2573		---	2573		---
2574	assert(isRegularReg(RegKind));	0	2574	assert(isRegularReg(RegKind));	0
2575		---	2575		---
2576	unsigned AlignSize = 1;	0	2576	unsigned AlignSize = 1;	0
2577	if (RegKind == IS_SGPR \|\| RegKind == IS_TTMP) {	0	2577	if (RegKind == IS_SGPR \|\| RegKind == IS_TTMP) {	0
2578	// SGPR and TTMP registers must be aligned.	---	2578	// SGPR and TTMP registers must be aligned.	---
2579	// Max required alignment is 4 dwords.	---	2579	// Max required alignment is 4 dwords.	---
2580	AlignSize = std::min(RegWidth / 32, 4u);	0	2580	AlignSize = std::min(RegWidth / 32, 4u);	0
2581	}	---	2581	}	---
2582		---	2582		---
2583	if (RegNum % AlignSize != 0) {	0	2583	if (RegNum % AlignSize != 0) {	0
2584	Error(Loc, "invalid register alignment");	0	2584	Error(Loc, "invalid register alignment");	0
2585	return AMDGPU::NoRegister;	0	2585	return AMDGPU::NoRegister;	0
2586	}	---	2586	}	---
2587		---	2587		---
2588	unsigned RegIdx = RegNum / AlignSize;	0	2588	unsigned RegIdx = RegNum / AlignSize;	0
2589	int RCID = getRegClass(RegKind, RegWidth);	0	2589	int RCID = getRegClass(RegKind, RegWidth);	0
2590	if (RCID == -1) {	0	2590	if (RCID == -1) {	0
2591	Error(Loc, "invalid or unsupported register size");	0	2591	Error(Loc, "invalid or unsupported register size");	0
2592	return AMDGPU::NoRegister;	0	2592	return AMDGPU::NoRegister;	0
2593	}	---	2593	}	---
2594		---	2594		---
2595	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	2595	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
2596	const MCRegisterClass RC = TRI->getRegClass(RCID);	0	2596	const MCRegisterClass RC = TRI->getRegClass(RCID);	0
2597	if (RegIdx >= RC.getNumRegs()) {	0	2597	if (RegIdx >= RC.getNumRegs()) {	0
2598	Error(Loc, "register index is out of range");	0	2598	Error(Loc, "register index is out of range");	0
2599	return AMDGPU::NoRegister;	0	2599	return AMDGPU::NoRegister;	0
2600	}	---	2600	}	---
2601		---	2601		---
2602	return RC.getRegister(RegIdx);	0	2602	return RC.getRegister(RegIdx);	0
2603	}	---	2603	}	---
2604		---	2604		---
2605	bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {	0	2605	bool AMDGPUAsmParser::ParseRegRange(unsigned &Num, unsigned &RegWidth) {	0
2606	int64_t RegLo, RegHi;	---	2606	int64_t RegLo, RegHi;	---
2607	if (!skipToken(AsmToken::LBrac, "missing register index"))	0	2607	if (!skipToken(AsmToken::LBrac, "missing register index"))	0
2608	return false;	0	2608	return false;	0
2609		---	2609		---
2610	SMLoc FirstIdxLoc = getLoc();	0	2610	SMLoc FirstIdxLoc = getLoc();	0
2611	SMLoc SecondIdxLoc;	0	2611	SMLoc SecondIdxLoc;	0
2612		---	2612		---
2613	if (!parseExpr(RegLo))	0	2613	if (!parseExpr(RegLo))	0
2614	return false;	0	2614	return false;	0
2615		---	2615		---
2616	if (trySkipToken(AsmToken::Colon)) {	0	2616	if (trySkipToken(AsmToken::Colon)) {	0
2617	SecondIdxLoc = getLoc();	0	2617	SecondIdxLoc = getLoc();	0
2618	if (!parseExpr(RegHi))	0	2618	if (!parseExpr(RegHi))	0
2619	return false;	0	2619	return false;	0
2620	} else {	---	2620	} else {	---
2621	RegHi = RegLo;	0	2621	RegHi = RegLo;	0
2622	}	---	2622	}	---
2623		---	2623		---
2624	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0	2624	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
2625	return false;	0	2625	return false;	0
2626		---	2626		---
2627	if (!isUInt<32>(RegLo)) {	0	2627	if (!isUInt<32>(RegLo)) {	0
2628	Error(FirstIdxLoc, "invalid register index");	0	2628	Error(FirstIdxLoc, "invalid register index");	0
2629	return false;	0	2629	return false;	0
2630	}	---	2630	}	---
2631		---	2631		---
2632	if (!isUInt<32>(RegHi)) {	0	2632	if (!isUInt<32>(RegHi)) {	0
2633	Error(SecondIdxLoc, "invalid register index");	0	2633	Error(SecondIdxLoc, "invalid register index");	0
2634	return false;	0	2634	return false;	0
2635	}	---	2635	}	---
2636		---	2636		---
2637	if (RegLo > RegHi) {	0	2637	if (RegLo > RegHi) {	0
2638	Error(FirstIdxLoc, "first register index should not exceed second index");	0	2638	Error(FirstIdxLoc, "first register index should not exceed second index");	0
2639	return false;	0	2639	return false;	0
2640	}	---	2640	}	---
2641		---	2641		---
2642	Num = static_cast(RegLo);	0	2642	Num = static_cast(RegLo);	0
2643	RegWidth = 32 * ((RegHi - RegLo) + 1);	0	2643	RegWidth = 32 * ((RegHi - RegLo) + 1);	0
2644	return true;	0	2644	return true;	0
2645	}	---	2645	}	---
2646		---	2646		---
2647	unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,	0	2647	unsigned AMDGPUAsmParser::ParseSpecialReg(RegisterKind &RegKind,	0
2648	unsigned &RegNum, unsigned &RegWidth,	---	2648	unsigned &RegNum, unsigned &RegWidth,	---
2649	SmallVectorImpl &Tokens) {	---	2649	SmallVectorImpl &Tokens) {	---
2650	assert(isToken(AsmToken::Identifier));	0	2650	assert(isToken(AsmToken::Identifier));	0
2651	unsigned Reg = getSpecialRegForName(getTokenStr());	0	2651	unsigned Reg = getSpecialRegForName(getTokenStr());	0
2652	if (Reg) {	0	2652	if (Reg) {	0
2653	RegNum = 0;	0	2653	RegNum = 0;	0
2654	RegWidth = 32;	0	2654	RegWidth = 32;	0
2655	RegKind = IS_SPECIAL;	0	2655	RegKind = IS_SPECIAL;	0
2656	Tokens.push_back(getToken());	0	2656	Tokens.push_back(getToken());	0
2657	lex(); // skip register name	0	2657	lex(); // skip register name	0
2658	}	---	2658	}	---
2659	return Reg;	0	2659	return Reg;	0
2660	}	---	2660	}	---
2661		---	2661		---
2662	unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,	0	2662	unsigned AMDGPUAsmParser::ParseRegularReg(RegisterKind &RegKind,	0
2663	unsigned &RegNum, unsigned &RegWidth,	---	2663	unsigned &RegNum, unsigned &RegWidth,	---
2664	SmallVectorImpl &Tokens) {	---	2664	SmallVectorImpl &Tokens) {	---
2665	assert(isToken(AsmToken::Identifier));	0	2665	assert(isToken(AsmToken::Identifier));	0
2666	StringRef RegName = getTokenStr();	0	2666	StringRef RegName = getTokenStr();	0
2667	auto Loc = getLoc();	0	2667	auto Loc = getLoc();	0
2668		---	2668		---
2669	const RegInfo *RI = getRegularRegInfo(RegName);	0	2669	const RegInfo *RI = getRegularRegInfo(RegName);	0
2670	if (!RI) {	0	2670	if (!RI) {	0
2671	Error(Loc, "invalid register name");	0	2671	Error(Loc, "invalid register name");	0
2672	return AMDGPU::NoRegister;	0	2672	return AMDGPU::NoRegister;	0
2673	}	---	2673	}	---
2674		---	2674		---
2675	Tokens.push_back(getToken());	0	2675	Tokens.push_back(getToken());	0
2676	lex(); // skip register name	0	2676	lex(); // skip register name	0
2677		---	2677		---
2678	RegKind = RI->Kind;	0	2678	RegKind = RI->Kind;	0
2679	StringRef RegSuffix = RegName.substr(RI->Name.size());	0	2679	StringRef RegSuffix = RegName.substr(RI->Name.size());	0
2680	if (!RegSuffix.empty()) {	0	2680	if (!RegSuffix.empty()) {	0
2681	// Single 32-bit register: vXX.	---	2681	// Single 32-bit register: vXX.	---
2682	if (!getRegNum(RegSuffix, RegNum)) {	0	2682	if (!getRegNum(RegSuffix, RegNum)) {	0
2683	Error(Loc, "invalid register index");	0	2683	Error(Loc, "invalid register index");	0
2684	return AMDGPU::NoRegister;	0	2684	return AMDGPU::NoRegister;	0
2685	}	---	2685	}	---
2686	RegWidth = 32;	0	2686	RegWidth = 32;	0
2687	} else {	---	2687	} else {	---
2688	// Range of registers: v[XX:YY]. ":YY" is optional.	---	2688	// Range of registers: v[XX:YY]. ":YY" is optional.	---
2689	if (!ParseRegRange(RegNum, RegWidth))	0	2689	if (!ParseRegRange(RegNum, RegWidth))	0
2690	return AMDGPU::NoRegister;	0	2690	return AMDGPU::NoRegister;	0
2691	}	---	2691	}	---
2692		---	2692		---
2693	return getRegularReg(RegKind, RegNum, RegWidth, Loc);	0	2693	return getRegularReg(RegKind, RegNum, RegWidth, Loc);	0
2694	}	---	2694	}	---
2695		---	2695		---
2696	unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	0	2696	unsigned AMDGPUAsmParser::ParseRegList(RegisterKind &RegKind, unsigned &RegNum,	0
2697	unsigned &RegWidth,	---	2697	unsigned &RegWidth,	---
2698	SmallVectorImpl &Tokens) {	---	2698	SmallVectorImpl &Tokens) {	---
2699	unsigned Reg = AMDGPU::NoRegister;	0	2699	unsigned Reg = AMDGPU::NoRegister;	0
2700	auto ListLoc = getLoc();	0	2700	auto ListLoc = getLoc();	0
2701		---	2701		---
2702	if (!skipToken(AsmToken::LBrac,	0	2702	if (!skipToken(AsmToken::LBrac,	0
2703	"expected a register or a list of registers")) {	---	2703	"expected a register or a list of registers")) {	---
2704	return AMDGPU::NoRegister;	0	2704	return AMDGPU::NoRegister;	0
2705	}	---	2705	}	---
2706		---	2706		---
2707	// List of consecutive registers, e.g.: [s0,s1,s2,s3]	---	2707	// List of consecutive registers, e.g.: [s0,s1,s2,s3]	---
2708		---	2708		---
2709	auto Loc = getLoc();	0	2709	auto Loc = getLoc();	0
2710	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))	0	2710	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth))	0
2711	return AMDGPU::NoRegister;	0	2711	return AMDGPU::NoRegister;	0
2712	if (RegWidth != 32) {	0	2712	if (RegWidth != 32) {	0
2713	Error(Loc, "expected a single 32-bit register");	0	2713	Error(Loc, "expected a single 32-bit register");	0
2714	return AMDGPU::NoRegister;	0	2714	return AMDGPU::NoRegister;	0
2715	}	---	2715	}	---
2716		---	2716		---
2717	for (; trySkipToken(AsmToken::Comma); ) {	0	2717	for (; trySkipToken(AsmToken::Comma); ) {	0
2718	RegisterKind NextRegKind;	---	2718	RegisterKind NextRegKind;	---
2719	unsigned NextReg, NextRegNum, NextRegWidth;	---	2719	unsigned NextReg, NextRegNum, NextRegWidth;	---
2720	Loc = getLoc();	0	2720	Loc = getLoc();	0
2721		---	2721		---
2722	if (!ParseAMDGPURegister(NextRegKind, NextReg,	0	2722	if (!ParseAMDGPURegister(NextRegKind, NextReg,	0
2723	NextRegNum, NextRegWidth,	---	2723	NextRegNum, NextRegWidth,	---
2724	Tokens)) {	---	2724	Tokens)) {	---
2725	return AMDGPU::NoRegister;	0	2725	return AMDGPU::NoRegister;	0
2726	}	---	2726	}	---
2727	if (NextRegWidth != 32) {	0	2727	if (NextRegWidth != 32) {	0
2728	Error(Loc, "expected a single 32-bit register");	0	2728	Error(Loc, "expected a single 32-bit register");	0
2729	return AMDGPU::NoRegister;	0	2729	return AMDGPU::NoRegister;	0
2730	}	---	2730	}	---
2731	if (NextRegKind != RegKind) {	0	2731	if (NextRegKind != RegKind) {	0
2732	Error(Loc, "registers in a list must be of the same kind");	0	2732	Error(Loc, "registers in a list must be of the same kind");	0
2733	return AMDGPU::NoRegister;	0	2733	return AMDGPU::NoRegister;	0
2734	}	---	2734	}	---
2735	if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))	0	2735	if (!AddNextRegisterToList(Reg, RegWidth, RegKind, NextReg, Loc))	0
2736	return AMDGPU::NoRegister;	0	2736	return AMDGPU::NoRegister;	0
2737	}	---	2737	}	---
2738		---	2738		---
2739	if (!skipToken(AsmToken::RBrac,	0	2739	if (!skipToken(AsmToken::RBrac,	0
2740	"expected a comma or a closing square bracket")) {	---	2740	"expected a comma or a closing square bracket")) {	---
2741	return AMDGPU::NoRegister;	0	2741	return AMDGPU::NoRegister;	0
2742	}	---	2742	}	---
2743		---	2743		---
2744	if (isRegularReg(RegKind))	0	2744	if (isRegularReg(RegKind))	0
2745	Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);	0	2745	Reg = getRegularReg(RegKind, RegNum, RegWidth, ListLoc);	0
2746		---	2746		---
2747	return Reg;	0	2747	return Reg;	0
2748	}	---	2748	}	---
2749		---	2749		---
2750	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	0	2750	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	0
2751	unsigned &RegNum, unsigned &RegWidth,	---	2751	unsigned &RegNum, unsigned &RegWidth,	---
2752	SmallVectorImpl &Tokens) {	---	2752	SmallVectorImpl &Tokens) {	---
2753	auto Loc = getLoc();	0	2753	auto Loc = getLoc();	0
2754	Reg = AMDGPU::NoRegister;	0	2754	Reg = AMDGPU::NoRegister;	0
2755		---	2755		---
2756	if (isToken(AsmToken::Identifier)) {	0	2756	if (isToken(AsmToken::Identifier)) {	0
2757	Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);	0	2757	Reg = ParseSpecialReg(RegKind, RegNum, RegWidth, Tokens);	0
2758	if (Reg == AMDGPU::NoRegister)	0	2758	if (Reg == AMDGPU::NoRegister)	0
2759	Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);	0	2759	Reg = ParseRegularReg(RegKind, RegNum, RegWidth, Tokens);	0
2760	} else {	---	2760	} else {	---
2761	Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);	0	2761	Reg = ParseRegList(RegKind, RegNum, RegWidth, Tokens);	0
2762	}	---	2762	}	---
2763		---	2763		---
2764	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	2764	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
2765	if (Reg == AMDGPU::NoRegister) {	0	2765	if (Reg == AMDGPU::NoRegister) {	0
2766	assert(Parser.hasPendingError());	0	2766	assert(Parser.hasPendingError());	0
2767	return false;	0	2767	return false;	0
2768	}	---	2768	}	---
2769		---	2769		---
2770	if (!subtargetHasRegister(*TRI, Reg)) {	0	2770	if (!subtargetHasRegister(*TRI, Reg)) {	0
2771	if (Reg == AMDGPU::SGPR_NULL) {	0	2771	if (Reg == AMDGPU::SGPR_NULL) {	0
2772	Error(Loc, "'null' operand is not supported on this GPU");	0	2772	Error(Loc, "'null' operand is not supported on this GPU");	0
2773	} else {	---	2773	} else {	---
2774	Error(Loc, "register not available on this GPU");	0	2774	Error(Loc, "register not available on this GPU");	0
2775	}	---	2775	}	---
2776	return false;	0	2776	return false;	0
2777	}	---	2777	}	---
2778		---	2778		---
2779	return true;	0	2779	return true;	0
2780	}	---	2780	}	---
2781		---	2781		---
2782	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	0	2782	bool AMDGPUAsmParser::ParseAMDGPURegister(RegisterKind &RegKind, unsigned &Reg,	0
2783	unsigned &RegNum, unsigned &RegWidth,	---	2783	unsigned &RegNum, unsigned &RegWidth,	---
2784	bool RestoreOnFailure /=false/) {	---	2784	bool RestoreOnFailure /=false/) {	---
2785	Reg = AMDGPU::NoRegister;	0	2785	Reg = AMDGPU::NoRegister;	0
2786		---	2786		---
2787	SmallVector Tokens;	0	2787	SmallVector Tokens;	0
2788	if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {	0	2788	if (ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth, Tokens)) {	0
2789	if (RestoreOnFailure) {	0	2789	if (RestoreOnFailure) {	0
2790	while (!Tokens.empty()) {	0	2790	while (!Tokens.empty()) {	0
2791	getLexer().UnLex(Tokens.pop_back_val());	0	2791	getLexer().UnLex(Tokens.pop_back_val());	0
2792	}	---	2792	}	---
2793	}	---	2793	}	---
2794	return true;	0	2794	return true;	0
2795	}	---	2795	}	---
2796	return false;	0	2796	return false;	0
2797	}	0	2797	}	0
2798		---	2798		---
2799	std::optional	---	2799	std::optional	---
2800	AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {	0	2800	AMDGPUAsmParser::getGprCountSymbolName(RegisterKind RegKind) {	0
2801	switch (RegKind) {	0	2801	switch (RegKind) {	0
2802	case IS_VGPR:	0	2802	case IS_VGPR:	0
2803	return StringRef(".amdgcn.next_free_vgpr");	0	2803	return StringRef(".amdgcn.next_free_vgpr");	0
2804	case IS_SGPR:	0	2804	case IS_SGPR:	0
2805	return StringRef(".amdgcn.next_free_sgpr");	0	2805	return StringRef(".amdgcn.next_free_sgpr");	0
2806	default:	0	2806	default:	0
2807	return std::nullopt;	0	2807	return std::nullopt;	0
2808	}	---	2808	}	---
2809	}	---	2809	}	---
2810		---	2810		---
2811	void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {	0	2811	void AMDGPUAsmParser::initializeGprCountSymbol(RegisterKind RegKind) {	0
2812	auto SymbolName = getGprCountSymbolName(RegKind);	0	2812	auto SymbolName = getGprCountSymbolName(RegKind);	0
2813	assert(SymbolName && "initializing invalid register kind");	0	2813	assert(SymbolName && "initializing invalid register kind");	0
2814	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	0	2814	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	0
2815	Sym->setVariableValue(MCConstantExpr::create(0, getContext()));	0	2815	Sym->setVariableValue(MCConstantExpr::create(0, getContext()));	0
2816	}	0	2816	}	0
2817		---	2817		---
2818	bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,	0	2818	bool AMDGPUAsmParser::updateGprCountSymbols(RegisterKind RegKind,	0
2819	unsigned DwordRegIndex,	---	2819	unsigned DwordRegIndex,	---
2820	unsigned RegWidth) {	---	2820	unsigned RegWidth) {	---
2821	// Symbols are only defined for GCN targets	---	2821	// Symbols are only defined for GCN targets	---
2822	if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)	0	2822	if (AMDGPU::getIsaVersion(getSTI().getCPU()).Major < 6)	0
2823	return true;	0	2823	return true;	0
2824		---	2824		---
2825	auto SymbolName = getGprCountSymbolName(RegKind);	0	2825	auto SymbolName = getGprCountSymbolName(RegKind);	0
2826	if (!SymbolName)	0	2826	if (!SymbolName)	0
2827	return true;	0	2827	return true;	0
2828	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	0	2828	MCSymbol Sym = getContext().getOrCreateSymbol(SymbolName);	0
2829		---	2829		---
2830	int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;	0	2830	int64_t NewMax = DwordRegIndex + divideCeil(RegWidth, 32) - 1;	0
2831	int64_t OldCount;	---	2831	int64_t OldCount;	---
2832		---	2832		---
2833	if (!Sym->isVariable())	0	2833	if (!Sym->isVariable())	0
2834	return !Error(getLoc(),	0	2834	return !Error(getLoc(),	0
2835	".amdgcn.next_free_{v,s}gpr symbols must be variable");	0	2835	".amdgcn.next_free_{v,s}gpr symbols must be variable");	0
2836	if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))	0	2836	if (!Sym->getVariableValue(false)->evaluateAsAbsolute(OldCount))	0
2837	return !Error(	0	2837	return !Error(	0
2838	getLoc(),	---	2838	getLoc(),	---
2839	".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");	0	2839	".amdgcn.next_free_{v,s}gpr symbols must be absolute expressions");	0
2840		---	2840		---
2841	if (OldCount <= NewMax)	0	2841	if (OldCount <= NewMax)	0
2842	Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));	0	2842	Sym->setVariableValue(MCConstantExpr::create(NewMax + 1, getContext()));	0
2843		---	2843		---
2844	return true;	0	2844	return true;	0
2845	}	---	2845	}	---
2846		---	2846		---
2847	std::unique_ptr	---	2847	std::unique_ptr	---
2848	AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {	0	2848	AMDGPUAsmParser::parseRegister(bool RestoreOnFailure) {	0
2849	const auto &Tok = getToken();	0	2849	const auto &Tok = getToken();	0
2850	SMLoc StartLoc = Tok.getLoc();	0	2850	SMLoc StartLoc = Tok.getLoc();	0
2851	SMLoc EndLoc = Tok.getEndLoc();	0	2851	SMLoc EndLoc = Tok.getEndLoc();	0
2852	RegisterKind RegKind;	---	2852	RegisterKind RegKind;	---
2853	unsigned Reg, RegNum, RegWidth;	---	2853	unsigned Reg, RegNum, RegWidth;	---
2854		---	2854		---
2855	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {	0	2855	if (!ParseAMDGPURegister(RegKind, Reg, RegNum, RegWidth)) {	0
2856	return nullptr;	0	2856	return nullptr;	0
2857	}	---	2857	}	---
2858	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0	2858	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0
2859	if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))	0	2859	if (!updateGprCountSymbols(RegKind, RegNum, RegWidth))	0
2860	return nullptr;	0	2860	return nullptr;	0
2861	} else	---	2861	} else	---
2862	KernelScope.usesRegister(RegKind, RegNum, RegWidth);	0	2862	KernelScope.usesRegister(RegKind, RegNum, RegWidth);	0
2863	return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);	0	2863	return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc);	0
2864	}	0	2864	}	0
2865		---	2865		---
2866	ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,	0	2866	ParseStatus AMDGPUAsmParser::parseImm(OperandVector &Operands,	0
2867	bool HasSP3AbsModifier) {	---	2867	bool HasSP3AbsModifier) {	---
2868	// TODO: add syntactic sugar for 1/(2*PI)	---	2868	// TODO: add syntactic sugar for 1/(2*PI)	---
2869		---	2869		---
2870	if (isRegister())	0	2870	if (isRegister())	0
2871	return ParseStatus::NoMatch;	0	2871	return ParseStatus::NoMatch;	0
2872	assert(!isModifier());	0	2872	assert(!isModifier());	0
2873		---	2873		---
2874	const auto& Tok = getToken();	0	2874	const auto& Tok = getToken();	0
2875	const auto& NextTok = peekToken();	0	2875	const auto& NextTok = peekToken();	0
2876	bool IsReal = Tok.is(AsmToken::Real);	0	2876	bool IsReal = Tok.is(AsmToken::Real);	0
2877	SMLoc S = getLoc();	0	2877	SMLoc S = getLoc();	0
2878	bool Negate = false;	0	2878	bool Negate = false;	0
2879		---	2879		---
2880	if (!IsReal && Tok.is(AsmToken::Minus) && NextTok.is(AsmToken::Real)) {	0	2880	if (!IsReal && Tok.is(AsmToken::Minus) && NextTok.is(AsmToken::Real)) {	0
2881	lex();	0	2881	lex();	0
2882	IsReal = true;	0	2882	IsReal = true;	0
2883	Negate = true;	0	2883	Negate = true;	0
2884	}	---	2884	}	---
2885		---	2885		---
2886	if (IsReal) {	0	2886	if (IsReal) {	0
2887	// Floating-point expressions are not supported.	---	2887	// Floating-point expressions are not supported.	---
2888	// Can only allow floating-point literals with an	---	2888	// Can only allow floating-point literals with an	---
2889	// optional sign.	---	2889	// optional sign.	---
2890		---	2890		---
2891	StringRef Num = getTokenStr();	0	2891	StringRef Num = getTokenStr();	0
2892	lex();	0	2892	lex();	0
2893		---	2893		---
2894	APFloat RealVal(APFloat::IEEEdouble());	0	2894	APFloat RealVal(APFloat::IEEEdouble());	0
2895	auto roundMode = APFloat::rmNearestTiesToEven;	0	2895	auto roundMode = APFloat::rmNearestTiesToEven;	0
2896	if (errorToBool(RealVal.convertFromString(Num, roundMode).takeError()))	0	2896	if (errorToBool(RealVal.convertFromString(Num, roundMode).takeError()))	0
2897	return ParseStatus::Failure;	0	2897	return ParseStatus::Failure;	0
2898	if (Negate)	0	2898	if (Negate)	0
2899	RealVal.changeSign();	0	2899	RealVal.changeSign();	0
2900		---	2900		---
2901	Operands.push_back(	0	2901	Operands.push_back(	0
2902	AMDGPUOperand::CreateImm(this, RealVal.bitcastToAPInt().getZExtValue(), S,	0	2902	AMDGPUOperand::CreateImm(this, RealVal.bitcastToAPInt().getZExtValue(), S,	0
2903	AMDGPUOperand::ImmTyNone, true));	---	2903	AMDGPUOperand::ImmTyNone, true));	---
2904		---	2904		---
2905	return ParseStatus::Success;	0	2905	return ParseStatus::Success;	0
2906		---	2906		---
2907	} else {	0	2907	} else {	0
2908	int64_t IntVal;	---	2908	int64_t IntVal;	---
2909	const MCExpr *Expr;	---	2909	const MCExpr *Expr;	---
2910	SMLoc S = getLoc();	0	2910	SMLoc S = getLoc();	0
2911		---	2911		---
2912	if (HasSP3AbsModifier) {	0	2912	if (HasSP3AbsModifier) {	0
2913	// This is a workaround for handling expressions	---	2913	// This is a workaround for handling expressions	---
2914	// as arguments of SP3 'abs' modifier, for example:	---	2914	// as arguments of SP3 'abs' modifier, for example:	---
2915	// \|1.0\|	---	2915	// \|1.0\|	---
2916	// \|-1\|	---	2916	// \|-1\|	---
2917	// \|1+x\|	---	2917	// \|1+x\|	---
2918	// This syntax is not compatible with syntax of standard	---	2918	// This syntax is not compatible with syntax of standard	---
2919	// MC expressions (due to the trailing '\|').	---	2919	// MC expressions (due to the trailing '\|').	---
2920	SMLoc EndLoc;	0	2920	SMLoc EndLoc;	0
2921	if (getParser().parsePrimaryExpr(Expr, EndLoc, nullptr))	0	2921	if (getParser().parsePrimaryExpr(Expr, EndLoc, nullptr))	0
2922	return ParseStatus::Failure;	0	2922	return ParseStatus::Failure;	0
2923	} else {	---	2923	} else {	---
2924	if (Parser.parseExpression(Expr))	0	2924	if (Parser.parseExpression(Expr))	0
2925	return ParseStatus::Failure;	0	2925	return ParseStatus::Failure;	0
2926	}	---	2926	}	---
2927		---	2927		---
2928	if (Expr->evaluateAsAbsolute(IntVal)) {	0	2928	if (Expr->evaluateAsAbsolute(IntVal)) {	0
2929	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	0	2929	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	0
2930	} else {	---	2930	} else {	---
2931	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	0	2931	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	0
2932	}	---	2932	}	---
2933		---	2933		---
2934	return ParseStatus::Success;	0	2934	return ParseStatus::Success;	0
2935	}	---	2935	}	---
2936		---	2936		---
2937	return ParseStatus::NoMatch;	---	2937	return ParseStatus::NoMatch;	---
2938	}	0	2938	}	0
2939		---	2939		---
2940	ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {	0	2940	ParseStatus AMDGPUAsmParser::parseReg(OperandVector &Operands) {	0
2941	if (!isRegister())	0	2941	if (!isRegister())	0
2942	return ParseStatus::NoMatch;	0	2942	return ParseStatus::NoMatch;	0
2943		---	2943		---
2944	if (auto R = parseRegister()) {	0	2944	if (auto R = parseRegister()) {	0
2945	assert(R->isReg());	0	2945	assert(R->isReg());	0
2946	Operands.push_back(std::move(R));	0	2946	Operands.push_back(std::move(R));	0
2947	return ParseStatus::Success;	0	2947	return ParseStatus::Success;	0
2948	}	0	2948	}	0
2949	return ParseStatus::Failure;	0	2949	return ParseStatus::Failure;	0
2950	}	---	2950	}	---
2951		---	2951		---
2952	ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,	0	2952	ParseStatus AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands,	0
2953	bool HasSP3AbsMod) {	---	2953	bool HasSP3AbsMod) {	---
2954	ParseStatus Res = parseReg(Operands);	0	2954	ParseStatus Res = parseReg(Operands);	0
2955	if (!Res.isNoMatch())	0	2955	if (!Res.isNoMatch())	0
2956	return Res;	0	2956	return Res;	0
2957	if (isModifier())	0	2957	if (isModifier())	0
2958	return ParseStatus::NoMatch;	0	2958	return ParseStatus::NoMatch;	0
2959	return parseImm(Operands, HasSP3AbsMod);	0	2959	return parseImm(Operands, HasSP3AbsMod);	0
2960	}	---	2960	}	---
2961		---	2961		---
2962	bool	---	2962	bool	---
2963	AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0	2963	AMDGPUAsmParser::isNamedOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0
2964	if (Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::LParen)) {	0	2964	if (Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::LParen)) {	0
2965	const auto &str = Token.getString();	0	2965	const auto &str = Token.getString();	0
2966	return str == "abs" \|\| str == "neg" \|\| str == "sext";	0	2966	return str == "abs" \|\| str == "neg" \|\| str == "sext";	0
2967	}	---	2967	}	---
2968	return false;	0	2968	return false;	0
2969	}	---	2969	}	---
2970		---	2970		---
2971	bool	---	2971	bool	---
2972	AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {	0	2972	AMDGPUAsmParser::isOpcodeModifierWithVal(const AsmToken &Token, const AsmToken &NextToken) const {	0
2973	return Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::Colon);	0	2973	return Token.is(AsmToken::Identifier) && NextToken.is(AsmToken::Colon);	0
2974	}	---	2974	}	---
2975		---	2975		---
2976	bool	---	2976	bool	---
2977	AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0	2977	AMDGPUAsmParser::isOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0
2978	return isNamedOperandModifier(Token, NextToken) \|\| Token.is(AsmToken::Pipe);	0	2978	return isNamedOperandModifier(Token, NextToken) \|\| Token.is(AsmToken::Pipe);	0
2979	}	---	2979	}	---
2980		---	2980		---
2981	bool	---	2981	bool	---
2982	AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0	2982	AMDGPUAsmParser::isRegOrOperandModifier(const AsmToken &Token, const AsmToken &NextToken) const {	0
2983	return isRegister(Token, NextToken) \|\| isOperandModifier(Token, NextToken);	0	2983	return isRegister(Token, NextToken) \|\| isOperandModifier(Token, NextToken);	0
2984	}	---	2984	}	---
2985		---	2985		---
2986	// Check if this is an operand modifier or an opcode modifier	---	2986	// Check if this is an operand modifier or an opcode modifier	---
2987	// which may look like an expression but it is not. We should	---	2987	// which may look like an expression but it is not. We should	---
2988	// avoid parsing these modifiers as expressions. Currently	---	2988	// avoid parsing these modifiers as expressions. Currently	---
2989	// recognized sequences are:	---	2989	// recognized sequences are:	---
2990	// \|...\|	---	2990	// \|...\|	---
2991	// abs(...)	---	2991	// abs(...)	---
2992	// neg(...)	---	2992	// neg(...)	---
2993	// sext(...)	---	2993	// sext(...)	---
2994	// -reg	---	2994	// -reg	---
2995	// -\|...\|	---	2995	// -\|...\|	---
2996	// -abs(...)	---	2996	// -abs(...)	---
2997	// name:...	---	2997	// name:...	---
2998	//	---	2998	//	---
2999	bool	---	2999	bool	---
3000	AMDGPUAsmParser::isModifier() {	0	3000	AMDGPUAsmParser::isModifier() {	0
3001		---	3001		---
3002	AsmToken Tok = getToken();	0	3002	AsmToken Tok = getToken();	0
3003	AsmToken NextToken[2];	0	3003	AsmToken NextToken[2];	0
3004	peekTokens(NextToken);	0	3004	peekTokens(NextToken);	0
3005		---	3005		---
3006	return isOperandModifier(Tok, NextToken[0]) \|\|	0	3006	return isOperandModifier(Tok, NextToken[0]) \|\|	0
3007	(Tok.is(AsmToken::Minus) && isRegOrOperandModifier(NextToken[0], NextToken[1])) \|\|	0	3007	(Tok.is(AsmToken::Minus) && isRegOrOperandModifier(NextToken[0], NextToken[1])) \|\|	0
3008	isOpcodeModifierWithVal(Tok, NextToken[0]);	0	3008	isOpcodeModifierWithVal(Tok, NextToken[0]);	0
3009	}	0	3009	}	0
3010		---	3010		---
3011	// Check if the current token is an SP3 'neg' modifier.	---	3011	// Check if the current token is an SP3 'neg' modifier.	---
3012	// Currently this modifier is allowed in the following context:	---	3012	// Currently this modifier is allowed in the following context:	---
3013	//	---	3013	//	---
3014	// 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".	---	3014	// 1. Before a register, e.g. "-v0", "-v[...]" or "-[v0,v1]".	---
3015	// 2. Before an 'abs' modifier: -abs(...)	---	3015	// 2. Before an 'abs' modifier: -abs(...)	---
3016	// 3. Before an SP3 'abs' modifier: -\|...\|	---	3016	// 3. Before an SP3 'abs' modifier: -\|...\|	---
3017	//	---	3017	//	---
3018	// In all other cases "-" is handled as a part	---	3018	// In all other cases "-" is handled as a part	---
3019	// of an expression that follows the sign.	---	3019	// of an expression that follows the sign.	---
3020	//	---	3020	//	---
3021	// Note: When "-" is followed by an integer literal,	---	3021	// Note: When "-" is followed by an integer literal,	---
3022	// this is interpreted as integer negation rather	---	3022	// this is interpreted as integer negation rather	---
3023	// than a floating-point NEG modifier applied to N.	---	3023	// than a floating-point NEG modifier applied to N.	---
3024	// Beside being contr-intuitive, such use of floating-point	---	3024	// Beside being contr-intuitive, such use of floating-point	---
3025	// NEG modifier would have resulted in different meaning	---	3025	// NEG modifier would have resulted in different meaning	---
3026	// of integer literals used with VOP1/2/C and VOP3,	---	3026	// of integer literals used with VOP1/2/C and VOP3,	---
3027	// for example:	---	3027	// for example:	---
3028	// v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF	---	3028	// v_exp_f32_e32 v5, -1 // VOP1: src0 = 0xFFFFFFFF	---
3029	// v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001	---	3029	// v_exp_f32_e64 v5, -1 // VOP3: src0 = 0x80000001	---
3030	// Negative fp literals with preceding "-" are	---	3030	// Negative fp literals with preceding "-" are	---
3031	// handled likewise for uniformity	---	3031	// handled likewise for uniformity	---
3032	//	---	3032	//	---
3033	bool	---	3033	bool	---
3034	AMDGPUAsmParser::parseSP3NegModifier() {	0	3034	AMDGPUAsmParser::parseSP3NegModifier() {	0
3035		---	3035		---
3036	AsmToken NextToken[2];	0	3036	AsmToken NextToken[2];	0
3037	peekTokens(NextToken);	0	3037	peekTokens(NextToken);	0
3038		---	3038		---
3039	if (isToken(AsmToken::Minus) &&	0	3039	if (isToken(AsmToken::Minus) &&	0
3040	(isRegister(NextToken[0], NextToken[1]) \|\|	0	3040	(isRegister(NextToken[0], NextToken[1]) \|\|	0
3041	NextToken[0].is(AsmToken::Pipe) \|\|	0	3041	NextToken[0].is(AsmToken::Pipe) \|\|	0
3042	isId(NextToken[0], "abs"))) {	0	3042	isId(NextToken[0], "abs"))) {	0
3043	lex();	0	3043	lex();	0
3044	return true;	0	3044	return true;	0
3045	}	---	3045	}	---
3046		---	3046		---
3047	return false;	0	3047	return false;	0
3048	}	0	3048	}	0
3049		---	3049		---
3050	ParseStatus	---	3050	ParseStatus	---
3051	AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,	0	3051	AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands,	0
3052	bool AllowImm) {	---	3052	bool AllowImm) {	---
3053	bool Neg, SP3Neg;	---	3053	bool Neg, SP3Neg;	---
3054	bool Abs, SP3Abs;	---	3054	bool Abs, SP3Abs;	---
3055	SMLoc Loc;	0	3055	SMLoc Loc;	0
3056		---	3056		---
3057	// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.	---	3057	// Disable ambiguous constructs like '--1' etc. Should use neg(-1) instead.	---
3058	if (isToken(AsmToken::Minus) && peekToken().is(AsmToken::Minus))	0	3058	if (isToken(AsmToken::Minus) && peekToken().is(AsmToken::Minus))	0
3059	return Error(getLoc(), "invalid syntax, expected 'neg' modifier");	0	3059	return Error(getLoc(), "invalid syntax, expected 'neg' modifier");	0
3060		---	3060		---
3061	SP3Neg = parseSP3NegModifier();	0	3061	SP3Neg = parseSP3NegModifier();	0
3062		---	3062		---
3063	Loc = getLoc();	0	3063	Loc = getLoc();	0
3064	Neg = trySkipId("neg");	0	3064	Neg = trySkipId("neg");	0
3065	if (Neg && SP3Neg)	0	3065	if (Neg && SP3Neg)	0
3066	return Error(Loc, "expected register or immediate");	0	3066	return Error(Loc, "expected register or immediate");	0
3067	if (Neg && !skipToken(AsmToken::LParen, "expected left paren after neg"))	0	3067	if (Neg && !skipToken(AsmToken::LParen, "expected left paren after neg"))	0
3068	return ParseStatus::Failure;	0	3068	return ParseStatus::Failure;	0
3069		---	3069		---
3070	Abs = trySkipId("abs");	0	3070	Abs = trySkipId("abs");	0
3071	if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))	0	3071	if (Abs && !skipToken(AsmToken::LParen, "expected left paren after abs"))	0
3072	return ParseStatus::Failure;	0	3072	return ParseStatus::Failure;	0
3073		---	3073		---
3074	Loc = getLoc();	0	3074	Loc = getLoc();	0
3075	SP3Abs = trySkipToken(AsmToken::Pipe);	0	3075	SP3Abs = trySkipToken(AsmToken::Pipe);	0
3076	if (Abs && SP3Abs)	0	3076	if (Abs && SP3Abs)	0
3077	return Error(Loc, "expected register or immediate");	0	3077	return Error(Loc, "expected register or immediate");	0
3078		---	3078		---
3079	ParseStatus Res;	0	3079	ParseStatus Res;	0
3080	if (AllowImm) {	0	3080	if (AllowImm) {	0
3081	Res = parseRegOrImm(Operands, SP3Abs);	0	3081	Res = parseRegOrImm(Operands, SP3Abs);	0
3082	} else {	---	3082	} else {	---
3083	Res = parseReg(Operands);	0	3083	Res = parseReg(Operands);	0
3084	}	---	3084	}	---
3085	if (!Res.isSuccess())	0	3085	if (!Res.isSuccess())	0
3086	return (SP3Neg \|\| Neg \|\| SP3Abs \|\| Abs) ? ParseStatus::Failure : Res;	0	3086	return (SP3Neg \|\| Neg \|\| SP3Abs \|\| Abs) ? ParseStatus::Failure : Res;	0
3087		---	3087		---
3088	if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))	0	3088	if (SP3Abs && !skipToken(AsmToken::Pipe, "expected vertical bar"))	0
3089	return ParseStatus::Failure;	0	3089	return ParseStatus::Failure;	0
3090	if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0	3090	if (Abs && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0
3091	return ParseStatus::Failure;	0	3091	return ParseStatus::Failure;	0
3092	if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0	3092	if (Neg && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0
3093	return ParseStatus::Failure;	0	3093	return ParseStatus::Failure;	0
3094		---	3094		---
3095	AMDGPUOperand::Modifiers Mods;	0	3095	AMDGPUOperand::Modifiers Mods;	0
3096	Mods.Abs = Abs \|\| SP3Abs;	0	3096	Mods.Abs = Abs \|\| SP3Abs;	0
3097	Mods.Neg = Neg \|\| SP3Neg;	0	3097	Mods.Neg = Neg \|\| SP3Neg;	0
3098		---	3098		---
3099	if (Mods.hasFPModifiers()) {	0	3099	if (Mods.hasFPModifiers()) {	0
3100	AMDGPUOperand &Op = static_cast(*Operands.back());	0	3100	AMDGPUOperand &Op = static_cast(*Operands.back());	0
3101	if (Op.isExpr())	0	3101	if (Op.isExpr())	0
3102	return Error(Op.getStartLoc(), "expected an absolute expression");	0	3102	return Error(Op.getStartLoc(), "expected an absolute expression");	0
3103	Op.setModifiers(Mods);	0	3103	Op.setModifiers(Mods);	0
3104	}	---	3104	}	---
3105	return ParseStatus::Success;	0	3105	return ParseStatus::Success;	0
3106	}	---	3106	}	---
3107		---	3107		---
3108	ParseStatus	---	3108	ParseStatus	---
3109	AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,	0	3109	AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands,	0
3110	bool AllowImm) {	---	3110	bool AllowImm) {	---
3111	bool Sext = trySkipId("sext");	0	3111	bool Sext = trySkipId("sext");	0
3112	if (Sext && !skipToken(AsmToken::LParen, "expected left paren after sext"))	0	3112	if (Sext && !skipToken(AsmToken::LParen, "expected left paren after sext"))	0
3113	return ParseStatus::Failure;	0	3113	return ParseStatus::Failure;	0
3114		---	3114		---
3115	ParseStatus Res;	0	3115	ParseStatus Res;	0
3116	if (AllowImm) {	0	3116	if (AllowImm) {	0
3117	Res = parseRegOrImm(Operands);	0	3117	Res = parseRegOrImm(Operands);	0
3118	} else {	---	3118	} else {	---
3119	Res = parseReg(Operands);	0	3119	Res = parseReg(Operands);	0
3120	}	---	3120	}	---
3121	if (!Res.isSuccess())	0	3121	if (!Res.isSuccess())	0
3122	return Sext ? ParseStatus::Failure : Res;	0	3122	return Sext ? ParseStatus::Failure : Res;	0
3123		---	3123		---
3124	if (Sext && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0	3124	if (Sext && !skipToken(AsmToken::RParen, "expected closing parentheses"))	0
3125	return ParseStatus::Failure;	0	3125	return ParseStatus::Failure;	0
3126		---	3126		---
3127	AMDGPUOperand::Modifiers Mods;	0	3127	AMDGPUOperand::Modifiers Mods;	0
3128	Mods.Sext = Sext;	0	3128	Mods.Sext = Sext;	0
3129		---	3129		---
3130	if (Mods.hasIntModifiers()) {	0	3130	if (Mods.hasIntModifiers()) {	0
3131	AMDGPUOperand &Op = static_cast(*Operands.back());	0	3131	AMDGPUOperand &Op = static_cast(*Operands.back());	0
3132	if (Op.isExpr())	0	3132	if (Op.isExpr())	0
3133	return Error(Op.getStartLoc(), "expected an absolute expression");	0	3133	return Error(Op.getStartLoc(), "expected an absolute expression");	0
3134	Op.setModifiers(Mods);	0	3134	Op.setModifiers(Mods);	0
3135	}	---	3135	}	---
3136		---	3136		---
3137	return ParseStatus::Success;	0	3137	return ParseStatus::Success;	0
3138	}	---	3138	}	---
3139		---	3139		---
3140	ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {	0	3140	ParseStatus AMDGPUAsmParser::parseRegWithFPInputMods(OperandVector &Operands) {	0
3141	return parseRegOrImmWithFPInputMods(Operands, false);	0	3141	return parseRegOrImmWithFPInputMods(Operands, false);	0
3142	}	---	3142	}	---
3143		---	3143		---
3144	ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {	0	3144	ParseStatus AMDGPUAsmParser::parseRegWithIntInputMods(OperandVector &Operands) {	0
3145	return parseRegOrImmWithIntInputMods(Operands, false);	0	3145	return parseRegOrImmWithIntInputMods(Operands, false);	0
3146	}	---	3146	}	---
3147		---	3147		---
3148	ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {	0	3148	ParseStatus AMDGPUAsmParser::parseVReg32OrOff(OperandVector &Operands) {	0
3149	auto Loc = getLoc();	0	3149	auto Loc = getLoc();	0
3150	if (trySkipId("off")) {	0	3150	if (trySkipId("off")) {	0
3151	Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,	0	3151	Operands.push_back(AMDGPUOperand::CreateImm(this, 0, Loc,	0
3152	AMDGPUOperand::ImmTyOff, false));	---	3152	AMDGPUOperand::ImmTyOff, false));	---
3153	return ParseStatus::Success;	0	3153	return ParseStatus::Success;	0
3154	}	---	3154	}	---
3155		---	3155		---
3156	if (!isRegister())	0	3156	if (!isRegister())	0
3157	return ParseStatus::NoMatch;	0	3157	return ParseStatus::NoMatch;	0
3158		---	3158		---
3159	std::unique_ptr Reg = parseRegister();	0	3159	std::unique_ptr Reg = parseRegister();	0
3160	if (Reg) {	0	3160	if (Reg) {	0
3161	Operands.push_back(std::move(Reg));	0	3161	Operands.push_back(std::move(Reg));	0
3162	return ParseStatus::Success;	0	3162	return ParseStatus::Success;	0
3163	}	---	3163	}	---
3164		---	3164		---
3165	return ParseStatus::Failure;	0	3165	return ParseStatus::Failure;	0
3166	}	0	3166	}	0
3167		---	3167		---
3168	unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {	0	3168	unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {	0
3169	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0	3169	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
3170		---	3170		---
3171	if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) \|\|	0	3171	if ((getForcedEncodingSize() == 32 && (TSFlags & SIInstrFlags::VOP3)) \|\|	0
3172	(getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) \|\|	0	3172	(getForcedEncodingSize() == 64 && !(TSFlags & SIInstrFlags::VOP3)) \|\|	0
3173	(isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) \|\|	0	3173	(isForcedDPP() && !(TSFlags & SIInstrFlags::DPP)) \|\|	0
3174	(isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )	0	3174	(isForcedSDWA() && !(TSFlags & SIInstrFlags::SDWA)) )	0
3175	return Match_InvalidOperand;	0	3175	return Match_InvalidOperand;	0
3176		---	3176		---
3177	if ((TSFlags & SIInstrFlags::VOP3) &&	0	3177	if ((TSFlags & SIInstrFlags::VOP3) &&	0
3178	(TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&	0	3178	(TSFlags & SIInstrFlags::VOPAsmPrefer32Bit) &&	0
3179	getForcedEncodingSize() != 64)	0	3179	getForcedEncodingSize() != 64)	0
3180	return Match_PreferE32;	0	3180	return Match_PreferE32;	0
3181		---	3181		---
3182	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	0	3182	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	0
3183	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	0	3183	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	0
3184	// v_mac_f32/16 allow only dst_sel == DWORD;	---	3184	// v_mac_f32/16 allow only dst_sel == DWORD;	---
3185	auto OpNum =	---	3185	auto OpNum =	---
3186	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);	0	3186	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);	0
3187	const auto &Op = Inst.getOperand(OpNum);	0	3187	const auto &Op = Inst.getOperand(OpNum);	0
3188	if (!Op.isImm() \|\| Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {	0	3188	if (!Op.isImm() \|\| Op.getImm() != AMDGPU::SDWA::SdwaSel::DWORD) {	0
3189	return Match_InvalidOperand;	0	3189	return Match_InvalidOperand;	0
3190	}	---	3190	}	---
3191	}	---	3191	}	---
3192		---	3192		---
3193	return Match_Success;	0	3193	return Match_Success;	0
3194	}	---	3194	}	---
3195		---	3195		---
3196	static ArrayRef getAllVariants() {	0	3196	static ArrayRef getAllVariants() {	0
3197	static const unsigned Variants[] = {	---	3197	static const unsigned Variants[] = {	---
3198	AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,	---	3198	AMDGPUAsmVariants::DEFAULT, AMDGPUAsmVariants::VOP3,	---
3199	AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9,	---	3199	AMDGPUAsmVariants::SDWA, AMDGPUAsmVariants::SDWA9,	---
3200	AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP	---	3200	AMDGPUAsmVariants::DPP, AMDGPUAsmVariants::VOP3_DPP	---
3201	};	---	3201	};	---
3202		---	3202		---
3203	return ArrayRef(Variants);	0	3203	return ArrayRef(Variants);	0
3204	}	---	3204	}	---
3205		---	3205		---
3206	// What asm variants we should check	---	3206	// What asm variants we should check	---
3207	ArrayRef AMDGPUAsmParser::getMatchedVariants() const {	0	3207	ArrayRef AMDGPUAsmParser::getMatchedVariants() const {	0
3208	if (isForcedDPP() && isForcedVOP3()) {	0	3208	if (isForcedDPP() && isForcedVOP3()) {	0
3209	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3_DPP};	---	3209	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3_DPP};	---
3210	return ArrayRef(Variants);	0	3210	return ArrayRef(Variants);	0
3211	}	---	3211	}	---
3212	if (getForcedEncodingSize() == 32) {	0	3212	if (getForcedEncodingSize() == 32) {	0
3213	static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};	---	3213	static const unsigned Variants[] = {AMDGPUAsmVariants::DEFAULT};	---
3214	return ArrayRef(Variants);	0	3214	return ArrayRef(Variants);	0
3215	}	---	3215	}	---
3216		---	3216		---
3217	if (isForcedVOP3()) {	0	3217	if (isForcedVOP3()) {	0
3218	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};	---	3218	static const unsigned Variants[] = {AMDGPUAsmVariants::VOP3};	---
3219	return ArrayRef(Variants);	0	3219	return ArrayRef(Variants);	0
3220	}	---	3220	}	---
3221		---	3221		---
3222	if (isForcedSDWA()) {	0	3222	if (isForcedSDWA()) {	0
3223	static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,	---	3223	static const unsigned Variants[] = {AMDGPUAsmVariants::SDWA,	---
3224	AMDGPUAsmVariants::SDWA9};	---	3224	AMDGPUAsmVariants::SDWA9};	---
3225	return ArrayRef(Variants);	0	3225	return ArrayRef(Variants);	0
3226	}	---	3226	}	---
3227		---	3227		---
3228	if (isForcedDPP()) {	0	3228	if (isForcedDPP()) {	0
3229	static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};	---	3229	static const unsigned Variants[] = {AMDGPUAsmVariants::DPP};	---
3230	return ArrayRef(Variants);	0	3230	return ArrayRef(Variants);	0
3231	}	---	3231	}	---
3232		---	3232		---
3233	return getAllVariants();	0	3233	return getAllVariants();	0
3234	}	---	3234	}	---
3235		---	3235		---
3236	StringRef AMDGPUAsmParser::getMatchedVariantName() const {	0	3236	StringRef AMDGPUAsmParser::getMatchedVariantName() const {	0
3237	if (isForcedDPP() && isForcedVOP3())	0	3237	if (isForcedDPP() && isForcedVOP3())	0
3238	return "e64_dpp";	0	3238	return "e64_dpp";	0
3239		---	3239		---
3240	if (getForcedEncodingSize() == 32)	0	3240	if (getForcedEncodingSize() == 32)	0
3241	return "e32";	0	3241	return "e32";	0
3242		---	3242		---
3243	if (isForcedVOP3())	0	3243	if (isForcedVOP3())	0
3244	return "e64";	0	3244	return "e64";	0
3245		---	3245		---
3246	if (isForcedSDWA())	0	3246	if (isForcedSDWA())	0
3247	return "sdwa";	0	3247	return "sdwa";	0
3248		---	3248		---
3249	if (isForcedDPP())	0	3249	if (isForcedDPP())	0
3250	return "dpp";	0	3250	return "dpp";	0
3251		---	3251		---
3252	return "";	0	3252	return "";	0
3253	}	---	3253	}	---
3254		---	3254		---
3255	unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {	0	3255	unsigned AMDGPUAsmParser::findImplicitSGPRReadInVOP(const MCInst &Inst) const {	0
3256	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	3256	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
3257	for (MCPhysReg Reg : Desc.implicit_uses()) {	0	3257	for (MCPhysReg Reg : Desc.implicit_uses()) {	0
3258	switch (Reg) {	0	3258	switch (Reg) {	0
3259	case AMDGPU::FLAT_SCR:	0	3259	case AMDGPU::FLAT_SCR:	0
3260	case AMDGPU::VCC:	---	3260	case AMDGPU::VCC:	---
3261	case AMDGPU::VCC_LO:	---	3261	case AMDGPU::VCC_LO:	---
3262	case AMDGPU::VCC_HI:	---	3262	case AMDGPU::VCC_HI:	---
3263	case AMDGPU::M0:	---	3263	case AMDGPU::M0:	---
3264	return Reg;	0	3264	return Reg;	0
3265	default:	0	3265	default:	0
3266	break;	0	3266	break;	0
3267	}	---	3267	}	---
3268	}	---	3268	}	---
3269	return AMDGPU::NoRegister;	0	3269	return AMDGPU::NoRegister;	0
3270	}	---	3270	}	---
3271		---	3271		---
3272	// NB: This code is correct only when used to check constant	---	3272	// NB: This code is correct only when used to check constant	---
3273	// bus limitations because GFX7 support no f16 inline constants.	---	3273	// bus limitations because GFX7 support no f16 inline constants.	---
3274	// Note that there are no cases when a GFX7 opcode violates	---	3274	// Note that there are no cases when a GFX7 opcode violates	---
3275	// constant bus limitations due to the use of an f16 constant.	---	3275	// constant bus limitations due to the use of an f16 constant.	---
3276	bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,	0	3276	bool AMDGPUAsmParser::isInlineConstant(const MCInst &Inst,	0
3277	unsigned OpIdx) const {	---	3277	unsigned OpIdx) const {	---
3278	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	3278	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
3279		---	3279		---
3280	if (!AMDGPU::isSISrcOperand(Desc, OpIdx) \|\|	0	3280	if (!AMDGPU::isSISrcOperand(Desc, OpIdx) \|\|	0
3281	AMDGPU::isKImmOperand(Desc, OpIdx)) {	0	3281	AMDGPU::isKImmOperand(Desc, OpIdx)) {	0
3282	return false;	0	3282	return false;	0
3283	}	---	3283	}	---
3284		---	3284		---
3285	const MCOperand &MO = Inst.getOperand(OpIdx);	0	3285	const MCOperand &MO = Inst.getOperand(OpIdx);	0
3286		---	3286		---
3287	int64_t Val = MO.getImm();	0	3287	int64_t Val = MO.getImm();	0
3288	auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);	0	3288	auto OpSize = AMDGPU::getOperandSize(Desc, OpIdx);	0
3289		---	3289		---
3290	switch (OpSize) { // expected operand size	0	3290	switch (OpSize) { // expected operand size	0
3291	case 8:	0	3291	case 8:	0
3292	return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());	0	3292	return AMDGPU::isInlinableLiteral64(Val, hasInv2PiInlineImm());	0
3293	case 4:	0	3293	case 4:	0
3294	return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());	0	3294	return AMDGPU::isInlinableLiteral32(Val, hasInv2PiInlineImm());	0
3295	case 2: {	0	3295	case 2: {	0
3296	const unsigned OperandType = Desc.operands()[OpIdx].OperandType;	0	3296	const unsigned OperandType = Desc.operands()[OpIdx].OperandType;	0
3297	if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 \|\|	0	3297	if (OperandType == AMDGPU::OPERAND_REG_IMM_INT16 \|\|	0
3298	OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 \|\|	0	3298	OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT16 \|\|	0
3299	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16)	---	3299	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_INT16)	---
3300	return AMDGPU::isInlinableIntLiteral(Val);	0	3300	return AMDGPU::isInlinableIntLiteral(Val);	0
3301		---	3301		---
3302	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 \|\|	0	3302	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2INT16 \|\|	0
3303	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 \|\|	0	3303	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2INT16 \|\|	0
3304	OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16)	---	3304	OperandType == AMDGPU::OPERAND_REG_IMM_V2INT16)	---
3305	return AMDGPU::isInlinableIntLiteralV216(Val);	0	3305	return AMDGPU::isInlinableIntLiteralV216(Val);	0
3306		---	3306		---
3307	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 \|\|	0	3307	if (OperandType == AMDGPU::OPERAND_REG_INLINE_C_V2FP16 \|\|	0
3308	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 \|\|	0	3308	OperandType == AMDGPU::OPERAND_REG_INLINE_AC_V2FP16 \|\|	0
3309	OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)	---	3309	OperandType == AMDGPU::OPERAND_REG_IMM_V2FP16)	---
3310	return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());	0	3310	return AMDGPU::isInlinableLiteralV216(Val, hasInv2PiInlineImm());	0
3311		---	3311		---
3312	return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());	0	3312	return AMDGPU::isInlinableLiteral16(Val, hasInv2PiInlineImm());	0
3313	}	---	3313	}	---
3314	default:	0	3314	default:	0
3315	llvm_unreachable("invalid operand size");	0	3315	llvm_unreachable("invalid operand size");	0
3316	}	---	3316	}	---
3317	}	---	3317	}	---
3318		---	3318		---
3319	unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {	0	3319	unsigned AMDGPUAsmParser::getConstantBusLimit(unsigned Opcode) const {	0
3320	if (!isGFX10Plus())	0	3320	if (!isGFX10Plus())	0
3321	return 1;	0	3321	return 1;	0
3322		---	3322		---
3323	switch (Opcode) {	0	3323	switch (Opcode) {	0
3324	// 64-bit shift instructions can use only one scalar value input	---	3324	// 64-bit shift instructions can use only one scalar value input	---
3325	case AMDGPU::V_LSHLREV_B64_e64:	0	3325	case AMDGPU::V_LSHLREV_B64_e64:	0
3326	case AMDGPU::V_LSHLREV_B64_gfx10:	---	3326	case AMDGPU::V_LSHLREV_B64_gfx10:	---
3327	case AMDGPU::V_LSHLREV_B64_e64_gfx11:	---	3327	case AMDGPU::V_LSHLREV_B64_e64_gfx11:	---
3328	case AMDGPU::V_LSHRREV_B64_e64:	---	3328	case AMDGPU::V_LSHRREV_B64_e64:	---
3329	case AMDGPU::V_LSHRREV_B64_gfx10:	---	3329	case AMDGPU::V_LSHRREV_B64_gfx10:	---
3330	case AMDGPU::V_LSHRREV_B64_e64_gfx11:	---	3330	case AMDGPU::V_LSHRREV_B64_e64_gfx11:	---
3331	case AMDGPU::V_ASHRREV_I64_e64:	---	3331	case AMDGPU::V_ASHRREV_I64_e64:	---
3332	case AMDGPU::V_ASHRREV_I64_gfx10:	---	3332	case AMDGPU::V_ASHRREV_I64_gfx10:	---
3333	case AMDGPU::V_ASHRREV_I64_e64_gfx11:	---	3333	case AMDGPU::V_ASHRREV_I64_e64_gfx11:	---
3334	case AMDGPU::V_LSHL_B64_e64:	---	3334	case AMDGPU::V_LSHL_B64_e64:	---
3335	case AMDGPU::V_LSHR_B64_e64:	---	3335	case AMDGPU::V_LSHR_B64_e64:	---
3336	case AMDGPU::V_ASHR_I64_e64:	---	3336	case AMDGPU::V_ASHR_I64_e64:	---
3337	return 1;	0	3337	return 1;	0
3338	default:	0	3338	default:	0
3339	return 2;	0	3339	return 2;	0
3340	}	---	3340	}	---
3341	}	---	3341	}	---
3342		---	3342		---
3343	constexpr unsigned MAX_SRC_OPERANDS_NUM = 6;	---	3343	constexpr unsigned MAX_SRC_OPERANDS_NUM = 6;	---
3344	using OperandIndices = SmallVector;	---	3344	using OperandIndices = SmallVector;	---
3345		---	3345		---
3346	// Get regular operand indices in the same order as specified	---	3346	// Get regular operand indices in the same order as specified	---
3347	// in the instruction (but append mandatory literals to the end).	---	3347	// in the instruction (but append mandatory literals to the end).	---
3348	static OperandIndices getSrcOperandIndices(unsigned Opcode,	0	3348	static OperandIndices getSrcOperandIndices(unsigned Opcode,	0
3349	bool AddMandatoryLiterals = false) {	---	3349	bool AddMandatoryLiterals = false) {	---
3350		---	3350		---
3351	int16_t ImmIdx =	0	3351	int16_t ImmIdx =	0
3352	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;	0	3352	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::imm) : -1;	0
3353		---	3353		---
3354	if (isVOPD(Opcode)) {	0	3354	if (isVOPD(Opcode)) {	0
3355	int16_t ImmDeferredIdx =	0	3355	int16_t ImmDeferredIdx =	0
3356	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred)	0	3356	AddMandatoryLiterals ? getNamedOperandIdx(Opcode, OpName::immDeferred)	0
3357	: -1;	---	3357	: -1;	---
3358		---	3358		---
3359	return {getNamedOperandIdx(Opcode, OpName::src0X),	0	3359	return {getNamedOperandIdx(Opcode, OpName::src0X),	0
3360	getNamedOperandIdx(Opcode, OpName::vsrc1X),	0	3360	getNamedOperandIdx(Opcode, OpName::vsrc1X),	0
3361	getNamedOperandIdx(Opcode, OpName::src0Y),	0	3361	getNamedOperandIdx(Opcode, OpName::src0Y),	0
3362	getNamedOperandIdx(Opcode, OpName::vsrc1Y),	0	3362	getNamedOperandIdx(Opcode, OpName::vsrc1Y),	0
3363	ImmDeferredIdx,	---	3363	ImmDeferredIdx,	---
3364	ImmIdx};	0	3364	ImmIdx};	0
3365	}	---	3365	}	---
3366		---	3366		---
3367	return {getNamedOperandIdx(Opcode, OpName::src0),	0	3367	return {getNamedOperandIdx(Opcode, OpName::src0),	0
3368	getNamedOperandIdx(Opcode, OpName::src1),	0	3368	getNamedOperandIdx(Opcode, OpName::src1),	0
3369	getNamedOperandIdx(Opcode, OpName::src2), ImmIdx};	0	3369	getNamedOperandIdx(Opcode, OpName::src2), ImmIdx};	0
3370	}	---	3370	}	---
3371		---	3371		---
3372	bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {	0	3372	bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {	0
3373	const MCOperand &MO = Inst.getOperand(OpIdx);	0	3373	const MCOperand &MO = Inst.getOperand(OpIdx);	0
3374	if (MO.isImm()) {	0	3374	if (MO.isImm()) {	0
3375	return !isInlineConstant(Inst, OpIdx);	0	3375	return !isInlineConstant(Inst, OpIdx);	0
3376	} else if (MO.isReg()) {	0	3376	} else if (MO.isReg()) {	0
3377	auto Reg = MO.getReg();	0	3377	auto Reg = MO.getReg();	0
3378	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	3378	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3379	auto PReg = mc2PseudoReg(Reg);	0	3379	auto PReg = mc2PseudoReg(Reg);	0
3380	return isSGPR(PReg, TRI) && PReg != SGPR_NULL;	0	3380	return isSGPR(PReg, TRI) && PReg != SGPR_NULL;	0
3381	} else {	---	3381	} else {	---
3382	return true;	0	3382	return true;	0
3383	}	---	3383	}	---
3384	}	---	3384	}	---
3385		---	3385		---
3386	bool AMDGPUAsmParser::validateConstantBusLimitations(	0	3386	bool AMDGPUAsmParser::validateConstantBusLimitations(	0
3387	const MCInst &Inst, const OperandVector &Operands) {	---	3387	const MCInst &Inst, const OperandVector &Operands) {	---
3388	const unsigned Opcode = Inst.getOpcode();	0	3388	const unsigned Opcode = Inst.getOpcode();	0
3389	const MCInstrDesc &Desc = MII.get(Opcode);	0	3389	const MCInstrDesc &Desc = MII.get(Opcode);	0
3390	unsigned LastSGPR = AMDGPU::NoRegister;	0	3390	unsigned LastSGPR = AMDGPU::NoRegister;	0
3391	unsigned ConstantBusUseCount = 0;	0	3391	unsigned ConstantBusUseCount = 0;	0
3392	unsigned NumLiterals = 0;	0	3392	unsigned NumLiterals = 0;	0
3393	unsigned LiteralSize;	---	3393	unsigned LiteralSize;	---
3394		---	3394		---
3395	if (!(Desc.TSFlags &	0	3395	if (!(Desc.TSFlags &	0
3396	(SIInstrFlags::VOPC \| SIInstrFlags::VOP1 \| SIInstrFlags::VOP2 \|	---	3396	(SIInstrFlags::VOPC \| SIInstrFlags::VOP1 \| SIInstrFlags::VOP2 \|	---
3397	SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P \| SIInstrFlags::SDWA)) &&	0	3397	SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P \| SIInstrFlags::SDWA)) &&	0
3398	!isVOPD(Opcode))	0	3398	!isVOPD(Opcode))	0
3399	return true;	0	3399	return true;	0
3400		---	3400		---
3401	// Check special imm operands (used by madmk, etc)	---	3401	// Check special imm operands (used by madmk, etc)	---
3402	if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {	0	3402	if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {	0
3403	++NumLiterals;	0	3403	++NumLiterals;	0
3404	LiteralSize = 4;	0	3404	LiteralSize = 4;	0
3405	}	---	3405	}	---
3406		---	3406		---
3407	SmallDenseSet SGPRsUsed;	0	3407	SmallDenseSet SGPRsUsed;	0
3408	unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);	0	3408	unsigned SGPRUsed = findImplicitSGPRReadInVOP(Inst);	0
3409	if (SGPRUsed != AMDGPU::NoRegister) {	0	3409	if (SGPRUsed != AMDGPU::NoRegister) {	0
3410	SGPRsUsed.insert(SGPRUsed);	0	3410	SGPRsUsed.insert(SGPRUsed);	0
3411	++ConstantBusUseCount;	0	3411	++ConstantBusUseCount;	0
3412	}	---	3412	}	---
3413		---	3413		---
3414	OperandIndices OpIndices = getSrcOperandIndices(Opcode);	0	3414	OperandIndices OpIndices = getSrcOperandIndices(Opcode);	0
3415		---	3415		---
3416	for (int OpIdx : OpIndices) {	0	3416	for (int OpIdx : OpIndices) {	0
3417	if (OpIdx == -1)	0	3417	if (OpIdx == -1)	0
3418	continue;	0	3418	continue;	0
3419		---	3419		---
3420	const MCOperand &MO = Inst.getOperand(OpIdx);	0	3420	const MCOperand &MO = Inst.getOperand(OpIdx);	0
3421	if (usesConstantBus(Inst, OpIdx)) {	0	3421	if (usesConstantBus(Inst, OpIdx)) {	0
3422	if (MO.isReg()) {	0	3422	if (MO.isReg()) {	0
3423	LastSGPR = mc2PseudoReg(MO.getReg());	0	3423	LastSGPR = mc2PseudoReg(MO.getReg());	0
3424	// Pairs of registers with a partial intersections like these	---	3424	// Pairs of registers with a partial intersections like these	---
3425	// s0, s[0:1]	---	3425	// s0, s[0:1]	---
3426	// flat_scratch_lo, flat_scratch	---	3426	// flat_scratch_lo, flat_scratch	---
3427	// flat_scratch_lo, flat_scratch_hi	---	3427	// flat_scratch_lo, flat_scratch_hi	---
3428	// are theoretically valid but they are disabled anyway.	---	3428	// are theoretically valid but they are disabled anyway.	---
3429	// Note that this code mimics SIInstrInfo::verifyInstruction	---	3429	// Note that this code mimics SIInstrInfo::verifyInstruction	---
3430	if (SGPRsUsed.insert(LastSGPR).second) {	0	3430	if (SGPRsUsed.insert(LastSGPR).second) {	0
3431	++ConstantBusUseCount;	0	3431	++ConstantBusUseCount;	0
3432	}	---	3432	}	---
3433	} else { // Expression or a literal	---	3433	} else { // Expression or a literal	---
3434		---	3434		---
3435	if (Desc.operands()[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)	0	3435	if (Desc.operands()[OpIdx].OperandType == MCOI::OPERAND_IMMEDIATE)	0
3436	continue; // special operand like VINTERP attr_chan	0	3436	continue; // special operand like VINTERP attr_chan	0
3437		---	3437		---
3438	// An instruction may use only one literal.	---	3438	// An instruction may use only one literal.	---
3439	// This has been validated on the previous step.	---	3439	// This has been validated on the previous step.	---
3440	// See validateVOPLiteral.	---	3440	// See validateVOPLiteral.	---
3441	// This literal may be used as more than one operand.	---	3441	// This literal may be used as more than one operand.	---
3442	// If all these operands are of the same size,	---	3442	// If all these operands are of the same size,	---
3443	// this literal counts as one scalar value.	---	3443	// this literal counts as one scalar value.	---
3444	// Otherwise it counts as 2 scalar values.	---	3444	// Otherwise it counts as 2 scalar values.	---
3445	// See "GFX10 Shader Programming", section 3.6.2.3.	---	3445	// See "GFX10 Shader Programming", section 3.6.2.3.	---
3446		---	3446		---
3447	unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);	0	3447	unsigned Size = AMDGPU::getOperandSize(Desc, OpIdx);	0
3448	if (Size < 4)	0	3448	if (Size < 4)	0
3449	Size = 4;	0	3449	Size = 4;	0
3450		---	3450		---
3451	if (NumLiterals == 0) {	0	3451	if (NumLiterals == 0) {	0
3452	NumLiterals = 1;	0	3452	NumLiterals = 1;	0
3453	LiteralSize = Size;	0	3453	LiteralSize = Size;	0
3454	} else if (LiteralSize != Size) {	0	3454	} else if (LiteralSize != Size) {	0
3455	NumLiterals = 2;	0	3455	NumLiterals = 2;	0
3456	}	---	3456	}	---
3457	}	---	3457	}	---
3458	}	---	3458	}	---
3459	}	---	3459	}	---
3460	ConstantBusUseCount += NumLiterals;	0	3460	ConstantBusUseCount += NumLiterals;	0
3461		---	3461		---
3462	if (ConstantBusUseCount <= getConstantBusLimit(Opcode))	0	3462	if (ConstantBusUseCount <= getConstantBusLimit(Opcode))	0
3463	return true;	0	3463	return true;	0
3464		---	3464		---
3465	SMLoc LitLoc = getLitLoc(Operands);	0	3465	SMLoc LitLoc = getLitLoc(Operands);	0
3466	SMLoc RegLoc = getRegLoc(LastSGPR, Operands);	0	3466	SMLoc RegLoc = getRegLoc(LastSGPR, Operands);	0
3467	SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;	0	3467	SMLoc Loc = (LitLoc.getPointer() < RegLoc.getPointer()) ? RegLoc : LitLoc;	0
3468	Error(Loc, "invalid operand (violates constant bus restrictions)");	0	3468	Error(Loc, "invalid operand (violates constant bus restrictions)");	0
3469	return false;	0	3469	return false;	0
3470	}	0	3470	}	0
3471		---	3471		---
3472	bool AMDGPUAsmParser::validateVOPDRegBankConstraints(	0	3472	bool AMDGPUAsmParser::validateVOPDRegBankConstraints(	0
3473	const MCInst &Inst, const OperandVector &Operands) {	---	3473	const MCInst &Inst, const OperandVector &Operands) {	---
3474		---	3474		---
3475	const unsigned Opcode = Inst.getOpcode();	0	3475	const unsigned Opcode = Inst.getOpcode();	0
3476	if (!isVOPD(Opcode))	0	3476	if (!isVOPD(Opcode))	0
3477	return true;	0	3477	return true;	0
3478		---	3478		---
3479	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	3479	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3480		---	3480		---
3481	auto getVRegIdx = [&](unsigned, unsigned OperandIdx) {	0	3481	auto getVRegIdx = [&](unsigned, unsigned OperandIdx) {	0
3482	const MCOperand &Opr = Inst.getOperand(OperandIdx);	0	3482	const MCOperand &Opr = Inst.getOperand(OperandIdx);	0
3483	return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI))	0	3483	return (Opr.isReg() && !isSGPR(mc2PseudoReg(Opr.getReg()), TRI))	0
3484	? Opr.getReg()	0	3484	? Opr.getReg()	0
3485	: MCRegister::NoRegister;	0	3485	: MCRegister::NoRegister;	0
3486	};	0	3486	};	0
3487		---	3487		---
3488	const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);	0	3488	const auto &InstInfo = getVOPDInstInfo(Opcode, &MII);	0
3489	auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(getVRegIdx);	0	3489	auto InvalidCompOprIdx = InstInfo.getInvalidCompOperandIndex(getVRegIdx);	0
3490	if (!InvalidCompOprIdx)	0	3490	if (!InvalidCompOprIdx)	0
3491	return true;	0	3491	return true;	0
3492		---	3492		---
3493	auto CompOprIdx = *InvalidCompOprIdx;	0	3493	auto CompOprIdx = *InvalidCompOprIdx;	0
3494	auto ParsedIdx =	---	3494	auto ParsedIdx =	---
3495	std::max(InstInfo[VOPD::X].getIndexInParsedOperands(CompOprIdx),	0	3495	std::max(InstInfo[VOPD::X].getIndexInParsedOperands(CompOprIdx),	0
3496	InstInfo[VOPD::Y].getIndexInParsedOperands(CompOprIdx));	0	3496	InstInfo[VOPD::Y].getIndexInParsedOperands(CompOprIdx));	0
3497	assert(ParsedIdx > 0 && ParsedIdx < Operands.size());	0	3497	assert(ParsedIdx > 0 && ParsedIdx < Operands.size());	0
3498		---	3498		---
3499	auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();	0	3499	auto Loc = ((AMDGPUOperand &)*Operands[ParsedIdx]).getStartLoc();	0
3500	if (CompOprIdx == VOPD::Component::DST) {	0	3500	if (CompOprIdx == VOPD::Component::DST) {	0
3501	Error(Loc, "one dst register must be even and the other odd");	0	3501	Error(Loc, "one dst register must be even and the other odd");	0
3502	} else {	---	3502	} else {	---
3503	auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM;	0	3503	auto CompSrcIdx = CompOprIdx - VOPD::Component::DST_NUM;	0
3504	Error(Loc, Twine("src") + Twine(CompSrcIdx) +	0	3504	Error(Loc, Twine("src") + Twine(CompSrcIdx) +	0
3505	" operands must use different VGPR banks");	0	3505	" operands must use different VGPR banks");	0
3506	}	---	3506	}	---
3507		---	3507		---
3508	return false;	0	3508	return false;	0
3509	}	---	3509	}	---
3510		---	3510		---
3511	bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {	0	3511	bool AMDGPUAsmParser::validateIntClampSupported(const MCInst &Inst) {	0
3512		---	3512		---
3513	const unsigned Opc = Inst.getOpcode();	0	3513	const unsigned Opc = Inst.getOpcode();	0
3514	const MCInstrDesc &Desc = MII.get(Opc);	0	3514	const MCInstrDesc &Desc = MII.get(Opc);	0
3515		---	3515		---
3516	if ((Desc.TSFlags & SIInstrFlags::IntClamp) != 0 && !hasIntClamp()) {	0	3516	if ((Desc.TSFlags & SIInstrFlags::IntClamp) != 0 && !hasIntClamp()) {	0
3517	int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);	0	3517	int ClampIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp);	0
3518	assert(ClampIdx != -1);	0	3518	assert(ClampIdx != -1);	0
3519	return Inst.getOperand(ClampIdx).getImm() == 0;	0	3519	return Inst.getOperand(ClampIdx).getImm() == 0;	0
3520	}	---	3520	}	---
3521		---	3521		---
3522	return true;	0	3522	return true;	0
3523	}	---	3523	}	---
3524		---	3524		---
3525	bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,	0	3525	bool AMDGPUAsmParser::validateMIMGDataSize(const MCInst &Inst,	0
3526	const SMLoc &IDLoc) {	---	3526	const SMLoc &IDLoc) {	---
3527		---	3527		---
3528	const unsigned Opc = Inst.getOpcode();	0	3528	const unsigned Opc = Inst.getOpcode();	0
3529	const MCInstrDesc &Desc = MII.get(Opc);	0	3529	const MCInstrDesc &Desc = MII.get(Opc);	0
3530		---	3530		---
3531	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0	3531	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3532	return true;	0	3532	return true;	0
3533		---	3533		---
3534	int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);	0	3534	int VDataIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdata);	0
3535	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0	3535	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0
3536	int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);	0	3536	int TFEIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::tfe);	0
3537		---	3537		---
3538	assert(VDataIdx != -1);	0	3538	assert(VDataIdx != -1);	0
3539		---	3539		---
3540	if ((DMaskIdx == -1 \|\| TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray	0	3540	if ((DMaskIdx == -1 \|\| TFEIdx == -1) && isGFX10_AEncoding()) // intersect_ray	0
3541	return true;	0	3541	return true;	0
3542		---	3542		---
3543	unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);	0	3543	unsigned VDataSize = AMDGPU::getRegOperandSize(getMRI(), Desc, VDataIdx);	0
3544	unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;	0	3544	unsigned TFESize = (TFEIdx != -1 && Inst.getOperand(TFEIdx).getImm()) ? 1 : 0;	0
3545	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0	3545	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0
3546	if (DMask == 0)	0	3546	if (DMask == 0)	0
3547	DMask = 1;	0	3547	DMask = 1;	0
3548		---	3548		---
3549	bool IsPackedD16 = false;	0	3549	bool IsPackedD16 = false;	0
3550	unsigned DataSize =	---	3550	unsigned DataSize =	---
3551	(Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask);	0	3551	(Desc.TSFlags & SIInstrFlags::Gather4) ? 4 : llvm::popcount(DMask);	0
3552	if (hasPackedD16()) {	0	3552	if (hasPackedD16()) {	0
3553	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	0	3553	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	0
3554	IsPackedD16 = D16Idx >= 0;	0	3554	IsPackedD16 = D16Idx >= 0;	0
3555	if (IsPackedD16 && Inst.getOperand(D16Idx).getImm())	0	3555	if (IsPackedD16 && Inst.getOperand(D16Idx).getImm())	0
3556	DataSize = (DataSize + 1) / 2;	0	3556	DataSize = (DataSize + 1) / 2;	0
3557	}	---	3557	}	---
3558		---	3558		---
3559	if ((VDataSize / 4) == DataSize + TFESize)	0	3559	if ((VDataSize / 4) == DataSize + TFESize)	0
3560	return true;	0	3560	return true;	0
3561		---	3561		---
3562	StringRef Modifiers;	0	3562	StringRef Modifiers;	0
3563	if (isGFX90A())	0	3563	if (isGFX90A())	0
3564	Modifiers = IsPackedD16 ? "dmask and d16" : "dmask";	0	3564	Modifiers = IsPackedD16 ? "dmask and d16" : "dmask";	0
3565	else	---	3565	else	---
3566	Modifiers = IsPackedD16 ? "dmask, d16 and tfe" : "dmask and tfe";	0	3566	Modifiers = IsPackedD16 ? "dmask, d16 and tfe" : "dmask and tfe";	0
3567		---	3567		---
3568	Error(IDLoc, Twine("image data size does not match ") + Modifiers);	0	3568	Error(IDLoc, Twine("image data size does not match ") + Modifiers);	0
3569	return false;	0	3569	return false;	0
3570	}	---	3570	}	---
3571		---	3571		---
3572	bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,	0	3572	bool AMDGPUAsmParser::validateMIMGAddrSize(const MCInst &Inst,	0
3573	const SMLoc &IDLoc) {	---	3573	const SMLoc &IDLoc) {	---
3574	const unsigned Opc = Inst.getOpcode();	0	3574	const unsigned Opc = Inst.getOpcode();	0
3575	const MCInstrDesc &Desc = MII.get(Opc);	0	3575	const MCInstrDesc &Desc = MII.get(Opc);	0
3576		---	3576		---
3577	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 \|\| !isGFX10Plus())	0	3577	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0 \|\| !isGFX10Plus())	0
3578	return true;	0	3578	return true;	0
3579		---	3579		---
3580	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	0	3580	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	0
3581		---	3581		---
3582	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	---	3582	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	---
3583	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	0	3583	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	0
3584	int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);	0	3584	int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0);	0
3585	int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);	0	3585	int SrsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc);	0
3586	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	0	3586	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	0
3587	int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);	0	3587	int A16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::a16);	0
3588		---	3588		---
3589	assert(VAddr0Idx != -1);	0	3589	assert(VAddr0Idx != -1);	0
3590	assert(SrsrcIdx != -1);	0	3590	assert(SrsrcIdx != -1);	0
3591	assert(SrsrcIdx > VAddr0Idx);	0	3591	assert(SrsrcIdx > VAddr0Idx);	0
3592		---	3592		---
3593	bool IsA16 = Inst.getOperand(A16Idx).getImm();	0	3593	bool IsA16 = Inst.getOperand(A16Idx).getImm();	0
3594	if (BaseOpcode->BVH) {	0	3594	if (BaseOpcode->BVH) {	0
3595	if (IsA16 == BaseOpcode->A16)	0	3595	if (IsA16 == BaseOpcode->A16)	0
3596	return true;	0	3596	return true;	0
3597	Error(IDLoc, "image address size does not match a16");	0	3597	Error(IDLoc, "image address size does not match a16");	0
3598	return false;	0	3598	return false;	0
3599	}	---	3599	}	---
3600		---	3600		---
3601	unsigned Dim = Inst.getOperand(DimIdx).getImm();	0	3601	unsigned Dim = Inst.getOperand(DimIdx).getImm();	0
3602	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	0	3602	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	0
3603	bool IsNSA = SrsrcIdx - VAddr0Idx > 1;	0	3603	bool IsNSA = SrsrcIdx - VAddr0Idx > 1;	0
3604	unsigned ActualAddrSize =	---	3604	unsigned ActualAddrSize =	---
3605	IsNSA ? SrsrcIdx - VAddr0Idx	0	3605	IsNSA ? SrsrcIdx - VAddr0Idx	0
3606	: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;	0	3606	: AMDGPU::getRegOperandSize(getMRI(), Desc, VAddr0Idx) / 4;	0
3607		---	3607		---
3608	unsigned ExpectedAddrSize =	---	3608	unsigned ExpectedAddrSize =	---
3609	AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());	0	3609	AMDGPU::getAddrSizeMIMGOp(BaseOpcode, DimInfo, IsA16, hasG16());	0
3610		---	3610		---
3611	if (IsNSA) {	0	3611	if (IsNSA) {	0
3612	if (hasPartialNSAEncoding() && ExpectedAddrSize > getNSAMaxSize()) {	0	3612	if (hasPartialNSAEncoding() && ExpectedAddrSize > getNSAMaxSize()) {	0
3613	int VAddrLastIdx = SrsrcIdx - 1;	0	3613	int VAddrLastIdx = SrsrcIdx - 1;	0
3614	unsigned VAddrLastSize =	---	3614	unsigned VAddrLastSize =	---
3615	AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;	0	3615	AMDGPU::getRegOperandSize(getMRI(), Desc, VAddrLastIdx) / 4;	0
3616		---	3616		---
3617	ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;	0	3617	ActualAddrSize = VAddrLastIdx - VAddr0Idx + VAddrLastSize;	0
3618	}	---	3618	}	---
3619	} else {	---	3619	} else {	---
3620	if (ExpectedAddrSize > 12)	0	3620	if (ExpectedAddrSize > 12)	0
3621	ExpectedAddrSize = 16;	0	3621	ExpectedAddrSize = 16;	0
3622		---	3622		---
3623	// Allow oversized 8 VGPR vaddr when only 5/6/7 VGPRs are required.	---	3623	// Allow oversized 8 VGPR vaddr when only 5/6/7 VGPRs are required.	---
3624	// This provides backward compatibility for assembly created	---	3624	// This provides backward compatibility for assembly created	---
3625	// before 160b/192b/224b types were directly supported.	---	3625	// before 160b/192b/224b types were directly supported.	---
3626	if (ActualAddrSize == 8 && (ExpectedAddrSize >= 5 && ExpectedAddrSize <= 7))	0	3626	if (ActualAddrSize == 8 && (ExpectedAddrSize >= 5 && ExpectedAddrSize <= 7))	0
3627	return true;	0	3627	return true;	0
3628	}	---	3628	}	---
3629		---	3629		---
3630	if (ActualAddrSize == ExpectedAddrSize)	0	3630	if (ActualAddrSize == ExpectedAddrSize)	0
3631	return true;	0	3631	return true;	0
3632		---	3632		---
3633	Error(IDLoc, "image address size does not match dim and a16");	0	3633	Error(IDLoc, "image address size does not match dim and a16");	0
3634	return false;	0	3634	return false;	0
3635	}	---	3635	}	---
3636		---	3636		---
3637	bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {	0	3637	bool AMDGPUAsmParser::validateMIMGAtomicDMask(const MCInst &Inst) {	0
3638		---	3638		---
3639	const unsigned Opc = Inst.getOpcode();	0	3639	const unsigned Opc = Inst.getOpcode();	0
3640	const MCInstrDesc &Desc = MII.get(Opc);	0	3640	const MCInstrDesc &Desc = MII.get(Opc);	0
3641		---	3641		---
3642	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0	3642	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3643	return true;	0	3643	return true;	0
3644	if (!Desc.mayLoad() \|\| !Desc.mayStore())	0	3644	if (!Desc.mayLoad() \|\| !Desc.mayStore())	0
3645	return true; // Not atomic	0	3645	return true; // Not atomic	0
3646		---	3646		---
3647	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0	3647	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0
3648	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0	3648	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0
3649		---	3649		---
3650	// This is an incomplete check because image_atomic_cmpswap	---	3650	// This is an incomplete check because image_atomic_cmpswap	---
3651	// may only use 0x3 and 0xf while other atomic operations	---	3651	// may only use 0x3 and 0xf while other atomic operations	---
3652	// may use 0x1 and 0x3. However these limitations are	---	3652	// may use 0x1 and 0x3. However these limitations are	---
3653	// verified when we check that dmask matches dst size.	---	3653	// verified when we check that dmask matches dst size.	---
3654	return DMask == 0x1 \|\| DMask == 0x3 \|\| DMask == 0xf;	0	3654	return DMask == 0x1 \|\| DMask == 0x3 \|\| DMask == 0xf;	0
3655	}	---	3655	}	---
3656		---	3656		---
3657	bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {	0	3657	bool AMDGPUAsmParser::validateMIMGGatherDMask(const MCInst &Inst) {	0
3658		---	3658		---
3659	const unsigned Opc = Inst.getOpcode();	0	3659	const unsigned Opc = Inst.getOpcode();	0
3660	const MCInstrDesc &Desc = MII.get(Opc);	0	3660	const MCInstrDesc &Desc = MII.get(Opc);	0
3661		---	3661		---
3662	if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0)	0	3662	if ((Desc.TSFlags & SIInstrFlags::Gather4) == 0)	0
3663	return true;	0	3663	return true;	0
3664		---	3664		---
3665	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0	3665	int DMaskIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dmask);	0
3666	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0	3666	unsigned DMask = Inst.getOperand(DMaskIdx).getImm() & 0xf;	0
3667		---	3667		---
3668	// GATHER4 instructions use dmask in a different fashion compared to	---	3668	// GATHER4 instructions use dmask in a different fashion compared to	---
3669	// other MIMG instructions. The only useful DMASK values are	---	3669	// other MIMG instructions. The only useful DMASK values are	---
3670	// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns	---	3670	// 1=red, 2=green, 4=blue, 8=alpha. (e.g. 1 returns	---
3671	// (red,red,red,red) etc.) The ISA document doesn't mention	---	3671	// (red,red,red,red) etc.) The ISA document doesn't mention	---
3672	// this.	---	3672	// this.	---
3673	return DMask == 0x1 \|\| DMask == 0x2 \|\| DMask == 0x4 \|\| DMask == 0x8;	0	3673	return DMask == 0x1 \|\| DMask == 0x2 \|\| DMask == 0x4 \|\| DMask == 0x8;	0
3674	}	---	3674	}	---
3675		---	3675		---
3676	bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {	0	3676	bool AMDGPUAsmParser::validateMIMGMSAA(const MCInst &Inst) {	0
3677	const unsigned Opc = Inst.getOpcode();	0	3677	const unsigned Opc = Inst.getOpcode();	0
3678	const MCInstrDesc &Desc = MII.get(Opc);	0	3678	const MCInstrDesc &Desc = MII.get(Opc);	0
3679		---	3679		---
3680	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0	3680	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3681	return true;	0	3681	return true;	0
3682		---	3682		---
3683	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	0	3683	const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(Opc);	0
3684	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	---	3684	const AMDGPU::MIMGBaseOpcodeInfo *BaseOpcode =	---
3685	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	0	3685	AMDGPU::getMIMGBaseOpcodeInfo(Info->BaseOpcode);	0
3686		---	3686		---
3687	if (!BaseOpcode->MSAA)	0	3687	if (!BaseOpcode->MSAA)	0
3688	return true;	0	3688	return true;	0
3689		---	3689		---
3690	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	0	3690	int DimIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dim);	0
3691	assert(DimIdx != -1);	0	3691	assert(DimIdx != -1);	0
3692		---	3692		---
3693	unsigned Dim = Inst.getOperand(DimIdx).getImm();	0	3693	unsigned Dim = Inst.getOperand(DimIdx).getImm();	0
3694	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	0	3694	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByEncoding(Dim);	0
3695		---	3695		---
3696	return DimInfo->MSAA;	0	3696	return DimInfo->MSAA;	0
3697	}	---	3697	}	---
3698		---	3698		---
3699	static bool IsMovrelsSDWAOpcode(const unsigned Opcode)	0	3699	static bool IsMovrelsSDWAOpcode(const unsigned Opcode)	0
3700	{	---	3700	{	---
3701	switch (Opcode) {	0	3701	switch (Opcode) {	0
3702	case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:	0	3702	case AMDGPU::V_MOVRELS_B32_sdwa_gfx10:	0
3703	case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:	---	3703	case AMDGPU::V_MOVRELSD_B32_sdwa_gfx10:	---
3704	case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:	---	3704	case AMDGPU::V_MOVRELSD_2_B32_sdwa_gfx10:	---
3705	return true;	0	3705	return true;	0
3706	default:	0	3706	default:	0
3707	return false;	0	3707	return false;	0
3708	}	---	3708	}	---
3709	}	---	3709	}	---
3710		---	3710		---
3711	// movrels* opcodes should only allow VGPRS as src0.	---	3711	// movrels* opcodes should only allow VGPRS as src0.	---
3712	// This is specified in .td description for vop1/vop3,	---	3712	// This is specified in .td description for vop1/vop3,	---
3713	// but sdwa is handled differently. See isSDWAOperand.	---	3713	// but sdwa is handled differently. See isSDWAOperand.	---
3714	bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,	0	3714	bool AMDGPUAsmParser::validateMovrels(const MCInst &Inst,	0
3715	const OperandVector &Operands) {	---	3715	const OperandVector &Operands) {	---
3716		---	3716		---
3717	const unsigned Opc = Inst.getOpcode();	0	3717	const unsigned Opc = Inst.getOpcode();	0
3718	const MCInstrDesc &Desc = MII.get(Opc);	0	3718	const MCInstrDesc &Desc = MII.get(Opc);	0
3719		---	3719		---
3720	if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 \|\| !IsMovrelsSDWAOpcode(Opc))	0	3720	if ((Desc.TSFlags & SIInstrFlags::SDWA) == 0 \|\| !IsMovrelsSDWAOpcode(Opc))	0
3721	return true;	0	3721	return true;	0
3722		---	3722		---
3723	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0	3723	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0
3724	assert(Src0Idx != -1);	0	3724	assert(Src0Idx != -1);	0
3725		---	3725		---
3726	SMLoc ErrLoc;	0	3726	SMLoc ErrLoc;	0
3727	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	0	3727	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	0
3728	if (Src0.isReg()) {	0	3728	if (Src0.isReg()) {	0
3729	auto Reg = mc2PseudoReg(Src0.getReg());	0	3729	auto Reg = mc2PseudoReg(Src0.getReg());	0
3730	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	3730	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3731	if (!isSGPR(Reg, TRI))	0	3731	if (!isSGPR(Reg, TRI))	0
3732	return true;	0	3732	return true;	0
3733	ErrLoc = getRegLoc(Reg, Operands);	0	3733	ErrLoc = getRegLoc(Reg, Operands);	0
3734	} else {	---	3734	} else {	---
3735	ErrLoc = getConstLoc(Operands);	0	3735	ErrLoc = getConstLoc(Operands);	0
3736	}	---	3736	}	---
3737		---	3737		---
3738	Error(ErrLoc, "source operand must be a VGPR");	0	3738	Error(ErrLoc, "source operand must be a VGPR");	0
3739	return false;	0	3739	return false;	0
3740	}	---	3740	}	---
3741		---	3741		---
3742	bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,	0	3742	bool AMDGPUAsmParser::validateMAIAccWrite(const MCInst &Inst,	0
3743	const OperandVector &Operands) {	---	3743	const OperandVector &Operands) {	---
3744		---	3744		---
3745	const unsigned Opc = Inst.getOpcode();	0	3745	const unsigned Opc = Inst.getOpcode();	0
3746		---	3746		---
3747	if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)	0	3747	if (Opc != AMDGPU::V_ACCVGPR_WRITE_B32_vi)	0
3748	return true;	0	3748	return true;	0
3749		---	3749		---
3750	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0	3750	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0
3751	assert(Src0Idx != -1);	0	3751	assert(Src0Idx != -1);	0
3752		---	3752		---
3753	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	0	3753	const MCOperand &Src0 = Inst.getOperand(Src0Idx);	0
3754	if (!Src0.isReg())	0	3754	if (!Src0.isReg())	0
3755	return true;	0	3755	return true;	0
3756		---	3756		---
3757	auto Reg = mc2PseudoReg(Src0.getReg());	0	3757	auto Reg = mc2PseudoReg(Src0.getReg());	0
3758	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	3758	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3759	if (!isGFX90A() && isSGPR(Reg, TRI)) {	0	3759	if (!isGFX90A() && isSGPR(Reg, TRI)) {	0
3760	Error(getRegLoc(Reg, Operands),	0	3760	Error(getRegLoc(Reg, Operands),	0
3761	"source operand must be either a VGPR or an inline constant");	---	3761	"source operand must be either a VGPR or an inline constant");	---
3762	return false;	0	3762	return false;	0
3763	}	---	3763	}	---
3764		---	3764		---
3765	return true;	0	3765	return true;	0
3766	}	---	3766	}	---
3767		---	3767		---
3768	bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,	0	3768	bool AMDGPUAsmParser::validateMAISrc2(const MCInst &Inst,	0
3769	const OperandVector &Operands) {	---	3769	const OperandVector &Operands) {	---
3770	unsigned Opcode = Inst.getOpcode();	0	3770	unsigned Opcode = Inst.getOpcode();	0
3771	const MCInstrDesc &Desc = MII.get(Opcode);	0	3771	const MCInstrDesc &Desc = MII.get(Opcode);	0
3772		---	3772		---
3773	if (!(Desc.TSFlags & SIInstrFlags::IsMAI) \|\|	0	3773	if (!(Desc.TSFlags & SIInstrFlags::IsMAI) \|\|	0
3774	!getFeatureBits()[FeatureMFMAInlineLiteralBug])	0	3774	!getFeatureBits()[FeatureMFMAInlineLiteralBug])	0
3775	return true;	0	3775	return true;	0
3776		---	3776		---
3777	const int Src2Idx = getNamedOperandIdx(Opcode, OpName::src2);	0	3777	const int Src2Idx = getNamedOperandIdx(Opcode, OpName::src2);	0
3778	if (Src2Idx == -1)	0	3778	if (Src2Idx == -1)	0
3779	return true;	0	3779	return true;	0
3780		---	3780		---
3781	if (Inst.getOperand(Src2Idx).isImm() && isInlineConstant(Inst, Src2Idx)) {	0	3781	if (Inst.getOperand(Src2Idx).isImm() && isInlineConstant(Inst, Src2Idx)) {	0
3782	Error(getConstLoc(Operands),	0	3782	Error(getConstLoc(Operands),	0
3783	"inline constants are not allowed for this operand");	---	3783	"inline constants are not allowed for this operand");	---
3784	return false;	0	3784	return false;	0
3785	}	---	3785	}	---
3786		---	3786		---
3787	return true;	0	3787	return true;	0
3788	}	---	3788	}	---
3789		---	3789		---
3790	bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,	0	3790	bool AMDGPUAsmParser::validateMFMA(const MCInst &Inst,	0
3791	const OperandVector &Operands) {	---	3791	const OperandVector &Operands) {	---
3792	const unsigned Opc = Inst.getOpcode();	0	3792	const unsigned Opc = Inst.getOpcode();	0
3793	const MCInstrDesc &Desc = MII.get(Opc);	0	3793	const MCInstrDesc &Desc = MII.get(Opc);	0
3794		---	3794		---
3795	if ((Desc.TSFlags & SIInstrFlags::IsMAI) == 0)	0	3795	if ((Desc.TSFlags & SIInstrFlags::IsMAI) == 0)	0
3796	return true;	0	3796	return true;	0
3797		---	3797		---
3798	const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);	0	3798	const int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);	0
3799	if (Src2Idx == -1)	0	3799	if (Src2Idx == -1)	0
3800	return true;	0	3800	return true;	0
3801		---	3801		---
3802	const MCOperand &Src2 = Inst.getOperand(Src2Idx);	0	3802	const MCOperand &Src2 = Inst.getOperand(Src2Idx);	0
3803	if (!Src2.isReg())	0	3803	if (!Src2.isReg())	0
3804	return true;	0	3804	return true;	0
3805		---	3805		---
3806	MCRegister Src2Reg = Src2.getReg();	0	3806	MCRegister Src2Reg = Src2.getReg();	0
3807	MCRegister DstReg = Inst.getOperand(0).getReg();	0	3807	MCRegister DstReg = Inst.getOperand(0).getReg();	0
3808	if (Src2Reg == DstReg)	0	3808	if (Src2Reg == DstReg)	0
3809	return true;	0	3809	return true;	0
3810		---	3810		---
3811	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0	3811	const MCRegisterInfo *TRI = getContext().getRegisterInfo();	0
3812	if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)	0	3812	if (TRI->getRegClass(Desc.operands()[0].RegClass).getSizeInBits() <= 128)	0
3813	return true;	0	3813	return true;	0
3814		---	3814		---
3815	if (TRI->regsOverlap(Src2Reg, DstReg)) {	0	3815	if (TRI->regsOverlap(Src2Reg, DstReg)) {	0
3816	Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),	0	3816	Error(getRegLoc(mc2PseudoReg(Src2Reg), Operands),	0
3817	"source 2 operand must not partially overlap with dst");	---	3817	"source 2 operand must not partially overlap with dst");	---
3818	return false;	0	3818	return false;	0
3819	}	---	3819	}	---
3820		---	3820		---
3821	return true;	0	3821	return true;	0
3822	}	---	3822	}	---
3823		---	3823		---
3824	bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {	0	3824	bool AMDGPUAsmParser::validateDivScale(const MCInst &Inst) {	0
3825	switch (Inst.getOpcode()) {	0	3825	switch (Inst.getOpcode()) {	0
3826	default:	0	3826	default:	0
3827	return true;	0	3827	return true;	0
3828	case V_DIV_SCALE_F32_gfx6_gfx7:	0	3828	case V_DIV_SCALE_F32_gfx6_gfx7:	0
3829	case V_DIV_SCALE_F32_vi:	---	3829	case V_DIV_SCALE_F32_vi:	---
3830	case V_DIV_SCALE_F32_gfx10:	---	3830	case V_DIV_SCALE_F32_gfx10:	---
3831	case V_DIV_SCALE_F64_gfx6_gfx7:	---	3831	case V_DIV_SCALE_F64_gfx6_gfx7:	---
3832	case V_DIV_SCALE_F64_vi:	---	3832	case V_DIV_SCALE_F64_vi:	---
3833	case V_DIV_SCALE_F64_gfx10:	---	3833	case V_DIV_SCALE_F64_gfx10:	---
3834	break;	0	3834	break;	0
3835	}	---	3835	}	---
3836		---	3836		---
3837	// TODO: Check that src0 = src1 or src2.	---	3837	// TODO: Check that src0 = src1 or src2.	---
3838		---	3838		---
3839	for (auto Name : {AMDGPU::OpName::src0_modifiers,	0	3839	for (auto Name : {AMDGPU::OpName::src0_modifiers,	0
3840	AMDGPU::OpName::src2_modifiers,	---	3840	AMDGPU::OpName::src2_modifiers,	---
3841	AMDGPU::OpName::src2_modifiers}) {	0	3841	AMDGPU::OpName::src2_modifiers}) {	0
3842	if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))	0	3842	if (Inst.getOperand(AMDGPU::getNamedOperandIdx(Inst.getOpcode(), Name))	0
3843	.getImm() &	0	3843	.getImm() &	0
3844	SISrcMods::ABS) {	---	3844	SISrcMods::ABS) {	---
3845	return false;	0	3845	return false;	0
3846	}	---	3846	}	---
3847	}	---	3847	}	---
3848		---	3848		---
3849	return true;	0	3849	return true;	0
3850	}	---	3850	}	---
3851		---	3851		---
3852	bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {	0	3852	bool AMDGPUAsmParser::validateMIMGD16(const MCInst &Inst) {	0
3853		---	3853		---
3854	const unsigned Opc = Inst.getOpcode();	0	3854	const unsigned Opc = Inst.getOpcode();	0
3855	const MCInstrDesc &Desc = MII.get(Opc);	0	3855	const MCInstrDesc &Desc = MII.get(Opc);	0
3856		---	3856		---
3857	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0	3857	if ((Desc.TSFlags & SIInstrFlags::MIMG) == 0)	0
3858	return true;	0	3858	return true;	0
3859		---	3859		---
3860	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	0	3860	int D16Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::d16);	0
3861	if (D16Idx >= 0 && Inst.getOperand(D16Idx).getImm()) {	0	3861	if (D16Idx >= 0 && Inst.getOperand(D16Idx).getImm()) {	0
3862	if (isCI() \|\| isSI())	0	3862	if (isCI() \|\| isSI())	0
3863	return false;	0	3863	return false;	0
3864	}	---	3864	}	---
3865		---	3865		---
3866	return true;	0	3866	return true;	0
3867	}	---	3867	}	---
3868		---	3868		---
3869	static bool IsRevOpcode(const unsigned Opcode)	0	3869	static bool IsRevOpcode(const unsigned Opcode)	0
3870	{	---	3870	{	---
3871	switch (Opcode) {	0	3871	switch (Opcode) {	0
3872	case AMDGPU::V_SUBREV_F32_e32:	0	3872	case AMDGPU::V_SUBREV_F32_e32:	0
3873	case AMDGPU::V_SUBREV_F32_e64:	---	3873	case AMDGPU::V_SUBREV_F32_e64:	---
3874	case AMDGPU::V_SUBREV_F32_e32_gfx10:	---	3874	case AMDGPU::V_SUBREV_F32_e32_gfx10:	---
3875	case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:	---	3875	case AMDGPU::V_SUBREV_F32_e32_gfx6_gfx7:	---
3876	case AMDGPU::V_SUBREV_F32_e32_vi:	---	3876	case AMDGPU::V_SUBREV_F32_e32_vi:	---
3877	case AMDGPU::V_SUBREV_F32_e64_gfx10:	---	3877	case AMDGPU::V_SUBREV_F32_e64_gfx10:	---
3878	case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:	---	3878	case AMDGPU::V_SUBREV_F32_e64_gfx6_gfx7:	---
3879	case AMDGPU::V_SUBREV_F32_e64_vi:	---	3879	case AMDGPU::V_SUBREV_F32_e64_vi:	---
3880		---	3880		---
3881	case AMDGPU::V_SUBREV_CO_U32_e32:	---	3881	case AMDGPU::V_SUBREV_CO_U32_e32:	---
3882	case AMDGPU::V_SUBREV_CO_U32_e64:	---	3882	case AMDGPU::V_SUBREV_CO_U32_e64:	---
3883	case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:	---	3883	case AMDGPU::V_SUBREV_I32_e32_gfx6_gfx7:	---
3884	case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:	---	3884	case AMDGPU::V_SUBREV_I32_e64_gfx6_gfx7:	---
3885		---	3885		---
3886	case AMDGPU::V_SUBBREV_U32_e32:	---	3886	case AMDGPU::V_SUBBREV_U32_e32:	---
3887	case AMDGPU::V_SUBBREV_U32_e64:	---	3887	case AMDGPU::V_SUBBREV_U32_e64:	---
3888	case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:	---	3888	case AMDGPU::V_SUBBREV_U32_e32_gfx6_gfx7:	---
3889	case AMDGPU::V_SUBBREV_U32_e32_vi:	---	3889	case AMDGPU::V_SUBBREV_U32_e32_vi:	---
3890	case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:	---	3890	case AMDGPU::V_SUBBREV_U32_e64_gfx6_gfx7:	---
3891	case AMDGPU::V_SUBBREV_U32_e64_vi:	---	3891	case AMDGPU::V_SUBBREV_U32_e64_vi:	---
3892		---	3892		---
3893	case AMDGPU::V_SUBREV_U32_e32:	---	3893	case AMDGPU::V_SUBREV_U32_e32:	---
3894	case AMDGPU::V_SUBREV_U32_e64:	---	3894	case AMDGPU::V_SUBREV_U32_e64:	---
3895	case AMDGPU::V_SUBREV_U32_e32_gfx9:	---	3895	case AMDGPU::V_SUBREV_U32_e32_gfx9:	---
3896	case AMDGPU::V_SUBREV_U32_e32_vi:	---	3896	case AMDGPU::V_SUBREV_U32_e32_vi:	---
3897	case AMDGPU::V_SUBREV_U32_e64_gfx9:	---	3897	case AMDGPU::V_SUBREV_U32_e64_gfx9:	---
3898	case AMDGPU::V_SUBREV_U32_e64_vi:	---	3898	case AMDGPU::V_SUBREV_U32_e64_vi:	---
3899		---	3899		---
3900	case AMDGPU::V_SUBREV_F16_e32:	---	3900	case AMDGPU::V_SUBREV_F16_e32:	---
3901	case AMDGPU::V_SUBREV_F16_e64:	---	3901	case AMDGPU::V_SUBREV_F16_e64:	---
3902	case AMDGPU::V_SUBREV_F16_e32_gfx10:	---	3902	case AMDGPU::V_SUBREV_F16_e32_gfx10:	---
3903	case AMDGPU::V_SUBREV_F16_e32_vi:	---	3903	case AMDGPU::V_SUBREV_F16_e32_vi:	---
3904	case AMDGPU::V_SUBREV_F16_e64_gfx10:	---	3904	case AMDGPU::V_SUBREV_F16_e64_gfx10:	---
3905	case AMDGPU::V_SUBREV_F16_e64_vi:	---	3905	case AMDGPU::V_SUBREV_F16_e64_vi:	---
3906		---	3906		---
3907	case AMDGPU::V_SUBREV_U16_e32:	---	3907	case AMDGPU::V_SUBREV_U16_e32:	---
3908	case AMDGPU::V_SUBREV_U16_e64:	---	3908	case AMDGPU::V_SUBREV_U16_e64:	---
3909	case AMDGPU::V_SUBREV_U16_e32_vi:	---	3909	case AMDGPU::V_SUBREV_U16_e32_vi:	---
3910	case AMDGPU::V_SUBREV_U16_e64_vi:	---	3910	case AMDGPU::V_SUBREV_U16_e64_vi:	---
3911		---	3911		---
3912	case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:	---	3912	case AMDGPU::V_SUBREV_CO_U32_e32_gfx9:	---
3913	case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:	---	3913	case AMDGPU::V_SUBREV_CO_U32_e64_gfx10:	---
3914	case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:	---	3914	case AMDGPU::V_SUBREV_CO_U32_e64_gfx9:	---
3915		---	3915		---
3916	case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:	---	3916	case AMDGPU::V_SUBBREV_CO_U32_e32_gfx9:	---
3917	case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:	---	3917	case AMDGPU::V_SUBBREV_CO_U32_e64_gfx9:	---
3918		---	3918		---
3919	case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:	---	3919	case AMDGPU::V_SUBREV_NC_U32_e32_gfx10:	---
3920	case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:	---	3920	case AMDGPU::V_SUBREV_NC_U32_e64_gfx10:	---
3921		---	3921		---
3922	case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:	---	3922	case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10:	---
3923	case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:	---	3923	case AMDGPU::V_SUBREV_CO_CI_U32_e64_gfx10:	---
3924		---	3924		---
3925	case AMDGPU::V_LSHRREV_B32_e32:	---	3925	case AMDGPU::V_LSHRREV_B32_e32:	---
3926	case AMDGPU::V_LSHRREV_B32_e64:	---	3926	case AMDGPU::V_LSHRREV_B32_e64:	---
3927	case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:	---	3927	case AMDGPU::V_LSHRREV_B32_e32_gfx6_gfx7:	---
3928	case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:	---	3928	case AMDGPU::V_LSHRREV_B32_e64_gfx6_gfx7:	---
3929	case AMDGPU::V_LSHRREV_B32_e32_vi:	---	3929	case AMDGPU::V_LSHRREV_B32_e32_vi:	---
3930	case AMDGPU::V_LSHRREV_B32_e64_vi:	---	3930	case AMDGPU::V_LSHRREV_B32_e64_vi:	---
3931	case AMDGPU::V_LSHRREV_B32_e32_gfx10:	---	3931	case AMDGPU::V_LSHRREV_B32_e32_gfx10:	---
3932	case AMDGPU::V_LSHRREV_B32_e64_gfx10:	---	3932	case AMDGPU::V_LSHRREV_B32_e64_gfx10:	---
3933		---	3933		---
3934	case AMDGPU::V_ASHRREV_I32_e32:	---	3934	case AMDGPU::V_ASHRREV_I32_e32:	---
3935	case AMDGPU::V_ASHRREV_I32_e64:	---	3935	case AMDGPU::V_ASHRREV_I32_e64:	---
3936	case AMDGPU::V_ASHRREV_I32_e32_gfx10:	---	3936	case AMDGPU::V_ASHRREV_I32_e32_gfx10:	---
3937	case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:	---	3937	case AMDGPU::V_ASHRREV_I32_e32_gfx6_gfx7:	---
3938	case AMDGPU::V_ASHRREV_I32_e32_vi:	---	3938	case AMDGPU::V_ASHRREV_I32_e32_vi:	---
3939	case AMDGPU::V_ASHRREV_I32_e64_gfx10:	---	3939	case AMDGPU::V_ASHRREV_I32_e64_gfx10:	---
3940	case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:	---	3940	case AMDGPU::V_ASHRREV_I32_e64_gfx6_gfx7:	---
3941	case AMDGPU::V_ASHRREV_I32_e64_vi:	---	3941	case AMDGPU::V_ASHRREV_I32_e64_vi:	---
3942		---	3942		---
3943	case AMDGPU::V_LSHLREV_B32_e32:	---	3943	case AMDGPU::V_LSHLREV_B32_e32:	---
3944	case AMDGPU::V_LSHLREV_B32_e64:	---	3944	case AMDGPU::V_LSHLREV_B32_e64:	---
3945	case AMDGPU::V_LSHLREV_B32_e32_gfx10:	---	3945	case AMDGPU::V_LSHLREV_B32_e32_gfx10:	---
3946	case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:	---	3946	case AMDGPU::V_LSHLREV_B32_e32_gfx6_gfx7:	---
3947	case AMDGPU::V_LSHLREV_B32_e32_vi:	---	3947	case AMDGPU::V_LSHLREV_B32_e32_vi:	---
3948	case AMDGPU::V_LSHLREV_B32_e64_gfx10:	---	3948	case AMDGPU::V_LSHLREV_B32_e64_gfx10:	---
3949	case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:	---	3949	case AMDGPU::V_LSHLREV_B32_e64_gfx6_gfx7:	---
3950	case AMDGPU::V_LSHLREV_B32_e64_vi:	---	3950	case AMDGPU::V_LSHLREV_B32_e64_vi:	---
3951		---	3951		---
3952	case AMDGPU::V_LSHLREV_B16_e32:	---	3952	case AMDGPU::V_LSHLREV_B16_e32:	---
3953	case AMDGPU::V_LSHLREV_B16_e64:	---	3953	case AMDGPU::V_LSHLREV_B16_e64:	---
3954	case AMDGPU::V_LSHLREV_B16_e32_vi:	---	3954	case AMDGPU::V_LSHLREV_B16_e32_vi:	---
3955	case AMDGPU::V_LSHLREV_B16_e64_vi:	---	3955	case AMDGPU::V_LSHLREV_B16_e64_vi:	---
3956	case AMDGPU::V_LSHLREV_B16_gfx10:	---	3956	case AMDGPU::V_LSHLREV_B16_gfx10:	---
3957		---	3957		---
3958	case AMDGPU::V_LSHRREV_B16_e32:	---	3958	case AMDGPU::V_LSHRREV_B16_e32:	---
3959	case AMDGPU::V_LSHRREV_B16_e64:	---	3959	case AMDGPU::V_LSHRREV_B16_e64:	---
3960	case AMDGPU::V_LSHRREV_B16_e32_vi:	---	3960	case AMDGPU::V_LSHRREV_B16_e32_vi:	---
3961	case AMDGPU::V_LSHRREV_B16_e64_vi:	---	3961	case AMDGPU::V_LSHRREV_B16_e64_vi:	---
3962	case AMDGPU::V_LSHRREV_B16_gfx10:	---	3962	case AMDGPU::V_LSHRREV_B16_gfx10:	---
3963		---	3963		---
3964	case AMDGPU::V_ASHRREV_I16_e32:	---	3964	case AMDGPU::V_ASHRREV_I16_e32:	---
3965	case AMDGPU::V_ASHRREV_I16_e64:	---	3965	case AMDGPU::V_ASHRREV_I16_e64:	---
3966	case AMDGPU::V_ASHRREV_I16_e32_vi:	---	3966	case AMDGPU::V_ASHRREV_I16_e32_vi:	---
3967	case AMDGPU::V_ASHRREV_I16_e64_vi:	---	3967	case AMDGPU::V_ASHRREV_I16_e64_vi:	---
3968	case AMDGPU::V_ASHRREV_I16_gfx10:	---	3968	case AMDGPU::V_ASHRREV_I16_gfx10:	---
3969		---	3969		---
3970	case AMDGPU::V_LSHLREV_B64_e64:	---	3970	case AMDGPU::V_LSHLREV_B64_e64:	---
3971	case AMDGPU::V_LSHLREV_B64_gfx10:	---	3971	case AMDGPU::V_LSHLREV_B64_gfx10:	---
3972	case AMDGPU::V_LSHLREV_B64_vi:	---	3972	case AMDGPU::V_LSHLREV_B64_vi:	---
3973		---	3973		---
3974	case AMDGPU::V_LSHRREV_B64_e64:	---	3974	case AMDGPU::V_LSHRREV_B64_e64:	---
3975	case AMDGPU::V_LSHRREV_B64_gfx10:	---	3975	case AMDGPU::V_LSHRREV_B64_gfx10:	---
3976	case AMDGPU::V_LSHRREV_B64_vi:	---	3976	case AMDGPU::V_LSHRREV_B64_vi:	---
3977		---	3977		---
3978	case AMDGPU::V_ASHRREV_I64_e64:	---	3978	case AMDGPU::V_ASHRREV_I64_e64:	---
3979	case AMDGPU::V_ASHRREV_I64_gfx10:	---	3979	case AMDGPU::V_ASHRREV_I64_gfx10:	---
3980	case AMDGPU::V_ASHRREV_I64_vi:	---	3980	case AMDGPU::V_ASHRREV_I64_vi:	---
3981		---	3981		---
3982	case AMDGPU::V_PK_LSHLREV_B16:	---	3982	case AMDGPU::V_PK_LSHLREV_B16:	---
3983	case AMDGPU::V_PK_LSHLREV_B16_gfx10:	---	3983	case AMDGPU::V_PK_LSHLREV_B16_gfx10:	---
3984	case AMDGPU::V_PK_LSHLREV_B16_vi:	---	3984	case AMDGPU::V_PK_LSHLREV_B16_vi:	---
3985		---	3985		---
3986	case AMDGPU::V_PK_LSHRREV_B16:	---	3986	case AMDGPU::V_PK_LSHRREV_B16:	---
3987	case AMDGPU::V_PK_LSHRREV_B16_gfx10:	---	3987	case AMDGPU::V_PK_LSHRREV_B16_gfx10:	---
3988	case AMDGPU::V_PK_LSHRREV_B16_vi:	---	3988	case AMDGPU::V_PK_LSHRREV_B16_vi:	---
3989	case AMDGPU::V_PK_ASHRREV_I16:	---	3989	case AMDGPU::V_PK_ASHRREV_I16:	---
3990	case AMDGPU::V_PK_ASHRREV_I16_gfx10:	---	3990	case AMDGPU::V_PK_ASHRREV_I16_gfx10:	---
3991	case AMDGPU::V_PK_ASHRREV_I16_vi:	---	3991	case AMDGPU::V_PK_ASHRREV_I16_vi:	---
3992	return true;	0	3992	return true;	0
3993	default:	0	3993	default:	0
3994	return false;	0	3994	return false;	0
3995	}	---	3995	}	---
3996	}	---	3996	}	---
3997		---	3997		---
3998	std::optional	---	3998	std::optional	---
3999	AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {	0	3999	AMDGPUAsmParser::validateLdsDirect(const MCInst &Inst) {	0
4000		---	4000		---
4001	using namespace SIInstrFlags;	---	4001	using namespace SIInstrFlags;	---
4002	const unsigned Opcode = Inst.getOpcode();	0	4002	const unsigned Opcode = Inst.getOpcode();	0
4003	const MCInstrDesc &Desc = MII.get(Opcode);	0	4003	const MCInstrDesc &Desc = MII.get(Opcode);	0
4004		---	4004		---
4005	// lds_direct register is defined so that it can be used	---	4005	// lds_direct register is defined so that it can be used	---
4006	// with 9-bit operands only. Ignore encodings which do not accept these.	---	4006	// with 9-bit operands only. Ignore encodings which do not accept these.	---
4007	const auto Enc = VOP1 \| VOP2 \| VOP3 \| VOPC \| VOP3P \| SIInstrFlags::SDWA;	0	4007	const auto Enc = VOP1 \| VOP2 \| VOP3 \| VOPC \| VOP3P \| SIInstrFlags::SDWA;	0
4008	if ((Desc.TSFlags & Enc) == 0)	0	4008	if ((Desc.TSFlags & Enc) == 0)	0
4009	return std::nullopt;	0	4009	return std::nullopt;	0
4010		---	4010		---
4011	for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {	0	4011	for (auto SrcName : {OpName::src0, OpName::src1, OpName::src2}) {	0
4012	auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);	0	4012	auto SrcIdx = getNamedOperandIdx(Opcode, SrcName);	0
4013	if (SrcIdx == -1)	0	4013	if (SrcIdx == -1)	0
4014	break;	0	4014	break;	0
4015	const auto &Src = Inst.getOperand(SrcIdx);	0	4015	const auto &Src = Inst.getOperand(SrcIdx);	0
4016	if (Src.isReg() && Src.getReg() == LDS_DIRECT) {	0	4016	if (Src.isReg() && Src.getReg() == LDS_DIRECT) {	0
4017		---	4017		---
4018	if (isGFX90A() \|\| isGFX11Plus())	0	4018	if (isGFX90A() \|\| isGFX11Plus())	0
4019	return StringRef("lds_direct is not supported on this GPU");	0	4019	return StringRef("lds_direct is not supported on this GPU");	0
4020		---	4020		---
4021	if (IsRevOpcode(Opcode) \|\| (Desc.TSFlags & SIInstrFlags::SDWA))	0	4021	if (IsRevOpcode(Opcode) \|\| (Desc.TSFlags & SIInstrFlags::SDWA))	0
4022	return StringRef("lds_direct cannot be used with this instruction");	0	4022	return StringRef("lds_direct cannot be used with this instruction");	0
4023		---	4023		---
4024	if (SrcName != OpName::src0)	0	4024	if (SrcName != OpName::src0)	0
4025	return StringRef("lds_direct may be used as src0 only");	0	4025	return StringRef("lds_direct may be used as src0 only");	0
4026	}	---	4026	}	---
4027	}	---	4027	}	---
4028		---	4028		---
4029	return std::nullopt;	0	4029	return std::nullopt;	0
4030	}	---	4030	}	---
4031		---	4031		---
4032	SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {	0	4032	SMLoc AMDGPUAsmParser::getFlatOffsetLoc(const OperandVector &Operands) const {	0
4033	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0	4033	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
4034	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	4034	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
4035	if (Op.isFlatOffset())	0	4035	if (Op.isFlatOffset())	0
4036	return Op.getStartLoc();	0	4036	return Op.getStartLoc();	0
4037	}	---	4037	}	---
4038	return getLoc();	0	4038	return getLoc();	0
4039	}	---	4039	}	---
4040		---	4040		---
4041	bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,	0	4041	bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,	0
4042	const OperandVector &Operands) {	---	4042	const OperandVector &Operands) {	---
4043	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0	4043	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4044	if ((TSFlags & SIInstrFlags::FLAT) == 0)	0	4044	if ((TSFlags & SIInstrFlags::FLAT) == 0)	0
4045	return true;	0	4045	return true;	0
4046		---	4046		---
4047	auto Opcode = Inst.getOpcode();	0	4047	auto Opcode = Inst.getOpcode();	0
4048	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	0	4048	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	0
4049	assert(OpNum != -1);	0	4049	assert(OpNum != -1);	0
4050		---	4050		---
4051	const auto &Op = Inst.getOperand(OpNum);	0	4051	const auto &Op = Inst.getOperand(OpNum);	0
4052	if (!hasFlatOffsets() && Op.getImm() != 0) {	0	4052	if (!hasFlatOffsets() && Op.getImm() != 0) {	0
4053	Error(getFlatOffsetLoc(Operands),	0	4053	Error(getFlatOffsetLoc(Operands),	0
4054	"flat offset modifier is not supported on this GPU");	---	4054	"flat offset modifier is not supported on this GPU");	---
4055	return false;	0	4055	return false;	0
4056	}	---	4056	}	---
4057		---	4057		---
4058	// For FLAT segment the offset must be positive;	---	4058	// For FLAT segment the offset must be positive;	---
4059	// MSB is ignored and forced to zero.	---	4059	// MSB is ignored and forced to zero.	---
4060	unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI());	0	4060	unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI());	0
4061	bool AllowNegative =	0	4061	bool AllowNegative =	0
4062	TSFlags & (SIInstrFlags::FlatGlobal \| SIInstrFlags::FlatScratch);	0	4062	TSFlags & (SIInstrFlags::FlatGlobal \| SIInstrFlags::FlatScratch);	0
4063	if (!isIntN(OffsetSize, Op.getImm()) \|\| (!AllowNegative && Op.getImm() < 0)) {	0	4063	if (!isIntN(OffsetSize, Op.getImm()) \|\| (!AllowNegative && Op.getImm() < 0)) {	0
4064	Error(getFlatOffsetLoc(Operands),	0	4064	Error(getFlatOffsetLoc(Operands),	0
4065	Twine("expected a ") +	0	4065	Twine("expected a ") +	0
4066	(AllowNegative ? Twine(OffsetSize) + "-bit signed offset"	0	4066	(AllowNegative ? Twine(OffsetSize) + "-bit signed offset"	0
4067	: Twine(OffsetSize - 1) + "-bit unsigned offset"));	0	4067	: Twine(OffsetSize - 1) + "-bit unsigned offset"));	0
4068	return false;	0	4068	return false;	0
4069	}	---	4069	}	---
4070		---	4070		---
4071	return true;	0	4071	return true;	0
4072	}	---	4072	}	---
4073		---	4073		---
4074	SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {	0	4074	SMLoc AMDGPUAsmParser::getSMEMOffsetLoc(const OperandVector &Operands) const {	0
4075	// Start with second operand because SMEM Offset cannot be dst or src0.	---	4075	// Start with second operand because SMEM Offset cannot be dst or src0.	---
4076	for (unsigned i = 2, e = Operands.size(); i != e; ++i) {	0	4076	for (unsigned i = 2, e = Operands.size(); i != e; ++i) {	0
4077	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	4077	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
4078	if (Op.isSMEMOffset() \|\| Op.isSMEMOffsetMod())	0	4078	if (Op.isSMEMOffset() \|\| Op.isSMEMOffsetMod())	0
4079	return Op.getStartLoc();	0	4079	return Op.getStartLoc();	0
4080	}	---	4080	}	---
4081	return getLoc();	0	4081	return getLoc();	0
4082	}	---	4082	}	---
4083		---	4083		---
4084	bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,	0	4084	bool AMDGPUAsmParser::validateSMEMOffset(const MCInst &Inst,	0
4085	const OperandVector &Operands) {	---	4085	const OperandVector &Operands) {	---
4086	if (isCI() \|\| isSI())	0	4086	if (isCI() \|\| isSI())	0
4087	return true;	0	4087	return true;	0
4088		---	4088		---
4089	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0	4089	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4090	if ((TSFlags & SIInstrFlags::SMRD) == 0)	0	4090	if ((TSFlags & SIInstrFlags::SMRD) == 0)	0
4091	return true;	0	4091	return true;	0
4092		---	4092		---
4093	auto Opcode = Inst.getOpcode();	0	4093	auto Opcode = Inst.getOpcode();	0
4094	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	0	4094	auto OpNum = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset);	0
4095	if (OpNum == -1)	0	4095	if (OpNum == -1)	0
4096	return true;	0	4096	return true;	0
4097		---	4097		---
4098	const auto &Op = Inst.getOperand(OpNum);	0	4098	const auto &Op = Inst.getOperand(OpNum);	0
4099	if (!Op.isImm())	0	4099	if (!Op.isImm())	0
4100	return true;	0	4100	return true;	0
4101		---	4101		---
4102	uint64_t Offset = Op.getImm();	0	4102	uint64_t Offset = Op.getImm();	0
4103	bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode);	0	4103	bool IsBuffer = AMDGPU::getSMEMIsBuffer(Opcode);	0
4104	if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) \|\|	0	4104	if (AMDGPU::isLegalSMRDEncodedUnsignedOffset(getSTI(), Offset) \|\|	0
4105	AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer))	0	4105	AMDGPU::isLegalSMRDEncodedSignedOffset(getSTI(), Offset, IsBuffer))	0
4106	return true;	0	4106	return true;	0
4107		---	4107		---
4108	Error(getSMEMOffsetLoc(Operands),	0	4108	Error(getSMEMOffsetLoc(Operands),	0
4109	(isVI() \|\| IsBuffer) ? "expected a 20-bit unsigned offset" :	0	4109	(isVI() \|\| IsBuffer) ? "expected a 20-bit unsigned offset" :	0
4110	"expected a 21-bit signed offset");	---	4110	"expected a 21-bit signed offset");	---
4111		---	4111		---
4112	return false;	0	4112	return false;	0
4113	}	---	4113	}	---
4114		---	4114		---
4115	bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {	0	4115	bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst) const {	0
4116	unsigned Opcode = Inst.getOpcode();	0	4116	unsigned Opcode = Inst.getOpcode();	0
4117	const MCInstrDesc &Desc = MII.get(Opcode);	0	4117	const MCInstrDesc &Desc = MII.get(Opcode);	0
4118	if (!(Desc.TSFlags & (SIInstrFlags::SOP2 \| SIInstrFlags::SOPC)))	0	4118	if (!(Desc.TSFlags & (SIInstrFlags::SOP2 \| SIInstrFlags::SOPC)))	0
4119	return true;	0	4119	return true;	0
4120		---	4120		---
4121	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);	0	4121	const int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);	0
4122	const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);	0	4122	const int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);	0
4123		---	4123		---
4124	const int OpIndices[] = { Src0Idx, Src1Idx };	0	4124	const int OpIndices[] = { Src0Idx, Src1Idx };	0
4125		---	4125		---
4126	unsigned NumExprs = 0;	0	4126	unsigned NumExprs = 0;	0
4127	unsigned NumLiterals = 0;	0	4127	unsigned NumLiterals = 0;	0
4128	uint32_t LiteralValue;	---	4128	uint32_t LiteralValue;	---
4129		---	4129		---
4130	for (int OpIdx : OpIndices) {	0	4130	for (int OpIdx : OpIndices) {	0
4131	if (OpIdx == -1) break;	0	4131	if (OpIdx == -1) break;	0
4132		---	4132		---
4133	const MCOperand &MO = Inst.getOperand(OpIdx);	0	4133	const MCOperand &MO = Inst.getOperand(OpIdx);	0
4134	// Exclude special imm operands (like that used by s_set_gpr_idx_on)	---	4134	// Exclude special imm operands (like that used by s_set_gpr_idx_on)	---
4135	if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {	0	4135	if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {	0
4136	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	0	4136	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	0
4137	uint32_t Value = static_cast(MO.getImm());	0	4137	uint32_t Value = static_cast(MO.getImm());	0
4138	if (NumLiterals == 0 \|\| LiteralValue != Value) {	0	4138	if (NumLiterals == 0 \|\| LiteralValue != Value) {	0
4139	LiteralValue = Value;	0	4139	LiteralValue = Value;	0
4140	++NumLiterals;	0	4140	++NumLiterals;	0
4141	}	---	4141	}	---
4142	} else if (MO.isExpr()) {	0	4142	} else if (MO.isExpr()) {	0
4143	++NumExprs;	0	4143	++NumExprs;	0
4144	}	---	4144	}	---
4145	}	---	4145	}	---
4146	}	---	4146	}	---
4147		---	4147		---
4148	return NumLiterals + NumExprs <= 1;	0	4148	return NumLiterals + NumExprs <= 1;	0
4149	}	---	4149	}	---
4150		---	4150		---
4151	bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {	0	4151	bool AMDGPUAsmParser::validateOpSel(const MCInst &Inst) {	0
4152	const unsigned Opc = Inst.getOpcode();	0	4152	const unsigned Opc = Inst.getOpcode();	0
4153	if (isPermlane16(Opc)) {	0	4153	if (isPermlane16(Opc)) {	0
4154	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0	4154	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
4155	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0	4155	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
4156		---	4156		---
4157	if (OpSel & ~3)	0	4157	if (OpSel & ~3)	0
4158	return false;	0	4158	return false;	0
4159	}	---	4159	}	---
4160		---	4160		---
4161	uint64_t TSFlags = MII.get(Opc).TSFlags;	0	4161	uint64_t TSFlags = MII.get(Opc).TSFlags;	0
4162		---	4162		---
4163	if (isGFX940() && (TSFlags & SIInstrFlags::IsDOT)) {	0	4163	if (isGFX940() && (TSFlags & SIInstrFlags::IsDOT)) {	0
4164	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0	4164	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
4165	if (OpSelIdx != -1) {	0	4165	if (OpSelIdx != -1) {	0
4166	if (Inst.getOperand(OpSelIdx).getImm() != 0)	0	4166	if (Inst.getOperand(OpSelIdx).getImm() != 0)	0
4167	return false;	0	4167	return false;	0
4168	}	---	4168	}	---
4169	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	0	4169	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	0
4170	if (OpSelHiIdx != -1) {	0	4170	if (OpSelHiIdx != -1) {	0
4171	if (Inst.getOperand(OpSelHiIdx).getImm() != -1)	0	4171	if (Inst.getOperand(OpSelHiIdx).getImm() != -1)	0
4172	return false;	0	4172	return false;	0
4173	}	---	4173	}	---
4174	}	---	4174	}	---
4175		---	4175		---
4176	// op_sel[0:1] must be 0 for v_dot2_bf16_bf16 and v_dot2_f16_f16 (VOP3 Dot).	---	4176	// op_sel[0:1] must be 0 for v_dot2_bf16_bf16 and v_dot2_f16_f16 (VOP3 Dot).	---
4177	if (isGFX11Plus() && (TSFlags & SIInstrFlags::IsDOT) &&	0	4177	if (isGFX11Plus() && (TSFlags & SIInstrFlags::IsDOT) &&	0
4178	(TSFlags & SIInstrFlags::VOP3) && !(TSFlags & SIInstrFlags::VOP3P)) {	0	4178	(TSFlags & SIInstrFlags::VOP3) && !(TSFlags & SIInstrFlags::VOP3P)) {	0
4179	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0	4179	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
4180	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0	4180	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
4181	if (OpSel & 3)	0	4181	if (OpSel & 3)	0
4182	return false;	0	4182	return false;	0
4183	}	---	4183	}	---
4184		---	4184		---
4185	return true;	0	4185	return true;	0
4186	}	---	4186	}	---
4187		---	4187		---
4188	bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,	0	4188	bool AMDGPUAsmParser::validateDPP(const MCInst &Inst,	0
4189	const OperandVector &Operands) {	---	4189	const OperandVector &Operands) {	---
4190	const unsigned Opc = Inst.getOpcode();	0	4190	const unsigned Opc = Inst.getOpcode();	0
4191	int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl);	0	4191	int DppCtrlIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::dpp_ctrl);	0
4192	if (DppCtrlIdx < 0)	0	4192	if (DppCtrlIdx < 0)	0
4193	return true;	0	4193	return true;	0
4194	unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();	0	4194	unsigned DppCtrl = Inst.getOperand(DppCtrlIdx).getImm();	0
4195		---	4195		---
4196	if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {	0	4196	if (!AMDGPU::isLegal64BitDPPControl(DppCtrl)) {	0
4197	// DPP64 is supported for row_newbcast only.	---	4197	// DPP64 is supported for row_newbcast only.	---
4198	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0	4198	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);	0
4199	if (Src0Idx >= 0 &&	0	4199	if (Src0Idx >= 0 &&	0
4200	getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) {	0	4200	getMRI()->getSubReg(Inst.getOperand(Src0Idx).getReg(), AMDGPU::sub1)) {	0
4201	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);	0	4201	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyDppCtrl, Operands);	0
4202	Error(S, "64 bit dpp only supports row_newbcast");	0	4202	Error(S, "64 bit dpp only supports row_newbcast");	0
4203	return false;	0	4203	return false;	0
4204	}	---	4204	}	---
4205	}	---	4205	}	---
4206		---	4206		---
4207	return true;	0	4207	return true;	0
4208	}	---	4208	}	---
4209		---	4209		---
4210	// Check if VCC register matches wavefront size	---	4210	// Check if VCC register matches wavefront size	---
4211	bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {	0	4211	bool AMDGPUAsmParser::validateVccOperand(unsigned Reg) const {	0
4212	auto FB = getFeatureBits();	0	4212	auto FB = getFeatureBits();	0
4213	return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) \|\|	0	4213	return (FB[AMDGPU::FeatureWavefrontSize64] && Reg == AMDGPU::VCC) \|\|	0
4214	(FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);	0	4214	(FB[AMDGPU::FeatureWavefrontSize32] && Reg == AMDGPU::VCC_LO);	0
4215	}	---	4215	}	---
4216		---	4216		---
4217	// One unique literal can be used. VOP3 literal is only allowed in GFX10+	---	4217	// One unique literal can be used. VOP3 literal is only allowed in GFX10+	---
4218	bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,	0	4218	bool AMDGPUAsmParser::validateVOPLiteral(const MCInst &Inst,	0
4219	const OperandVector &Operands) {	---	4219	const OperandVector &Operands) {	---
4220	unsigned Opcode = Inst.getOpcode();	0	4220	unsigned Opcode = Inst.getOpcode();	0
4221	const MCInstrDesc &Desc = MII.get(Opcode);	0	4221	const MCInstrDesc &Desc = MII.get(Opcode);	0
4222	bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1;	0	4222	bool HasMandatoryLiteral = getNamedOperandIdx(Opcode, OpName::imm) != -1;	0
4223	if (!(Desc.TSFlags & (SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P)) &&	0	4223	if (!(Desc.TSFlags & (SIInstrFlags::VOP3 \| SIInstrFlags::VOP3P)) &&	0
4224	!HasMandatoryLiteral && !isVOPD(Opcode))	0	4224	!HasMandatoryLiteral && !isVOPD(Opcode))	0
4225	return true;	0	4225	return true;	0
4226		---	4226		---
4227	OperandIndices OpIndices = getSrcOperandIndices(Opcode, HasMandatoryLiteral);	0	4227	OperandIndices OpIndices = getSrcOperandIndices(Opcode, HasMandatoryLiteral);	0
4228		---	4228		---
4229	unsigned NumExprs = 0;	0	4229	unsigned NumExprs = 0;	0
4230	unsigned NumLiterals = 0;	0	4230	unsigned NumLiterals = 0;	0
4231	uint32_t LiteralValue;	---	4231	uint32_t LiteralValue;	---
4232		---	4232		---
4233	for (int OpIdx : OpIndices) {	0	4233	for (int OpIdx : OpIndices) {	0
4234	if (OpIdx == -1)	0	4234	if (OpIdx == -1)	0
4235	continue;	0	4235	continue;	0
4236		---	4236		---
4237	const MCOperand &MO = Inst.getOperand(OpIdx);	0	4237	const MCOperand &MO = Inst.getOperand(OpIdx);	0
4238	if (!MO.isImm() && !MO.isExpr())	0	4238	if (!MO.isImm() && !MO.isExpr())	0
4239	continue;	0	4239	continue;	0
4240	if (!isSISrcOperand(Desc, OpIdx))	0	4240	if (!isSISrcOperand(Desc, OpIdx))	0
4241	continue;	0	4241	continue;	0
4242		---	4242		---
4243	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	0	4243	if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {	0
4244	uint32_t Value = static_cast(MO.getImm());	0	4244	uint32_t Value = static_cast(MO.getImm());	0
4245	if (NumLiterals == 0 \|\| LiteralValue != Value) {	0	4245	if (NumLiterals == 0 \|\| LiteralValue != Value) {	0
4246	LiteralValue = Value;	0	4246	LiteralValue = Value;	0
4247	++NumLiterals;	0	4247	++NumLiterals;	0
4248	}	---	4248	}	---
4249	} else if (MO.isExpr()) {	0	4249	} else if (MO.isExpr()) {	0
4250	++NumExprs;	0	4250	++NumExprs;	0
4251	}	---	4251	}	---
4252	}	---	4252	}	---
4253	NumLiterals += NumExprs;	0	4253	NumLiterals += NumExprs;	0
4254		---	4254		---
4255	if (!NumLiterals)	0	4255	if (!NumLiterals)	0
4256	return true;	0	4256	return true;	0
4257		---	4257		---
4258	if (!HasMandatoryLiteral && !getFeatureBits()[FeatureVOP3Literal]) {	0	4258	if (!HasMandatoryLiteral && !getFeatureBits()[FeatureVOP3Literal]) {	0
4259	Error(getLitLoc(Operands), "literal operands are not supported");	0	4259	Error(getLitLoc(Operands), "literal operands are not supported");	0
4260	return false;	0	4260	return false;	0
4261	}	---	4261	}	---
4262		---	4262		---
4263	if (NumLiterals > 1) {	0	4263	if (NumLiterals > 1) {	0
4264	Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");	0	4264	Error(getLitLoc(Operands, true), "only one unique literal operand is allowed");	0
4265	return false;	0	4265	return false;	0
4266	}	---	4266	}	---
4267		---	4267		---
4268	return true;	0	4268	return true;	0
4269	}	0	4269	}	0
4270		---	4270		---
4271	// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.	---	4271	// Returns -1 if not a register, 0 if VGPR and 1 if AGPR.	---
4272	static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,	0	4272	static int IsAGPROperand(const MCInst &Inst, uint16_t NameIdx,	0
4273	const MCRegisterInfo *MRI) {	---	4273	const MCRegisterInfo *MRI) {	---
4274	int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);	0	4274	int OpIdx = AMDGPU::getNamedOperandIdx(Inst.getOpcode(), NameIdx);	0
4275	if (OpIdx < 0)	0	4275	if (OpIdx < 0)	0
4276	return -1;	0	4276	return -1;	0
4277		---	4277		---
4278	const MCOperand &Op = Inst.getOperand(OpIdx);	0	4278	const MCOperand &Op = Inst.getOperand(OpIdx);	0
4279	if (!Op.isReg())	0	4279	if (!Op.isReg())	0
4280	return -1;	0	4280	return -1;	0
4281		---	4281		---
4282	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	0	4282	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	0
4283	auto Reg = Sub ? Sub : Op.getReg();	0	4283	auto Reg = Sub ? Sub : Op.getReg();	0
4284	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	0	4284	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	0
4285	return AGPR32.contains(Reg) ? 1 : 0;	0	4285	return AGPR32.contains(Reg) ? 1 : 0;	0
4286	}	---	4286	}	---
4287		---	4287		---
4288	bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {	0	4288	bool AMDGPUAsmParser::validateAGPRLdSt(const MCInst &Inst) const {	0
4289	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0	4289	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4290	if ((TSFlags & (SIInstrFlags::FLAT \| SIInstrFlags::MUBUF \|	0	4290	if ((TSFlags & (SIInstrFlags::FLAT \| SIInstrFlags::MUBUF \|	0
4291	SIInstrFlags::MTBUF \| SIInstrFlags::MIMG \|	---	4291	SIInstrFlags::MTBUF \| SIInstrFlags::MIMG \|	---
4292	SIInstrFlags::DS)) == 0)	---	4292	SIInstrFlags::DS)) == 0)	---
4293	return true;	0	4293	return true;	0
4294		---	4294		---
4295	uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0	0	4295	uint16_t DataNameIdx = (TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0	0
4296	: AMDGPU::OpName::vdata;	---	4296	: AMDGPU::OpName::vdata;	---
4297		---	4297		---
4298	const MCRegisterInfo *MRI = getMRI();	0	4298	const MCRegisterInfo *MRI = getMRI();	0
4299	int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);	0	4299	int DstAreg = IsAGPROperand(Inst, AMDGPU::OpName::vdst, MRI);	0
4300	int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);	0	4300	int DataAreg = IsAGPROperand(Inst, DataNameIdx, MRI);	0
4301		---	4301		---
4302	if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {	0	4302	if ((TSFlags & SIInstrFlags::DS) && DataAreg >= 0) {	0
4303	int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);	0	4303	int Data2Areg = IsAGPROperand(Inst, AMDGPU::OpName::data1, MRI);	0
4304	if (Data2Areg >= 0 && Data2Areg != DataAreg)	0	4304	if (Data2Areg >= 0 && Data2Areg != DataAreg)	0
4305	return false;	0	4305	return false;	0
4306	}	---	4306	}	---
4307		---	4307		---
4308	auto FB = getFeatureBits();	0	4308	auto FB = getFeatureBits();	0
4309	if (FB[AMDGPU::FeatureGFX90AInsts]) {	0	4309	if (FB[AMDGPU::FeatureGFX90AInsts]) {	0
4310	if (DataAreg < 0 \|\| DstAreg < 0)	0	4310	if (DataAreg < 0 \|\| DstAreg < 0)	0
4311	return true;	0	4311	return true;	0
4312	return DstAreg == DataAreg;	0	4312	return DstAreg == DataAreg;	0
4313	}	---	4313	}	---
4314		---	4314		---
4315	return DstAreg < 1 && DataAreg < 1;	0	4315	return DstAreg < 1 && DataAreg < 1;	0
4316	}	---	4316	}	---
4317		---	4317		---
4318	bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {	0	4318	bool AMDGPUAsmParser::validateVGPRAlign(const MCInst &Inst) const {	0
4319	auto FB = getFeatureBits();	0	4319	auto FB = getFeatureBits();	0
4320	if (!FB[AMDGPU::FeatureGFX90AInsts])	0	4320	if (!FB[AMDGPU::FeatureGFX90AInsts])	0
4321	return true;	0	4321	return true;	0
4322		---	4322		---
4323	const MCRegisterInfo *MRI = getMRI();	0	4323	const MCRegisterInfo *MRI = getMRI();	0
4324	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	0	4324	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	0
4325	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	0	4325	const MCRegisterClass &AGPR32 = MRI->getRegClass(AMDGPU::AGPR_32RegClassID);	0
4326	for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {	0	4326	for (unsigned I = 0, E = Inst.getNumOperands(); I != E; ++I) {	0
4327	const MCOperand &Op = Inst.getOperand(I);	0	4327	const MCOperand &Op = Inst.getOperand(I);	0
4328	if (!Op.isReg())	0	4328	if (!Op.isReg())	0
4329	continue;	0	4329	continue;	0
4330		---	4330		---
4331	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	0	4331	unsigned Sub = MRI->getSubReg(Op.getReg(), AMDGPU::sub0);	0
4332	if (!Sub)	0	4332	if (!Sub)	0
4333	continue;	0	4333	continue;	0
4334		---	4334		---
4335	if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))	0	4335	if (VGPR32.contains(Sub) && ((Sub - AMDGPU::VGPR0) & 1))	0
4336	return false;	0	4336	return false;	0
4337	if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))	0	4337	if (AGPR32.contains(Sub) && ((Sub - AMDGPU::AGPR0) & 1))	0
4338	return false;	0	4338	return false;	0
4339	}	---	4339	}	---
4340		---	4340		---
4341	return true;	0	4341	return true;	0
4342	}	---	4342	}	---
4343		---	4343		---
4344	SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {	0	4344	SMLoc AMDGPUAsmParser::getBLGPLoc(const OperandVector &Operands) const {	0
4345	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0	4345	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
4346	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	4346	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
4347	if (Op.isBLGP())	0	4347	if (Op.isBLGP())	0
4348	return Op.getStartLoc();	0	4348	return Op.getStartLoc();	0
4349	}	---	4349	}	---
4350	return SMLoc();	0	4350	return SMLoc();	0
4351	}	---	4351	}	---
4352		---	4352		---
4353	bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,	0	4353	bool AMDGPUAsmParser::validateBLGP(const MCInst &Inst,	0
4354	const OperandVector &Operands) {	---	4354	const OperandVector &Operands) {	---
4355	unsigned Opc = Inst.getOpcode();	0	4355	unsigned Opc = Inst.getOpcode();	0
4356	int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp);	0	4356	int BlgpIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::blgp);	0
4357	if (BlgpIdx == -1)	0	4357	if (BlgpIdx == -1)	0
4358	return true;	0	4358	return true;	0
4359	SMLoc BLGPLoc = getBLGPLoc(Operands);	0	4359	SMLoc BLGPLoc = getBLGPLoc(Operands);	0
4360	if (!BLGPLoc.isValid())	0	4360	if (!BLGPLoc.isValid())	0
4361	return true;	0	4361	return true;	0
4362	bool IsNeg = StringRef(BLGPLoc.getPointer()).startswith("neg:");	0	4362	bool IsNeg = StringRef(BLGPLoc.getPointer()).startswith("neg:");	0
4363	auto FB = getFeatureBits();	0	4363	auto FB = getFeatureBits();	0
4364	bool UsesNeg = false;	0	4364	bool UsesNeg = false;	0
4365	if (FB[AMDGPU::FeatureGFX940Insts]) {	0	4365	if (FB[AMDGPU::FeatureGFX940Insts]) {	0
4366	switch (Opc) {	0	4366	switch (Opc) {	0
4367	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:	0	4367	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_acd:	0
4368	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:	---	4368	case AMDGPU::V_MFMA_F64_16X16X4F64_gfx940_vcd:	---
4369	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:	---	4369	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_acd:	---
4370	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:	---	4370	case AMDGPU::V_MFMA_F64_4X4X4F64_gfx940_vcd:	---
4371	UsesNeg = true;	0	4371	UsesNeg = true;	0
4372	}	---	4372	}	---
4373	}	---	4373	}	---
4374		---	4374		---
4375	if (IsNeg == UsesNeg)	0	4375	if (IsNeg == UsesNeg)	0
4376	return true;	0	4376	return true;	0
4377		---	4377		---
4378	Error(BLGPLoc,	0	4378	Error(BLGPLoc,	0
4379	UsesNeg ? "invalid modifier: blgp is not supported"	---	4379	UsesNeg ? "invalid modifier: blgp is not supported"	---
4380	: "invalid modifier: neg is not supported");	---	4380	: "invalid modifier: neg is not supported");	---
4381		---	4381		---
4382	return false;	0	4382	return false;	0
4383	}	---	4383	}	---
4384		---	4384		---
4385	bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,	0	4385	bool AMDGPUAsmParser::validateWaitCnt(const MCInst &Inst,	0
4386	const OperandVector &Operands) {	---	4386	const OperandVector &Operands) {	---
4387	if (!isGFX11Plus())	0	4387	if (!isGFX11Plus())	0
4388	return true;	0	4388	return true;	0
4389		---	4389		---
4390	unsigned Opc = Inst.getOpcode();	0	4390	unsigned Opc = Inst.getOpcode();	0
4391	if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 &&	0	4391	if (Opc != AMDGPU::S_WAITCNT_EXPCNT_gfx11 &&	0
4392	Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 &&	0	4392	Opc != AMDGPU::S_WAITCNT_LGKMCNT_gfx11 &&	0
4393	Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 &&	0	4393	Opc != AMDGPU::S_WAITCNT_VMCNT_gfx11 &&	0
4394	Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11)	---	4394	Opc != AMDGPU::S_WAITCNT_VSCNT_gfx11)	---
4395	return true;	0	4395	return true;	0
4396		---	4396		---
4397	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);	0	4397	int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::sdst);	0
4398	assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());	0	4398	assert(Src0Idx >= 0 && Inst.getOperand(Src0Idx).isReg());	0
4399	auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());	0	4399	auto Reg = mc2PseudoReg(Inst.getOperand(Src0Idx).getReg());	0
4400	if (Reg == AMDGPU::SGPR_NULL)	0	4400	if (Reg == AMDGPU::SGPR_NULL)	0
4401	return true;	0	4401	return true;	0
4402		---	4402		---
4403	SMLoc RegLoc = getRegLoc(Reg, Operands);	0	4403	SMLoc RegLoc = getRegLoc(Reg, Operands);	0
4404	Error(RegLoc, "src0 must be null");	0	4404	Error(RegLoc, "src0 must be null");	0
4405	return false;	0	4405	return false;	0
4406	}	---	4406	}	---
4407		---	4407		---
4408	// gfx90a has an undocumented limitation:	---	4408	// gfx90a has an undocumented limitation:	---
4409	// DS_GWS opcodes must use even aligned registers.	---	4409	// DS_GWS opcodes must use even aligned registers.	---
4410	bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,	0	4410	bool AMDGPUAsmParser::validateGWS(const MCInst &Inst,	0
4411	const OperandVector &Operands) {	---	4411	const OperandVector &Operands) {	---
4412	if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])	0	4412	if (!getFeatureBits()[AMDGPU::FeatureGFX90AInsts])	0
4413	return true;	0	4413	return true;	0
4414		---	4414		---
4415	int Opc = Inst.getOpcode();	0	4415	int Opc = Inst.getOpcode();	0
4416	if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&	0	4416	if (Opc != AMDGPU::DS_GWS_INIT_vi && Opc != AMDGPU::DS_GWS_BARRIER_vi &&	0
4417	Opc != AMDGPU::DS_GWS_SEMA_BR_vi)	---	4417	Opc != AMDGPU::DS_GWS_SEMA_BR_vi)	---
4418	return true;	0	4418	return true;	0
4419		---	4419		---
4420	const MCRegisterInfo *MRI = getMRI();	0	4420	const MCRegisterInfo *MRI = getMRI();	0
4421	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	0	4421	const MCRegisterClass &VGPR32 = MRI->getRegClass(AMDGPU::VGPR_32RegClassID);	0
4422	int Data0Pos =	---	4422	int Data0Pos =	---
4423	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);	0	4423	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0);	0
4424	assert(Data0Pos != -1);	0	4424	assert(Data0Pos != -1);	0
4425	auto Reg = Inst.getOperand(Data0Pos).getReg();	0	4425	auto Reg = Inst.getOperand(Data0Pos).getReg();	0
4426	auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);	0	4426	auto RegIdx = Reg - (VGPR32.contains(Reg) ? AMDGPU::VGPR0 : AMDGPU::AGPR0);	0
4427	if (RegIdx & 1) {	0	4427	if (RegIdx & 1) {	0
4428	SMLoc RegLoc = getRegLoc(Reg, Operands);	0	4428	SMLoc RegLoc = getRegLoc(Reg, Operands);	0
4429	Error(RegLoc, "vgpr must be even aligned");	0	4429	Error(RegLoc, "vgpr must be even aligned");	0
4430	return false;	0	4430	return false;	0
4431	}	---	4431	}	---
4432		---	4432		---
4433	return true;	0	4433	return true;	0
4434	}	---	4434	}	---
4435		---	4435		---
4436	bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,	0	4436	bool AMDGPUAsmParser::validateCoherencyBits(const MCInst &Inst,	0
4437	const OperandVector &Operands,	---	4437	const OperandVector &Operands,	---
4438	const SMLoc &IDLoc) {	---	4438	const SMLoc &IDLoc) {	---
4439	int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),	0	4439	int CPolPos = AMDGPU::getNamedOperandIdx(Inst.getOpcode(),	0
4440	AMDGPU::OpName::cpol);	0	4440	AMDGPU::OpName::cpol);	0
4441	if (CPolPos == -1)	0	4441	if (CPolPos == -1)	0
4442	return true;	0	4442	return true;	0
4443		---	4443		---
4444	unsigned CPol = Inst.getOperand(CPolPos).getImm();	0	4444	unsigned CPol = Inst.getOperand(CPolPos).getImm();	0
4445		---	4445		---
4446	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0	4446	uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;	0
4447	if (TSFlags & SIInstrFlags::SMRD) {	0	4447	if (TSFlags & SIInstrFlags::SMRD) {	0
4448	if (CPol && (isSI() \|\| isCI())) {	0	4448	if (CPol && (isSI() \|\| isCI())) {	0
4449	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0	4449	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0
4450	Error(S, "cache policy is not supported for SMRD instructions");	0	4450	Error(S, "cache policy is not supported for SMRD instructions");	0
4451	return false;	0	4451	return false;	0
4452	}	---	4452	}	---
4453	if (CPol & ~(AMDGPU::CPol::GLC \| AMDGPU::CPol::DLC)) {	0	4453	if (CPol & ~(AMDGPU::CPol::GLC \| AMDGPU::CPol::DLC)) {	0
4454	Error(IDLoc, "invalid cache policy for SMEM instruction");	0	4454	Error(IDLoc, "invalid cache policy for SMEM instruction");	0
4455	return false;	0	4455	return false;	0
4456	}	---	4456	}	---
4457	}	---	4457	}	---
4458		---	4458		---
4459	if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {	0	4459	if (isGFX90A() && !isGFX940() && (CPol & CPol::SCC)) {	0
4460	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0	4460	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0
4461	StringRef CStr(S.getPointer());	0	4461	StringRef CStr(S.getPointer());	0
4462	S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);	0	4462	S = SMLoc::getFromPointer(&CStr.data()[CStr.find("scc")]);	0
4463	Error(S, "scc is not supported on this GPU");	0	4463	Error(S, "scc is not supported on this GPU");	0
4464	return false;	0	4464	return false;	0
4465	}	---	4465	}	---
4466		---	4466		---
4467	if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet \| SIInstrFlags::IsAtomicRet)))	0	4467	if (!(TSFlags & (SIInstrFlags::IsAtomicNoRet \| SIInstrFlags::IsAtomicRet)))	0
4468	return true;	0	4468	return true;	0
4469		---	4469		---
4470	if (TSFlags & SIInstrFlags::IsAtomicRet) {	0	4470	if (TSFlags & SIInstrFlags::IsAtomicRet) {	0
4471	if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {	0	4471	if (!(TSFlags & SIInstrFlags::MIMG) && !(CPol & CPol::GLC)) {	0
4472	Error(IDLoc, isGFX940() ? "instruction must use sc0"	0	4472	Error(IDLoc, isGFX940() ? "instruction must use sc0"	0
4473	: "instruction must use glc");	---	4473	: "instruction must use glc");	---
4474	return false;	0	4474	return false;	0
4475	}	---	4475	}	---
4476	} else {	---	4476	} else {	---
4477	if (CPol & CPol::GLC) {	0	4477	if (CPol & CPol::GLC) {	0
4478	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0	4478	SMLoc S = getImmLoc(AMDGPUOperand::ImmTyCPol, Operands);	0
4479	StringRef CStr(S.getPointer());	0	4479	StringRef CStr(S.getPointer());	0
4480	S = SMLoc::getFromPointer(	0	4480	S = SMLoc::getFromPointer(	0
4481	&CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]);	0	4481	&CStr.data()[CStr.find(isGFX940() ? "sc0" : "glc")]);	0
4482	Error(S, isGFX940() ? "instruction must not use sc0"	0	4482	Error(S, isGFX940() ? "instruction must not use sc0"	0
4483	: "instruction must not use glc");	---	4483	: "instruction must not use glc");	---
4484	return false;	0	4484	return false;	0
4485	}	---	4485	}	---
4486	}	---	4486	}	---
4487		---	4487		---
4488	return true;	0	4488	return true;	0
4489	}	---	4489	}	---
4490		---	4490		---
4491	bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {	0	4491	bool AMDGPUAsmParser::validateExeczVcczOperands(const OperandVector &Operands) {	0
4492	if (!isGFX11Plus())	0	4492	if (!isGFX11Plus())	0
4493	return true;	0	4493	return true;	0
4494	for (auto &Operand : Operands) {	0	4494	for (auto &Operand : Operands) {	0
4495	if (!Operand->isReg())	0	4495	if (!Operand->isReg())	0
4496	continue;	0	4496	continue;	0
4497	unsigned Reg = Operand->getReg();	0	4497	unsigned Reg = Operand->getReg();	0
4498	if (Reg == SRC_EXECZ \|\| Reg == SRC_VCCZ) {	0	4498	if (Reg == SRC_EXECZ \|\| Reg == SRC_VCCZ) {	0
4499	Error(getRegLoc(Reg, Operands),	0	4499	Error(getRegLoc(Reg, Operands),	0
4500	"execz and vccz are not supported on this GPU");	---	4500	"execz and vccz are not supported on this GPU");	---
4501	return false;	0	4501	return false;	0
4502	}	---	4502	}	---
4503	}	---	4503	}	---
4504	return true;	0	4504	return true;	0
4505	}	---	4505	}	---
4506		---	4506		---
4507	bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,	0	4507	bool AMDGPUAsmParser::validateTFE(const MCInst &Inst,	0
4508	const OperandVector &Operands) {	---	4508	const OperandVector &Operands) {	---
4509	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	4509	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
4510	if (Desc.mayStore() &&	0	4510	if (Desc.mayStore() &&	0
4511	(Desc.TSFlags & (SIInstrFlags::MUBUF \| SIInstrFlags::MTBUF))) {	0	4511	(Desc.TSFlags & (SIInstrFlags::MUBUF \| SIInstrFlags::MTBUF))) {	0
4512	SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);	0	4512	SMLoc Loc = getImmLoc(AMDGPUOperand::ImmTyTFE, Operands);	0
4513	if (Loc != getInstLoc(Operands)) {	0	4513	if (Loc != getInstLoc(Operands)) {	0
4514	Error(Loc, "TFE modifier has no meaning for store instructions");	0	4514	Error(Loc, "TFE modifier has no meaning for store instructions");	0
4515	return false;	0	4515	return false;	0
4516	}	---	4516	}	---
4517	}	---	4517	}	---
4518		---	4518		---
4519	return true;	0	4519	return true;	0
4520	}	---	4520	}	---
4521		---	4521		---
4522	bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,	0	4522	bool AMDGPUAsmParser::validateInstruction(const MCInst &Inst,	0
4523	const SMLoc &IDLoc,	---	4523	const SMLoc &IDLoc,	---
4524	const OperandVector &Operands) {	---	4524	const OperandVector &Operands) {	---
4525	if (auto ErrMsg = validateLdsDirect(Inst)) {	0	4525	if (auto ErrMsg = validateLdsDirect(Inst)) {	0
4526	Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);	0	4526	Error(getRegLoc(LDS_DIRECT, Operands), *ErrMsg);	0
4527	return false;	0	4527	return false;	0
4528	}	---	4528	}	---
4529	if (!validateSOPLiteral(Inst)) {	0	4529	if (!validateSOPLiteral(Inst)) {	0
4530	Error(getLitLoc(Operands),	0	4530	Error(getLitLoc(Operands),	0
4531	"only one unique literal operand is allowed");	---	4531	"only one unique literal operand is allowed");	---
4532	return false;	0	4532	return false;	0
4533	}	---	4533	}	---
4534	if (!validateVOPLiteral(Inst, Operands)) {	0	4534	if (!validateVOPLiteral(Inst, Operands)) {	0
4535	return false;	0	4535	return false;	0
4536	}	---	4536	}	---
4537	if (!validateConstantBusLimitations(Inst, Operands)) {	0	4537	if (!validateConstantBusLimitations(Inst, Operands)) {	0
4538	return false;	0	4538	return false;	0
4539	}	---	4539	}	---
4540	if (!validateVOPDRegBankConstraints(Inst, Operands)) {	0	4540	if (!validateVOPDRegBankConstraints(Inst, Operands)) {	0
4541	return false;	0	4541	return false;	0
4542	}	---	4542	}	---
4543	if (!validateIntClampSupported(Inst)) {	0	4543	if (!validateIntClampSupported(Inst)) {	0
4544	Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),	0	4544	Error(getImmLoc(AMDGPUOperand::ImmTyClampSI, Operands),	0
4545	"integer clamping is not supported on this GPU");	---	4545	"integer clamping is not supported on this GPU");	---
4546	return false;	0	4546	return false;	0
4547	}	---	4547	}	---
4548	if (!validateOpSel(Inst)) {	0	4548	if (!validateOpSel(Inst)) {	0
4549	Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),	0	4549	Error(getImmLoc(AMDGPUOperand::ImmTyOpSel, Operands),	0
4550	"invalid op_sel operand");	---	4550	"invalid op_sel operand");	---
4551	return false;	0	4551	return false;	0
4552	}	---	4552	}	---
4553	if (!validateDPP(Inst, Operands)) {	0	4553	if (!validateDPP(Inst, Operands)) {	0
4554	return false;	0	4554	return false;	0
4555	}	---	4555	}	---
4556	// For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.	---	4556	// For MUBUF/MTBUF d16 is a part of opcode, so there is nothing to validate.	---
4557	if (!validateMIMGD16(Inst)) {	0	4557	if (!validateMIMGD16(Inst)) {	0
4558	Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),	0	4558	Error(getImmLoc(AMDGPUOperand::ImmTyD16, Operands),	0
4559	"d16 modifier is not supported on this GPU");	---	4559	"d16 modifier is not supported on this GPU");	---
4560	return false;	0	4560	return false;	0
4561	}	---	4561	}	---
4562	if (!validateMIMGMSAA(Inst)) {	0	4562	if (!validateMIMGMSAA(Inst)) {	0
4563	Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),	0	4563	Error(getImmLoc(AMDGPUOperand::ImmTyDim, Operands),	0
4564	"invalid dim; must be MSAA type");	---	4564	"invalid dim; must be MSAA type");	---
4565	return false;	0	4565	return false;	0
4566	}	---	4566	}	---
4567	if (!validateMIMGDataSize(Inst, IDLoc)) {	0	4567	if (!validateMIMGDataSize(Inst, IDLoc)) {	0
4568	return false;	0	4568	return false;	0
4569	}	---	4569	}	---
4570	if (!validateMIMGAddrSize(Inst, IDLoc))	0	4570	if (!validateMIMGAddrSize(Inst, IDLoc))	0
4571	return false;	0	4571	return false;	0
4572	if (!validateMIMGAtomicDMask(Inst)) {	0	4572	if (!validateMIMGAtomicDMask(Inst)) {	0
4573	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	0	4573	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	0
4574	"invalid atomic image dmask");	---	4574	"invalid atomic image dmask");	---
4575	return false;	0	4575	return false;	0
4576	}	---	4576	}	---
4577	if (!validateMIMGGatherDMask(Inst)) {	0	4577	if (!validateMIMGGatherDMask(Inst)) {	0
4578	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	0	4578	Error(getImmLoc(AMDGPUOperand::ImmTyDMask, Operands),	0
4579	"invalid image_gather dmask: only one bit must be set");	---	4579	"invalid image_gather dmask: only one bit must be set");	---
4580	return false;	0	4580	return false;	0
4581	}	---	4581	}	---
4582	if (!validateMovrels(Inst, Operands)) {	0	4582	if (!validateMovrels(Inst, Operands)) {	0
4583	return false;	0	4583	return false;	0
4584	}	---	4584	}	---
4585	if (!validateFlatOffset(Inst, Operands)) {	0	4585	if (!validateFlatOffset(Inst, Operands)) {	0
4586	return false;	0	4586	return false;	0
4587	}	---	4587	}	---
4588	if (!validateSMEMOffset(Inst, Operands)) {	0	4588	if (!validateSMEMOffset(Inst, Operands)) {	0
4589	return false;	0	4589	return false;	0
4590	}	---	4590	}	---
4591	if (!validateMAIAccWrite(Inst, Operands)) {	0	4591	if (!validateMAIAccWrite(Inst, Operands)) {	0
4592	return false;	0	4592	return false;	0
4593	}	---	4593	}	---
4594	if (!validateMAISrc2(Inst, Operands)) {	0	4594	if (!validateMAISrc2(Inst, Operands)) {	0
4595	return false;	0	4595	return false;	0
4596	}	---	4596	}	---
4597	if (!validateMFMA(Inst, Operands)) {	0	4597	if (!validateMFMA(Inst, Operands)) {	0
4598	return false;	0	4598	return false;	0
4599	}	---	4599	}	---
4600	if (!validateCoherencyBits(Inst, Operands, IDLoc)) {	0	4600	if (!validateCoherencyBits(Inst, Operands, IDLoc)) {	0
4601	return false;	0	4601	return false;	0
4602	}	---	4602	}	---
4603		---	4603		---
4604	if (!validateAGPRLdSt(Inst)) {	0	4604	if (!validateAGPRLdSt(Inst)) {	0
4605	Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]	0	4605	Error(IDLoc, getFeatureBits()[AMDGPU::FeatureGFX90AInsts]	0
4606	? "invalid register class: data and dst should be all VGPR or AGPR"	---	4606	? "invalid register class: data and dst should be all VGPR or AGPR"	---
4607	: "invalid register class: agpr loads and stores not supported on this GPU"	---	4607	: "invalid register class: agpr loads and stores not supported on this GPU"	---
4608	);	---	4608	);	---
4609	return false;	0	4609	return false;	0
4610	}	---	4610	}	---
4611	if (!validateVGPRAlign(Inst)) {	0	4611	if (!validateVGPRAlign(Inst)) {	0
4612	Error(IDLoc,	0	4612	Error(IDLoc,	0
4613	"invalid register class: vgpr tuples must be 64 bit aligned");	---	4613	"invalid register class: vgpr tuples must be 64 bit aligned");	---
4614	return false;	0	4614	return false;	0
4615	}	---	4615	}	---
4616	if (!validateGWS(Inst, Operands)) {	0	4616	if (!validateGWS(Inst, Operands)) {	0
4617	return false;	0	4617	return false;	0
4618	}	---	4618	}	---
4619		---	4619		---
4620	if (!validateBLGP(Inst, Operands)) {	0	4620	if (!validateBLGP(Inst, Operands)) {	0
4621	return false;	0	4621	return false;	0
4622	}	---	4622	}	---
4623		---	4623		---
4624	if (!validateDivScale(Inst)) {	0	4624	if (!validateDivScale(Inst)) {	0
4625	Error(IDLoc, "ABS not allowed in VOP3B instructions");	0	4625	Error(IDLoc, "ABS not allowed in VOP3B instructions");	0
4626	return false;	0	4626	return false;	0
4627	}	---	4627	}	---
4628	if (!validateWaitCnt(Inst, Operands)) {	0	4628	if (!validateWaitCnt(Inst, Operands)) {	0
4629	return false;	0	4629	return false;	0
4630	}	---	4630	}	---
4631	if (!validateExeczVcczOperands(Operands)) {	0	4631	if (!validateExeczVcczOperands(Operands)) {	0
4632	return false;	0	4632	return false;	0
4633	}	---	4633	}	---
4634	if (!validateTFE(Inst, Operands)) {	0	4634	if (!validateTFE(Inst, Operands)) {	0
4635	return false;	0	4635	return false;	0
4636	}	---	4636	}	---
4637		---	4637		---
4638	return true;	0	4638	return true;	0
4639	}	---	4639	}	---
4640		---	4640		---
4641	static std::string AMDGPUMnemonicSpellCheck(StringRef S,	---	4641	static std::string AMDGPUMnemonicSpellCheck(StringRef S,	---
4642	const FeatureBitset &FBS,	---	4642	const FeatureBitset &FBS,	---
4643	unsigned VariantID = 0);	---	4643	unsigned VariantID = 0);	---
4644		---	4644		---
4645	static bool AMDGPUCheckMnemonic(StringRef Mnemonic,	---	4645	static bool AMDGPUCheckMnemonic(StringRef Mnemonic,	---
4646	const FeatureBitset &AvailableFeatures,	---	4646	const FeatureBitset &AvailableFeatures,	---
4647	unsigned VariantID);	---	4647	unsigned VariantID);	---
4648		---	4648		---
4649	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	0	4649	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	0
4650	const FeatureBitset &FBS) {	---	4650	const FeatureBitset &FBS) {	---
4651	return isSupportedMnemo(Mnemo, FBS, getAllVariants());	0	4651	return isSupportedMnemo(Mnemo, FBS, getAllVariants());	0
4652	}	---	4652	}	---
4653		---	4653		---
4654	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	0	4654	bool AMDGPUAsmParser::isSupportedMnemo(StringRef Mnemo,	0
4655	const FeatureBitset &FBS,	---	4655	const FeatureBitset &FBS,	---
4656	ArrayRef Variants) {	---	4656	ArrayRef Variants) {	---
4657	for (auto Variant : Variants) {	0	4657	for (auto Variant : Variants) {	0
4658	if (AMDGPUCheckMnemonic(Mnemo, FBS, Variant))	0	4658	if (AMDGPUCheckMnemonic(Mnemo, FBS, Variant))	0
4659	return true;	0	4659	return true;	0
4660	}	---	4660	}	---
4661		---	4661		---
4662	return false;	0	4662	return false;	0
4663	}	---	4663	}	---
4664		---	4664		---
4665	bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,	0	4665	bool AMDGPUAsmParser::checkUnsupportedInstruction(StringRef Mnemo,	0
4666	const SMLoc &IDLoc) {	---	4666	const SMLoc &IDLoc) {	---
4667	FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());	0	4667	FeatureBitset FBS = ComputeAvailableFeatures(getFeatureBits());	0
4668		---	4668		---
4669	// Check if requested instruction variant is supported.	---	4669	// Check if requested instruction variant is supported.	---
4670	if (isSupportedMnemo(Mnemo, FBS, getMatchedVariants()))	0	4670	if (isSupportedMnemo(Mnemo, FBS, getMatchedVariants()))	0
4671	return false;	0	4671	return false;	0
4672		---	4672		---
4673	// This instruction is not supported.	---	4673	// This instruction is not supported.	---
4674	// Clear any other pending errors because they are no longer relevant.	---	4674	// Clear any other pending errors because they are no longer relevant.	---
4675	getParser().clearPendingErrors();	0	4675	getParser().clearPendingErrors();	0
4676		---	4676		---
4677	// Requested instruction variant is not supported.	---	4677	// Requested instruction variant is not supported.	---
4678	// Check if any other variants are supported.	---	4678	// Check if any other variants are supported.	---
4679	StringRef VariantName = getMatchedVariantName();	0	4679	StringRef VariantName = getMatchedVariantName();	0
4680	if (!VariantName.empty() && isSupportedMnemo(Mnemo, FBS)) {	0	4680	if (!VariantName.empty() && isSupportedMnemo(Mnemo, FBS)) {	0
4681	return Error(IDLoc,	0	4681	return Error(IDLoc,	0
4682	Twine(VariantName,	0	4682	Twine(VariantName,	0
4683	" variant of this instruction is not supported"));	0	4683	" variant of this instruction is not supported"));	0
4684	}	---	4684	}	---
4685		---	4685		---
4686	// Check if this instruction may be used with a different wavesize.	---	4686	// Check if this instruction may be used with a different wavesize.	---
4687	if (isGFX10Plus() && getFeatureBits()[AMDGPU::FeatureWavefrontSize64] &&	0	4687	if (isGFX10Plus() && getFeatureBits()[AMDGPU::FeatureWavefrontSize64] &&	0
4688	!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) {	0	4688	!getFeatureBits()[AMDGPU::FeatureWavefrontSize32]) {	0
4689		---	4689		---
4690	FeatureBitset FeaturesWS32 = getFeatureBits();	0	4690	FeatureBitset FeaturesWS32 = getFeatureBits();	0
4691	FeaturesWS32.flip(AMDGPU::FeatureWavefrontSize64)	0	4691	FeaturesWS32.flip(AMDGPU::FeatureWavefrontSize64)	0
4692	.flip(AMDGPU::FeatureWavefrontSize32);	0	4692	.flip(AMDGPU::FeatureWavefrontSize32);	0
4693	FeatureBitset AvailableFeaturesWS32 =	---	4693	FeatureBitset AvailableFeaturesWS32 =	---
4694	ComputeAvailableFeatures(FeaturesWS32);	0	4694	ComputeAvailableFeatures(FeaturesWS32);	0
4695		---	4695		---
4696	if (isSupportedMnemo(Mnemo, AvailableFeaturesWS32, getMatchedVariants()))	0	4696	if (isSupportedMnemo(Mnemo, AvailableFeaturesWS32, getMatchedVariants()))	0
4697	return Error(IDLoc, "instruction requires wavesize=32");	0	4697	return Error(IDLoc, "instruction requires wavesize=32");	0
4698	}	---	4698	}	---
4699		---	4699		---
4700	// Finally check if this instruction is supported on any other GPU.	---	4700	// Finally check if this instruction is supported on any other GPU.	---
4701	if (isSupportedMnemo(Mnemo, FeatureBitset().set())) {	0	4701	if (isSupportedMnemo(Mnemo, FeatureBitset().set())) {	0
4702	return Error(IDLoc, "instruction not supported on this GPU");	0	4702	return Error(IDLoc, "instruction not supported on this GPU");	0
4703	}	---	4703	}	---
4704		---	4704		---
4705	// Instruction not supported on any GPU. Probably a typo.	---	4705	// Instruction not supported on any GPU. Probably a typo.	---
4706	std::string Suggestion = AMDGPUMnemonicSpellCheck(Mnemo, FBS);	0	4706	std::string Suggestion = AMDGPUMnemonicSpellCheck(Mnemo, FBS);	0
4707	return Error(IDLoc, "invalid instruction" + Suggestion);	0	4707	return Error(IDLoc, "invalid instruction" + Suggestion);	0
4708	}	0	4708	}	0
4709		---	4709		---
4710	static bool isInvalidVOPDY(const OperandVector &Operands,	0	4710	static bool isInvalidVOPDY(const OperandVector &Operands,	0
4711	uint64_t InvalidOprIdx) {	---	4711	uint64_t InvalidOprIdx) {	---
4712	assert(InvalidOprIdx < Operands.size());	0	4712	assert(InvalidOprIdx < Operands.size());	0
4713	const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);	0	4713	const auto &Op = ((AMDGPUOperand &)*Operands[InvalidOprIdx]);	0
4714	if (Op.isToken() && InvalidOprIdx > 1) {	0	4714	if (Op.isToken() && InvalidOprIdx > 1) {	0
4715	const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);	0	4715	const auto &PrevOp = ((AMDGPUOperand &)*Operands[InvalidOprIdx - 1]);	0
4716	return PrevOp.isToken() && PrevOp.getToken() == "::";	0	4716	return PrevOp.isToken() && PrevOp.getToken() == "::";	0
4717	}	---	4717	}	---
4718	return false;	0	4718	return false;	0
4719	}	---	4719	}	---
4720		---	4720		---
4721	bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	0	4721	bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,	0
4722	OperandVector &Operands,	---	4722	OperandVector &Operands,	---
4723	MCStreamer &Out,	---	4723	MCStreamer &Out,	---
4724	uint64_t &ErrorInfo,	---	4724	uint64_t &ErrorInfo,	---
4725	bool MatchingInlineAsm) {	---	4725	bool MatchingInlineAsm) {	---
4726	MCInst Inst;	0	4726	MCInst Inst;	0
4727	unsigned Result = Match_Success;	0	4727	unsigned Result = Match_Success;	0
4728	for (auto Variant : getMatchedVariants()) {	0	4728	for (auto Variant : getMatchedVariants()) {	0
4729	uint64_t EI;	---	4729	uint64_t EI;	---
4730	auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,	0	4730	auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,	0
4731	Variant);	---	4731	Variant);	---
4732	// We order match statuses from least to most specific. We use most specific	---	4732	// We order match statuses from least to most specific. We use most specific	---
4733	// status as resulting	---	4733	// status as resulting	---
4734	// Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32	---	4734	// Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature < Match_PreferE32	---
4735	if ((R == Match_Success) \|\|	0	4735	if ((R == Match_Success) \|\|	0
4736	(R == Match_PreferE32) \|\|	0	4736	(R == Match_PreferE32) \|\|	0
4737	(R == Match_MissingFeature && Result != Match_PreferE32) \|\|	0	4737	(R == Match_MissingFeature && Result != Match_PreferE32) \|\|	0
4738	(R == Match_InvalidOperand && Result != Match_MissingFeature	0	4738	(R == Match_InvalidOperand && Result != Match_MissingFeature	0
4739	&& Result != Match_PreferE32) \|\|	0	4739	&& Result != Match_PreferE32) \|\|	0
4740	(R == Match_MnemonicFail && Result != Match_InvalidOperand	0	4740	(R == Match_MnemonicFail && Result != Match_InvalidOperand	0
4741	&& Result != Match_MissingFeature	0	4741	&& Result != Match_MissingFeature	0
4742	&& Result != Match_PreferE32)) {	0	4742	&& Result != Match_PreferE32)) {	0
4743	Result = R;	0	4743	Result = R;	0
4744	ErrorInfo = EI;	0	4744	ErrorInfo = EI;	0
4745	}	---	4745	}	---
4746	if (R == Match_Success)	0	4746	if (R == Match_Success)	0
4747	break;	0	4747	break;	0
4748	}	---	4748	}	---
4749		---	4749		---
4750	if (Result == Match_Success) {	0	4750	if (Result == Match_Success) {	0
4751	if (!validateInstruction(Inst, IDLoc, Operands)) {	0	4751	if (!validateInstruction(Inst, IDLoc, Operands)) {	0
4752	return true;	0	4752	return true;	0
4753	}	---	4753	}	---
4754	Inst.setLoc(IDLoc);	0	4754	Inst.setLoc(IDLoc);	0
4755	Out.emitInstruction(Inst, getSTI());	0	4755	Out.emitInstruction(Inst, getSTI());	0
4756	return false;	0	4756	return false;	0
4757	}	---	4757	}	---
4758		---	4758		---
4759	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	0	4759	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	0
4760	if (checkUnsupportedInstruction(Mnemo, IDLoc)) {	0	4760	if (checkUnsupportedInstruction(Mnemo, IDLoc)) {	0
4761	return true;	0	4761	return true;	0
4762	}	---	4762	}	---
4763		---	4763		---
4764	switch (Result) {	0	4764	switch (Result) {	0
4765	default: break;	0	4765	default: break;	0
4766	case Match_MissingFeature:	0	4766	case Match_MissingFeature:	0
4767	// It has been verified that the specified instruction	---	4767	// It has been verified that the specified instruction	---
4768	// mnemonic is valid. A match was found but it requires	---	4768	// mnemonic is valid. A match was found but it requires	---
4769	// features which are not supported on this GPU.	---	4769	// features which are not supported on this GPU.	---
4770	return Error(IDLoc, "operands are not valid for this GPU or mode");	0	4770	return Error(IDLoc, "operands are not valid for this GPU or mode");	0
4771		---	4771		---
4772	case Match_InvalidOperand: {	0	4772	case Match_InvalidOperand: {	0
4773	SMLoc ErrorLoc = IDLoc;	0	4773	SMLoc ErrorLoc = IDLoc;	0
4774	if (ErrorInfo != ~0ULL) {	0	4774	if (ErrorInfo != ~0ULL) {	0
4775	if (ErrorInfo >= Operands.size()) {	0	4775	if (ErrorInfo >= Operands.size()) {	0
4776	return Error(IDLoc, "too few operands for instruction");	0	4776	return Error(IDLoc, "too few operands for instruction");	0
4777	}	---	4777	}	---
4778	ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();	0	4778	ErrorLoc = ((AMDGPUOperand &)*Operands[ErrorInfo]).getStartLoc();	0
4779	if (ErrorLoc == SMLoc())	0	4779	if (ErrorLoc == SMLoc())	0
4780	ErrorLoc = IDLoc;	0	4780	ErrorLoc = IDLoc;	0
4781		---	4781		---
4782	if (isInvalidVOPDY(Operands, ErrorInfo))	0	4782	if (isInvalidVOPDY(Operands, ErrorInfo))	0
4783	return Error(ErrorLoc, "invalid VOPDY instruction");	0	4783	return Error(ErrorLoc, "invalid VOPDY instruction");	0
4784	}	---	4784	}	---
4785	return Error(ErrorLoc, "invalid operand for instruction");	0	4785	return Error(ErrorLoc, "invalid operand for instruction");	0
4786	}	---	4786	}	---
4787		---	4787		---
4788	case Match_PreferE32:	0	4788	case Match_PreferE32:	0
4789	return Error(IDLoc, "internal error: instruction without _e64 suffix "	0	4789	return Error(IDLoc, "internal error: instruction without _e64 suffix "	0
4790	"should be encoded as e32");	0	4790	"should be encoded as e32");	0
4791	case Match_MnemonicFail:	0	4791	case Match_MnemonicFail:	0
4792	llvm_unreachable("Invalid instructions should have been handled already");	0	4792	llvm_unreachable("Invalid instructions should have been handled already");	0
4793	}	---	4793	}	---
4794	llvm_unreachable("Implement any new match types added!");	0	4794	llvm_unreachable("Implement any new match types added!");	0
4795	}	0	4795	}	0
4796		---	4796		---
4797	bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {	0	4797	bool AMDGPUAsmParser::ParseAsAbsoluteExpression(uint32_t &Ret) {	0
4798	int64_t Tmp = -1;	0	4798	int64_t Tmp = -1;	0
4799	if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {	0	4799	if (!isToken(AsmToken::Integer) && !isToken(AsmToken::Identifier)) {	0
4800	return true;	0	4800	return true;	0
4801	}	---	4801	}	---
4802	if (getParser().parseAbsoluteExpression(Tmp)) {	0	4802	if (getParser().parseAbsoluteExpression(Tmp)) {	0
4803	return true;	0	4803	return true;	0
4804	}	---	4804	}	---
4805	Ret = static_cast(Tmp);	0	4805	Ret = static_cast(Tmp);	0
4806	return false;	0	4806	return false;	0
4807	}	---	4807	}	---
4808		---	4808		---
4809	bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,	0	4809	bool AMDGPUAsmParser::ParseDirectiveMajorMinor(uint32_t &Major,	0
4810	uint32_t &Minor) {	---	4810	uint32_t &Minor) {	---
4811	if (ParseAsAbsoluteExpression(Major))	0	4811	if (ParseAsAbsoluteExpression(Major))	0
4812	return TokError("invalid major version");	0	4812	return TokError("invalid major version");	0
4813		---	4813		---
4814	if (!trySkipToken(AsmToken::Comma))	0	4814	if (!trySkipToken(AsmToken::Comma))	0
4815	return TokError("minor version number required, comma expected");	0	4815	return TokError("minor version number required, comma expected");	0
4816		---	4816		---
4817	if (ParseAsAbsoluteExpression(Minor))	0	4817	if (ParseAsAbsoluteExpression(Minor))	0
4818	return TokError("invalid minor version");	0	4818	return TokError("invalid minor version");	0
4819		---	4819		---
4820	return false;	0	4820	return false;	0
4821	}	---	4821	}	---
4822		---	4822		---
4823	bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {	0	4823	bool AMDGPUAsmParser::ParseDirectiveAMDGCNTarget() {	0
4824	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	0	4824	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	0
4825	return TokError("directive only supported for amdgcn architecture");	0	4825	return TokError("directive only supported for amdgcn architecture");	0
4826		---	4826		---
4827	std::string TargetIDDirective;	0	4827	std::string TargetIDDirective;	0
4828	SMLoc TargetStart = getTok().getLoc();	0	4828	SMLoc TargetStart = getTok().getLoc();	0
4829	if (getParser().parseEscapedString(TargetIDDirective))	0	4829	if (getParser().parseEscapedString(TargetIDDirective))	0
4830	return true;	0	4830	return true;	0
4831		---	4831		---
4832	SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());	0	4832	SMRange TargetRange = SMRange(TargetStart, getTok().getLoc());	0
4833	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	0	4833	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	0
4834	return getParser().Error(TargetRange.Start,	0	4834	return getParser().Error(TargetRange.Start,	0
4835	(Twine(".amdgcn_target directive's target id ") +	0	4835	(Twine(".amdgcn_target directive's target id ") +	0
4836	Twine(TargetIDDirective) +	0	4836	Twine(TargetIDDirective) +	0
4837	Twine(" does not match the specified target id ") +	0	4837	Twine(" does not match the specified target id ") +	0
4838	Twine(getTargetStreamer().getTargetID()->toString())).str());	0	4838	Twine(getTargetStreamer().getTargetID()->toString())).str());	0
4839		---	4839		---
4840	return false;	0	4840	return false;	0
4841	}	0	4841	}	0
4842		---	4842		---
4843	bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {	0	4843	bool AMDGPUAsmParser::OutOfRangeError(SMRange Range) {	0
4844	return Error(Range.Start, "value out of range", Range);	0	4844	return Error(Range.Start, "value out of range", Range);	0
4845	}	---	4845	}	---
4846		---	4846		---
4847	bool AMDGPUAsmParser::calculateGPRBlocks(	0	4847	bool AMDGPUAsmParser::calculateGPRBlocks(	0
4848	const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,	---	4848	const FeatureBitset &Features, bool VCCUsed, bool FlatScrUsed,	---
4849	bool XNACKUsed, std::optional EnableWavefrontSize32,	---	4849	bool XNACKUsed, std::optional EnableWavefrontSize32,	---
4850	unsigned NextFreeVGPR, SMRange VGPRRange, unsigned NextFreeSGPR,	---	4850	unsigned NextFreeVGPR, SMRange VGPRRange, unsigned NextFreeSGPR,	---
4851	SMRange SGPRRange, unsigned &VGPRBlocks, unsigned &SGPRBlocks) {	---	4851	SMRange SGPRRange, unsigned &VGPRBlocks, unsigned &SGPRBlocks) {	---
4852	// TODO(scott.linder): These calculations are duplicated from	---	4852	// TODO(scott.linder): These calculations are duplicated from	---
4853	// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.	---	4853	// AMDGPUAsmPrinter::getSIProgramInfo and could be unified.	---
4854	IsaVersion Version = getIsaVersion(getSTI().getCPU());	0	4854	IsaVersion Version = getIsaVersion(getSTI().getCPU());	0
4855		---	4855		---
4856	unsigned NumVGPRs = NextFreeVGPR;	0	4856	unsigned NumVGPRs = NextFreeVGPR;	0
4857	unsigned NumSGPRs = NextFreeSGPR;	0	4857	unsigned NumSGPRs = NextFreeSGPR;	0
4858		---	4858		---
4859	if (Version.Major >= 10)	0	4859	if (Version.Major >= 10)	0
4860	NumSGPRs = 0;	0	4860	NumSGPRs = 0;	0
4861	else {	---	4861	else {	---
4862	unsigned MaxAddressableNumSGPRs =	---	4862	unsigned MaxAddressableNumSGPRs =	---
4863	IsaInfo::getAddressableNumSGPRs(&getSTI());	0	4863	IsaInfo::getAddressableNumSGPRs(&getSTI());	0
4864		---	4864		---
4865	if (Version.Major >= 8 && !Features.test(FeatureSGPRInitBug) &&	0	4865	if (Version.Major >= 8 && !Features.test(FeatureSGPRInitBug) &&	0
4866	NumSGPRs > MaxAddressableNumSGPRs)	---	4866	NumSGPRs > MaxAddressableNumSGPRs)	---
4867	return OutOfRangeError(SGPRRange);	0	4867	return OutOfRangeError(SGPRRange);	0
4868		---	4868		---
4869	NumSGPRs +=	0	4869	NumSGPRs +=	0
4870	IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);	0	4870	IsaInfo::getNumExtraSGPRs(&getSTI(), VCCUsed, FlatScrUsed, XNACKUsed);	0
4871		---	4871		---
4872	if ((Version.Major <= 7 \|\| Features.test(FeatureSGPRInitBug)) &&	0	4872	if ((Version.Major <= 7 \|\| Features.test(FeatureSGPRInitBug)) &&	0
4873	NumSGPRs > MaxAddressableNumSGPRs)	---	4873	NumSGPRs > MaxAddressableNumSGPRs)	---
4874	return OutOfRangeError(SGPRRange);	0	4874	return OutOfRangeError(SGPRRange);	0
4875		---	4875		---
4876	if (Features.test(FeatureSGPRInitBug))	0	4876	if (Features.test(FeatureSGPRInitBug))	0
4877	NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;	0	4877	NumSGPRs = IsaInfo::FIXED_NUM_SGPRS_FOR_INIT_BUG;	0
4878	}	---	4878	}	---
4879		---	4879		---
4880	VGPRBlocks =	0	4880	VGPRBlocks =	0
4881	IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);	0	4881	IsaInfo::getNumVGPRBlocks(&getSTI(), NumVGPRs, EnableWavefrontSize32);	0
4882	SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);	0	4882	SGPRBlocks = IsaInfo::getNumSGPRBlocks(&getSTI(), NumSGPRs);	0
4883		---	4883		---
4884	return false;	0	4884	return false;	0
4885	}	---	4885	}	---
4886		---	4886		---
4887	bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {	0	4887	bool AMDGPUAsmParser::ParseDirectiveAMDHSAKernel() {	0
4888	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	0	4888	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn)	0
4889	return TokError("directive only supported for amdgcn architecture");	0	4889	return TokError("directive only supported for amdgcn architecture");	0
4890		---	4890		---
4891	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)	0	4891	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA)	0
4892	return TokError("directive only supported for amdhsa OS");	0	4892	return TokError("directive only supported for amdhsa OS");	0
4893		---	4893		---
4894	StringRef KernelName;	0	4894	StringRef KernelName;	0
4895	if (getParser().parseIdentifier(KernelName))	0	4895	if (getParser().parseIdentifier(KernelName))	0
4896	return true;	0	4896	return true;	0
4897		---	4897		---
4898	kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());	0	4898	kernel_descriptor_t KD = getDefaultAmdhsaKernelDescriptor(&getSTI());	0
4899		---	4899		---
4900	StringSet<> Seen;	0	4900	StringSet<> Seen;	0
4901		---	4901		---
4902	IsaVersion IVersion = getIsaVersion(getSTI().getCPU());	0	4902	IsaVersion IVersion = getIsaVersion(getSTI().getCPU());	0
4903		---	4903		---
4904	SMRange VGPRRange;	0	4904	SMRange VGPRRange;	0
4905	uint64_t NextFreeVGPR = 0;	0	4905	uint64_t NextFreeVGPR = 0;	0
4906	uint64_t AccumOffset = 0;	0	4906	uint64_t AccumOffset = 0;	0
4907	uint64_t SharedVGPRCount = 0;	0	4907	uint64_t SharedVGPRCount = 0;	0
4908	SMRange SGPRRange;	0	4908	SMRange SGPRRange;	0
4909	uint64_t NextFreeSGPR = 0;	0	4909	uint64_t NextFreeSGPR = 0;	0
4910		---	4910		---
4911	// Count the number of user SGPRs implied from the enabled feature bits.	---	4911	// Count the number of user SGPRs implied from the enabled feature bits.	---
4912	unsigned ImpliedUserSGPRCount = 0;	0	4912	unsigned ImpliedUserSGPRCount = 0;	0
4913		---	4913		---
4914	// Track if the asm explicitly contains the directive for the user SGPR	---	4914	// Track if the asm explicitly contains the directive for the user SGPR	---
4915	// count.	---	4915	// count.	---
4916	std::optional ExplicitUserSGPRCount;	0	4916	std::optional ExplicitUserSGPRCount;	0
4917	bool ReserveVCC = true;	0	4917	bool ReserveVCC = true;	0
4918	bool ReserveFlatScr = true;	0	4918	bool ReserveFlatScr = true;	0
4919	std::optional EnableWavefrontSize32;	0	4919	std::optional EnableWavefrontSize32;	0
4920		---	4920		---
4921	while (true) {	---	4921	while (true) {	---
4922	while (trySkipToken(AsmToken::EndOfStatement));	0	4922	while (trySkipToken(AsmToken::EndOfStatement));	0
4923		---	4923		---
4924	StringRef ID;	0	4924	StringRef ID;	0
4925	SMRange IDRange = getTok().getLocRange();	0	4925	SMRange IDRange = getTok().getLocRange();	0
4926	if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))	0	4926	if (!parseId(ID, "expected .amdhsa_ directive or .end_amdhsa_kernel"))	0
4927	return true;	0	4927	return true;	0
4928		---	4928		---
4929	if (ID == ".end_amdhsa_kernel")	0	4929	if (ID == ".end_amdhsa_kernel")	0
4930	break;	0	4930	break;	0
4931		---	4931		---
4932	if (!Seen.insert(ID).second)	0	4932	if (!Seen.insert(ID).second)	0
4933	return TokError(".amdhsa_ directives cannot be repeated");	0	4933	return TokError(".amdhsa_ directives cannot be repeated");	0
4934		---	4934		---
4935	SMLoc ValStart = getLoc();	0	4935	SMLoc ValStart = getLoc();	0
4936	int64_t IVal;	---	4936	int64_t IVal;	---
4937	if (getParser().parseAbsoluteExpression(IVal))	0	4937	if (getParser().parseAbsoluteExpression(IVal))	0
4938	return true;	0	4938	return true;	0
4939	SMLoc ValEnd = getLoc();	0	4939	SMLoc ValEnd = getLoc();	0
4940	SMRange ValRange = SMRange(ValStart, ValEnd);	0	4940	SMRange ValRange = SMRange(ValStart, ValEnd);	0
4941		---	4941		---
4942	if (IVal < 0)	0	4942	if (IVal < 0)	0
4943	return OutOfRangeError(ValRange);	0	4943	return OutOfRangeError(ValRange);	0
4944		---	4944		---
4945	uint64_t Val = IVal;	0	4945	uint64_t Val = IVal;	0
4946		---	4946		---
4947	#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE) \	---	4947	#define PARSE_BITS_ENTRY(FIELD, ENTRY, VALUE, RANGE) \	---
4948	if (!isUInt(VALUE)) \	---	4948	if (!isUInt(VALUE)) \	---
4949	return OutOfRangeError(RANGE); \	---	4949	return OutOfRangeError(RANGE); \	---
4950	AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);	---	4950	AMDHSA_BITS_SET(FIELD, ENTRY, VALUE);	---
4951		---	4951		---
4952	if (ID == ".amdhsa_group_segment_fixed_size") {	0	4952	if (ID == ".amdhsa_group_segment_fixed_size") {	0
4953	if (!isUInt(Val))	0	4953	if (!isUInt(Val))	0
4954	return OutOfRangeError(ValRange);	0	4954	return OutOfRangeError(ValRange);	0
4955	KD.group_segment_fixed_size = Val;	0	4955	KD.group_segment_fixed_size = Val;	0
4956	} else if (ID == ".amdhsa_private_segment_fixed_size") {	0	4956	} else if (ID == ".amdhsa_private_segment_fixed_size") {	0
4957	if (!isUInt(Val))	0	4957	if (!isUInt(Val))	0
4958	return OutOfRangeError(ValRange);	0	4958	return OutOfRangeError(ValRange);	0
4959	KD.private_segment_fixed_size = Val;	0	4959	KD.private_segment_fixed_size = Val;	0
4960	} else if (ID == ".amdhsa_kernarg_size") {	0	4960	} else if (ID == ".amdhsa_kernarg_size") {	0
4961	if (!isUInt(Val))	0	4961	if (!isUInt(Val))	0
4962	return OutOfRangeError(ValRange);	0	4962	return OutOfRangeError(ValRange);	0
4963	KD.kernarg_size = Val;	0	4963	KD.kernarg_size = Val;	0
4964	} else if (ID == ".amdhsa_user_sgpr_count") {	0	4964	} else if (ID == ".amdhsa_user_sgpr_count") {	0
4965	ExplicitUserSGPRCount = Val;	0	4965	ExplicitUserSGPRCount = Val;	0
4966	} else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {	0	4966	} else if (ID == ".amdhsa_user_sgpr_private_segment_buffer") {	0
4967	if (hasArchitectedFlatScratch())	0	4967	if (hasArchitectedFlatScratch())	0
4968	return Error(IDRange.Start,	0	4968	return Error(IDRange.Start,	0
4969	"directive is not supported with architected flat scratch",	---	4969	"directive is not supported with architected flat scratch",	---
4970	IDRange);	0	4970	IDRange);	0
4971	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	4971	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4972	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,	---	4972	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,	---
4973	Val, ValRange);	---	4973	Val, ValRange);	---
4974	if (Val)	0	4974	if (Val)	0
4975	ImpliedUserSGPRCount += 4;	0	4975	ImpliedUserSGPRCount += 4;	0
4976	} else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {	0	4976	} else if (ID == ".amdhsa_user_sgpr_dispatch_ptr") {	0
4977	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	4977	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4978	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,	---	4978	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR, Val,	---
4979	ValRange);	---	4979	ValRange);	---
4980	if (Val)	0	4980	if (Val)	0
4981	ImpliedUserSGPRCount += 2;	0	4981	ImpliedUserSGPRCount += 2;	0
4982	} else if (ID == ".amdhsa_user_sgpr_queue_ptr") {	0	4982	} else if (ID == ".amdhsa_user_sgpr_queue_ptr") {	0
4983	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	4983	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4984	KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,	---	4984	KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR, Val,	---
4985	ValRange);	---	4985	ValRange);	---
4986	if (Val)	0	4986	if (Val)	0
4987	ImpliedUserSGPRCount += 2;	0	4987	ImpliedUserSGPRCount += 2;	0
4988	} else if (ID == ".amdhsa_user_sgpr_kernarg_segment_ptr") {	0	4988	} else if (ID == ".amdhsa_user_sgpr_kernarg_segment_ptr") {	0
4989	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	4989	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4990	KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,	---	4990	KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,	---
4991	Val, ValRange);	---	4991	Val, ValRange);	---
4992	if (Val)	0	4992	if (Val)	0
4993	ImpliedUserSGPRCount += 2;	0	4993	ImpliedUserSGPRCount += 2;	0
4994	} else if (ID == ".amdhsa_user_sgpr_dispatch_id") {	0	4994	} else if (ID == ".amdhsa_user_sgpr_dispatch_id") {	0
4995	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	4995	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
4996	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,	---	4996	KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID, Val,	---
4997	ValRange);	---	4997	ValRange);	---
4998	if (Val)	0	4998	if (Val)	0
4999	ImpliedUserSGPRCount += 2;	0	4999	ImpliedUserSGPRCount += 2;	0
5000	} else if (ID == ".amdhsa_user_sgpr_flat_scratch_init") {	0	5000	} else if (ID == ".amdhsa_user_sgpr_flat_scratch_init") {	0
5001	if (hasArchitectedFlatScratch())	0	5001	if (hasArchitectedFlatScratch())	0
5002	return Error(IDRange.Start,	0	5002	return Error(IDRange.Start,	0
5003	"directive is not supported with architected flat scratch",	---	5003	"directive is not supported with architected flat scratch",	---
5004	IDRange);	0	5004	IDRange);	0
5005	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	5005	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5006	KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,	---	5006	KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT, Val,	---
5007	ValRange);	---	5007	ValRange);	---
5008	if (Val)	0	5008	if (Val)	0
5009	ImpliedUserSGPRCount += 2;	0	5009	ImpliedUserSGPRCount += 2;	0
5010	} else if (ID == ".amdhsa_user_sgpr_private_segment_size") {	0	5010	} else if (ID == ".amdhsa_user_sgpr_private_segment_size") {	0
5011	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	5011	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5012	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,	---	5012	KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,	---
5013	Val, ValRange);	---	5013	Val, ValRange);	---
5014	if (Val)	0	5014	if (Val)	0
5015	ImpliedUserSGPRCount += 1;	0	5015	ImpliedUserSGPRCount += 1;	0
5016	} else if (ID == ".amdhsa_wavefront_size32") {	0	5016	} else if (ID == ".amdhsa_wavefront_size32") {	0
5017	if (IVersion.Major < 10)	0	5017	if (IVersion.Major < 10)	0
5018	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0	5018	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5019	EnableWavefrontSize32 = Val;	0	5019	EnableWavefrontSize32 = Val;	0
5020	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	5020	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5021	KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,	---	5021	KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,	---
5022	Val, ValRange);	---	5022	Val, ValRange);	---
5023	} else if (ID == ".amdhsa_uses_dynamic_stack") {	0	5023	} else if (ID == ".amdhsa_uses_dynamic_stack") {	0
5024	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0	5024	PARSE_BITS_ENTRY(KD.kernel_code_properties,	0
5025	KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, Val, ValRange);	---	5025	KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK, Val, ValRange);	---
5026	} else if (ID == ".amdhsa_system_sgpr_private_segment_wavefront_offset") {	0	5026	} else if (ID == ".amdhsa_system_sgpr_private_segment_wavefront_offset") {	0
5027	if (hasArchitectedFlatScratch())	0	5027	if (hasArchitectedFlatScratch())	0
5028	return Error(IDRange.Start,	0	5028	return Error(IDRange.Start,	0
5029	"directive is not supported with architected flat scratch",	---	5029	"directive is not supported with architected flat scratch",	---
5030	IDRange);	0	5030	IDRange);	0
5031	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5031	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5032	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	---	5032	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	---
5033	} else if (ID == ".amdhsa_enable_private_segment") {	0	5033	} else if (ID == ".amdhsa_enable_private_segment") {	0
5034	if (!hasArchitectedFlatScratch())	0	5034	if (!hasArchitectedFlatScratch())	0
5035	return Error(	0	5035	return Error(	0
5036	IDRange.Start,	---	5036	IDRange.Start,	---
5037	"directive is not supported without architected flat scratch",	---	5037	"directive is not supported without architected flat scratch",	---
5038	IDRange);	0	5038	IDRange);	0
5039	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5039	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5040	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	---	5040	COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT, Val, ValRange);	---
5041	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_x") {	0	5041	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_x") {	0
5042	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5042	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5043	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,	---	5043	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X, Val,	---
5044	ValRange);	---	5044	ValRange);	---
5045	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_y") {	0	5045	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_y") {	0
5046	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5046	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5047	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,	---	5047	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y, Val,	---
5048	ValRange);	---	5048	ValRange);	---
5049	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_z") {	0	5049	} else if (ID == ".amdhsa_system_sgpr_workgroup_id_z") {	0
5050	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5050	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5051	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,	---	5051	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z, Val,	---
5052	ValRange);	---	5052	ValRange);	---
5053	} else if (ID == ".amdhsa_system_sgpr_workgroup_info") {	0	5053	} else if (ID == ".amdhsa_system_sgpr_workgroup_info") {	0
5054	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5054	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5055	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,	---	5055	COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO, Val,	---
5056	ValRange);	---	5056	ValRange);	---
5057	} else if (ID == ".amdhsa_system_vgpr_workitem_id") {	0	5057	} else if (ID == ".amdhsa_system_vgpr_workitem_id") {	0
5058	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5058	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5059	COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,	---	5059	COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID, Val,	---
5060	ValRange);	---	5060	ValRange);	---
5061	} else if (ID == ".amdhsa_next_free_vgpr") {	0	5061	} else if (ID == ".amdhsa_next_free_vgpr") {	0
5062	VGPRRange = ValRange;	0	5062	VGPRRange = ValRange;	0
5063	NextFreeVGPR = Val;	0	5063	NextFreeVGPR = Val;	0
5064	} else if (ID == ".amdhsa_next_free_sgpr") {	0	5064	} else if (ID == ".amdhsa_next_free_sgpr") {	0
5065	SGPRRange = ValRange;	0	5065	SGPRRange = ValRange;	0
5066	NextFreeSGPR = Val;	0	5066	NextFreeSGPR = Val;	0
5067	} else if (ID == ".amdhsa_accum_offset") {	0	5067	} else if (ID == ".amdhsa_accum_offset") {	0
5068	if (!isGFX90A())	0	5068	if (!isGFX90A())	0
5069	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	0	5069	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	0
5070	AccumOffset = Val;	0	5070	AccumOffset = Val;	0
5071	} else if (ID == ".amdhsa_reserve_vcc") {	0	5071	} else if (ID == ".amdhsa_reserve_vcc") {	0
5072	if (!isUInt<1>(Val))	0	5072	if (!isUInt<1>(Val))	0
5073	return OutOfRangeError(ValRange);	0	5073	return OutOfRangeError(ValRange);	0
5074	ReserveVCC = Val;	0	5074	ReserveVCC = Val;	0
5075	} else if (ID == ".amdhsa_reserve_flat_scratch") {	0	5075	} else if (ID == ".amdhsa_reserve_flat_scratch") {	0
5076	if (IVersion.Major < 7)	0	5076	if (IVersion.Major < 7)	0
5077	return Error(IDRange.Start, "directive requires gfx7+", IDRange);	0	5077	return Error(IDRange.Start, "directive requires gfx7+", IDRange);	0
5078	if (hasArchitectedFlatScratch())	0	5078	if (hasArchitectedFlatScratch())	0
5079	return Error(IDRange.Start,	0	5079	return Error(IDRange.Start,	0
5080	"directive is not supported with architected flat scratch",	---	5080	"directive is not supported with architected flat scratch",	---
5081	IDRange);	0	5081	IDRange);	0
5082	if (!isUInt<1>(Val))	0	5082	if (!isUInt<1>(Val))	0
5083	return OutOfRangeError(ValRange);	0	5083	return OutOfRangeError(ValRange);	0
5084	ReserveFlatScr = Val;	0	5084	ReserveFlatScr = Val;	0
5085	} else if (ID == ".amdhsa_reserve_xnack_mask") {	0	5085	} else if (ID == ".amdhsa_reserve_xnack_mask") {	0
5086	if (IVersion.Major < 8)	0	5086	if (IVersion.Major < 8)	0
5087	return Error(IDRange.Start, "directive requires gfx8+", IDRange);	0	5087	return Error(IDRange.Start, "directive requires gfx8+", IDRange);	0
5088	if (!isUInt<1>(Val))	0	5088	if (!isUInt<1>(Val))	0
5089	return OutOfRangeError(ValRange);	0	5089	return OutOfRangeError(ValRange);	0
5090	if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())	0	5090	if (Val != getTargetStreamer().getTargetID()->isXnackOnOrAny())	0
5091	return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",	0	5091	return getParser().Error(IDRange.Start, ".amdhsa_reserve_xnack_mask does not match target id",	0
5092	IDRange);	0	5092	IDRange);	0
5093	} else if (ID == ".amdhsa_float_round_mode_32") {	0	5093	} else if (ID == ".amdhsa_float_round_mode_32") {	0
5094	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0	5094	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5095	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);	---	5095	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32, Val, ValRange);	---
5096	} else if (ID == ".amdhsa_float_round_mode_16_64") {	0	5096	} else if (ID == ".amdhsa_float_round_mode_16_64") {	0
5097	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0	5097	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5098	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);	---	5098	COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64, Val, ValRange);	---
5099	} else if (ID == ".amdhsa_float_denorm_mode_32") {	0	5099	} else if (ID == ".amdhsa_float_denorm_mode_32") {	0
5100	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0	5100	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5101	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);	---	5101	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32, Val, ValRange);	---
5102	} else if (ID == ".amdhsa_float_denorm_mode_16_64") {	0	5102	} else if (ID == ".amdhsa_float_denorm_mode_16_64") {	0
5103	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0	5103	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5104	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,	---	5104	COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64, Val,	---
5105	ValRange);	---	5105	ValRange);	---
5106	} else if (ID == ".amdhsa_dx10_clamp") {	0	5106	} else if (ID == ".amdhsa_dx10_clamp") {	0
5107	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0	5107	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1,	0
5108	COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);	---	5108	COMPUTE_PGM_RSRC1_ENABLE_DX10_CLAMP, Val, ValRange);	---
5109	} else if (ID == ".amdhsa_ieee_mode") {	0	5109	} else if (ID == ".amdhsa_ieee_mode") {	0
5110	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,	0	5110	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_ENABLE_IEEE_MODE,	0
5111	Val, ValRange);	---	5111	Val, ValRange);	---
5112	} else if (ID == ".amdhsa_fp16_overflow") {	0	5112	} else if (ID == ".amdhsa_fp16_overflow") {	0
5113	if (IVersion.Major < 9)	0	5113	if (IVersion.Major < 9)	0
5114	return Error(IDRange.Start, "directive requires gfx9+", IDRange);	0	5114	return Error(IDRange.Start, "directive requires gfx9+", IDRange);	0
5115	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,	0	5115	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FP16_OVFL, Val,	0
5116	ValRange);	---	5116	ValRange);	---
5117	} else if (ID == ".amdhsa_tg_split") {	0	5117	} else if (ID == ".amdhsa_tg_split") {	0
5118	if (!isGFX90A())	0	5118	if (!isGFX90A())	0
5119	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	0	5119	return Error(IDRange.Start, "directive requires gfx90a+", IDRange);	0
5120	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Val,	0	5120	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT, Val,	0
5121	ValRange);	---	5121	ValRange);	---
5122	} else if (ID == ".amdhsa_workgroup_processor_mode") {	0	5122	} else if (ID == ".amdhsa_workgroup_processor_mode") {	0
5123	if (IVersion.Major < 10)	0	5123	if (IVersion.Major < 10)	0
5124	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0	5124	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5125	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,	0	5125	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_WGP_MODE, Val,	0
5126	ValRange);	---	5126	ValRange);	---
5127	} else if (ID == ".amdhsa_memory_ordered") {	0	5127	} else if (ID == ".amdhsa_memory_ordered") {	0
5128	if (IVersion.Major < 10)	0	5128	if (IVersion.Major < 10)	0
5129	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0	5129	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5130	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,	0	5130	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_MEM_ORDERED, Val,	0
5131	ValRange);	---	5131	ValRange);	---
5132	} else if (ID == ".amdhsa_forward_progress") {	0	5132	} else if (ID == ".amdhsa_forward_progress") {	0
5133	if (IVersion.Major < 10)	0	5133	if (IVersion.Major < 10)	0
5134	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0	5134	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5135	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,	0	5135	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc1, COMPUTE_PGM_RSRC1_FWD_PROGRESS, Val,	0
5136	ValRange);	---	5136	ValRange);	---
5137	} else if (ID == ".amdhsa_shared_vgpr_count") {	0	5137	} else if (ID == ".amdhsa_shared_vgpr_count") {	0
5138	if (IVersion.Major < 10)	0	5138	if (IVersion.Major < 10)	0
5139	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0	5139	return Error(IDRange.Start, "directive requires gfx10+", IDRange);	0
5140	SharedVGPRCount = Val;	0	5140	SharedVGPRCount = Val;	0
5141	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3,	0	5141	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc3,	0
5142	COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, Val,	---	5142	COMPUTE_PGM_RSRC3_GFX10_PLUS_SHARED_VGPR_COUNT, Val,	---
5143	ValRange);	---	5143	ValRange);	---
5144	} else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {	0	5144	} else if (ID == ".amdhsa_exception_fp_ieee_invalid_op") {	0
5145	PARSE_BITS_ENTRY(	0	5145	PARSE_BITS_ENTRY(	0
5146	KD.compute_pgm_rsrc2,	---	5146	KD.compute_pgm_rsrc2,	---
5147	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,	---	5147	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION, Val,	---
5148	ValRange);	---	5148	ValRange);	---
5149	} else if (ID == ".amdhsa_exception_fp_denorm_src") {	0	5149	} else if (ID == ".amdhsa_exception_fp_denorm_src") {	0
5150	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5150	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5151	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,	---	5151	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,	---
5152	Val, ValRange);	---	5152	Val, ValRange);	---
5153	} else if (ID == ".amdhsa_exception_fp_ieee_div_zero") {	0	5153	} else if (ID == ".amdhsa_exception_fp_ieee_div_zero") {	0
5154	PARSE_BITS_ENTRY(	0	5154	PARSE_BITS_ENTRY(	0
5155	KD.compute_pgm_rsrc2,	---	5155	KD.compute_pgm_rsrc2,	---
5156	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,	---	5156	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO, Val,	---
5157	ValRange);	---	5157	ValRange);	---
5158	} else if (ID == ".amdhsa_exception_fp_ieee_overflow") {	0	5158	} else if (ID == ".amdhsa_exception_fp_ieee_overflow") {	0
5159	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5159	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5160	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,	---	5160	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,	---
5161	Val, ValRange);	---	5161	Val, ValRange);	---
5162	} else if (ID == ".amdhsa_exception_fp_ieee_underflow") {	0	5162	} else if (ID == ".amdhsa_exception_fp_ieee_underflow") {	0
5163	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5163	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5164	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,	---	5164	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,	---
5165	Val, ValRange);	---	5165	Val, ValRange);	---
5166	} else if (ID == ".amdhsa_exception_fp_ieee_inexact") {	0	5166	} else if (ID == ".amdhsa_exception_fp_ieee_inexact") {	0
5167	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5167	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5168	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,	---	5168	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,	---
5169	Val, ValRange);	---	5169	Val, ValRange);	---
5170	} else if (ID == ".amdhsa_exception_int_div_zero") {	0	5170	} else if (ID == ".amdhsa_exception_int_div_zero") {	0
5171	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0	5171	PARSE_BITS_ENTRY(KD.compute_pgm_rsrc2,	0
5172	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,	---	5172	COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,	---
5173	Val, ValRange);	---	5173	Val, ValRange);	---
5174	} else {	---	5174	} else {	---
5175	return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange);	0	5175	return Error(IDRange.Start, "unknown .amdhsa_kernel directive", IDRange);	0
5176	}	---	5176	}	---
5177		---	5177		---
5178	#undef PARSE_BITS_ENTRY	---	5178	#undef PARSE_BITS_ENTRY	---
5179	}	0	5179	}	0
5180		---	5180		---
5181	if (!Seen.contains(".amdhsa_next_free_vgpr"))	0	5181	if (!Seen.contains(".amdhsa_next_free_vgpr"))	0
5182	return TokError(".amdhsa_next_free_vgpr directive is required");	0	5182	return TokError(".amdhsa_next_free_vgpr directive is required");	0
5183		---	5183		---
5184	if (!Seen.contains(".amdhsa_next_free_sgpr"))	0	5184	if (!Seen.contains(".amdhsa_next_free_sgpr"))	0
5185	return TokError(".amdhsa_next_free_sgpr directive is required");	0	5185	return TokError(".amdhsa_next_free_sgpr directive is required");	0
5186		---	5186		---
5187	unsigned VGPRBlocks;	---	5187	unsigned VGPRBlocks;	---
5188	unsigned SGPRBlocks;	---	5188	unsigned SGPRBlocks;	---
5189	if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,	0	5189	if (calculateGPRBlocks(getFeatureBits(), ReserveVCC, ReserveFlatScr,	0
5190	getTargetStreamer().getTargetID()->isXnackOnOrAny(),	0	5190	getTargetStreamer().getTargetID()->isXnackOnOrAny(),	0
5191	EnableWavefrontSize32, NextFreeVGPR,	---	5191	EnableWavefrontSize32, NextFreeVGPR,	---
5192	VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,	---	5192	VGPRRange, NextFreeSGPR, SGPRRange, VGPRBlocks,	---
5193	SGPRBlocks))	---	5193	SGPRBlocks))	---
5194	return true;	0	5194	return true;	0
5195		---	5195		---
5196	if (!isUInt(	0	5196	if (!isUInt(	0
5197	VGPRBlocks))	---	5197	VGPRBlocks))	---
5198	return OutOfRangeError(VGPRRange);	0	5198	return OutOfRangeError(VGPRRange);	0
5199	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	0	5199	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	0
5200	COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, VGPRBlocks);	---	5200	COMPUTE_PGM_RSRC1_GRANULATED_WORKITEM_VGPR_COUNT, VGPRBlocks);	---
5201		---	5201		---
5202	if (!isUInt(	0	5202	if (!isUInt(	0
5203	SGPRBlocks))	---	5203	SGPRBlocks))	---
5204	return OutOfRangeError(SGPRRange);	0	5204	return OutOfRangeError(SGPRRange);	0
5205	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	0	5205	AMDHSA_BITS_SET(KD.compute_pgm_rsrc1,	0
5206	COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT,	---	5206	COMPUTE_PGM_RSRC1_GRANULATED_WAVEFRONT_SGPR_COUNT,	---
5207	SGPRBlocks);	---	5207	SGPRBlocks);	---
5208		---	5208		---
5209	if (ExplicitUserSGPRCount && ImpliedUserSGPRCount > *ExplicitUserSGPRCount)	0	5209	if (ExplicitUserSGPRCount && ImpliedUserSGPRCount > *ExplicitUserSGPRCount)	0
5210	return TokError("amdgpu_user_sgpr_count smaller than than implied by "	0	5210	return TokError("amdgpu_user_sgpr_count smaller than than implied by "	0
5211	"enabled user SGPRs");	0	5211	"enabled user SGPRs");	0
5212		---	5212		---
5213	unsigned UserSGPRCount =	---	5213	unsigned UserSGPRCount =	---
5214	ExplicitUserSGPRCount ? *ExplicitUserSGPRCount : ImpliedUserSGPRCount;	0	5214	ExplicitUserSGPRCount ? *ExplicitUserSGPRCount : ImpliedUserSGPRCount;	0
5215		---	5215		---
5216	if (!isUInt(UserSGPRCount))	0	5216	if (!isUInt(UserSGPRCount))	0
5217	return TokError("too many user SGPRs enabled");	0	5217	return TokError("too many user SGPRs enabled");	0
5218	AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,	0	5218	AMDHSA_BITS_SET(KD.compute_pgm_rsrc2, COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,	0
5219	UserSGPRCount);	---	5219	UserSGPRCount);	---
5220		---	5220		---
5221	if (isGFX90A()) {	0	5221	if (isGFX90A()) {	0
5222	if (!Seen.contains(".amdhsa_accum_offset"))	0	5222	if (!Seen.contains(".amdhsa_accum_offset"))	0
5223	return TokError(".amdhsa_accum_offset directive is required");	0	5223	return TokError(".amdhsa_accum_offset directive is required");	0
5224	if (AccumOffset < 4 \|\| AccumOffset > 256 \|\| (AccumOffset & 3))	0	5224	if (AccumOffset < 4 \|\| AccumOffset > 256 \|\| (AccumOffset & 3))	0
5225	return TokError("accum_offset should be in range [4..256] in "	0	5225	return TokError("accum_offset should be in range [4..256] in "	0
5226	"increments of 4");	0	5226	"increments of 4");	0
5227	if (AccumOffset > alignTo(std::max((uint64_t)1, NextFreeVGPR), 4))	0	5227	if (AccumOffset > alignTo(std::max((uint64_t)1, NextFreeVGPR), 4))	0
5228	return TokError("accum_offset exceeds total VGPR allocation");	0	5228	return TokError("accum_offset exceeds total VGPR allocation");	0
5229	AMDHSA_BITS_SET(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,	0	5229	AMDHSA_BITS_SET(KD.compute_pgm_rsrc3, COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,	0
5230	(AccumOffset / 4 - 1));	---	5230	(AccumOffset / 4 - 1));	---
5231	}	---	5231	}	---
5232		---	5232		---
5233	if (IVersion.Major >= 10) {	0	5233	if (IVersion.Major >= 10) {	0
5234	// SharedVGPRCount < 16 checked by PARSE_ENTRY_BITS	---	5234	// SharedVGPRCount < 16 checked by PARSE_ENTRY_BITS	---
5235	if (SharedVGPRCount && EnableWavefrontSize32 && *EnableWavefrontSize32) {	0	5235	if (SharedVGPRCount && EnableWavefrontSize32 && *EnableWavefrontSize32) {	0
5236	return TokError("shared_vgpr_count directive not valid on "	0	5236	return TokError("shared_vgpr_count directive not valid on "	0
5237	"wavefront size 32");	0	5237	"wavefront size 32");	0
5238	}	---	5238	}	---
5239	if (SharedVGPRCount * 2 + VGPRBlocks > 63) {	0	5239	if (SharedVGPRCount * 2 + VGPRBlocks > 63) {	0
5240	return TokError("shared_vgpr_count*2 + "	0	5240	return TokError("shared_vgpr_count*2 + "	0
5241	"compute_pgm_rsrc1.GRANULATED_WORKITEM_VGPR_COUNT cannot "	---	5241	"compute_pgm_rsrc1.GRANULATED_WORKITEM_VGPR_COUNT cannot "	---
5242	"exceed 63\n");	0	5242	"exceed 63\n");	0
5243	}	---	5243	}	---
5244	}	---	5244	}	---
5245		---	5245		---
5246	getTargetStreamer().EmitAmdhsaKernelDescriptor(	0	5246	getTargetStreamer().EmitAmdhsaKernelDescriptor(	0
5247	getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,	---	5247	getSTI(), KernelName, KD, NextFreeVGPR, NextFreeSGPR, ReserveVCC,	---
5248	ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion());	---	5248	ReserveFlatScr, AMDGPU::getAmdhsaCodeObjectVersion());	---
5249	return false;	0	5249	return false;	0
5250	}	0	5250	}	0
5251		---	5251		---
5252	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {	0	5252	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectVersion() {	0
5253	uint32_t Major;	---	5253	uint32_t Major;	---
5254	uint32_t Minor;	---	5254	uint32_t Minor;	---
5255		---	5255		---
5256	if (ParseDirectiveMajorMinor(Major, Minor))	0	5256	if (ParseDirectiveMajorMinor(Major, Minor))	0
5257	return true;	0	5257	return true;	0
5258		---	5258		---
5259	getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);	0	5259	getTargetStreamer().EmitDirectiveHSACodeObjectVersion(Major, Minor);	0
5260	return false;	0	5260	return false;	0
5261	}	---	5261	}	---
5262		---	5262		---
5263	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {	0	5263	bool AMDGPUAsmParser::ParseDirectiveHSACodeObjectISA() {	0
5264	uint32_t Major;	---	5264	uint32_t Major;	---
5265	uint32_t Minor;	---	5265	uint32_t Minor;	---
5266	uint32_t Stepping;	---	5266	uint32_t Stepping;	---
5267	StringRef VendorName;	0	5267	StringRef VendorName;	0
5268	StringRef ArchName;	0	5268	StringRef ArchName;	0
5269		---	5269		---
5270	// If this directive has no arguments, then use the ISA version for the	---	5270	// If this directive has no arguments, then use the ISA version for the	---
5271	// targeted GPU.	---	5271	// targeted GPU.	---
5272	if (isToken(AsmToken::EndOfStatement)) {	0	5272	if (isToken(AsmToken::EndOfStatement)) {	0
5273	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0	5273	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
5274	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,	0	5274	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(ISA.Major, ISA.Minor,	0
5275	ISA.Stepping,	---	5275	ISA.Stepping,	---
5276	"AMD", "AMDGPU");	---	5276	"AMD", "AMDGPU");	---
5277	return false;	0	5277	return false;	0
5278	}	---	5278	}	---
5279		---	5279		---
5280	if (ParseDirectiveMajorMinor(Major, Minor))	0	5280	if (ParseDirectiveMajorMinor(Major, Minor))	0
5281	return true;	0	5281	return true;	0
5282		---	5282		---
5283	if (!trySkipToken(AsmToken::Comma))	0	5283	if (!trySkipToken(AsmToken::Comma))	0
5284	return TokError("stepping version number required, comma expected");	0	5284	return TokError("stepping version number required, comma expected");	0
5285		---	5285		---
5286	if (ParseAsAbsoluteExpression(Stepping))	0	5286	if (ParseAsAbsoluteExpression(Stepping))	0
5287	return TokError("invalid stepping version");	0	5287	return TokError("invalid stepping version");	0
5288		---	5288		---
5289	if (!trySkipToken(AsmToken::Comma))	0	5289	if (!trySkipToken(AsmToken::Comma))	0
5290	return TokError("vendor name required, comma expected");	0	5290	return TokError("vendor name required, comma expected");	0
5291		---	5291		---
5292	if (!parseString(VendorName, "invalid vendor name"))	0	5292	if (!parseString(VendorName, "invalid vendor name"))	0
5293	return true;	0	5293	return true;	0
5294		---	5294		---
5295	if (!trySkipToken(AsmToken::Comma))	0	5295	if (!trySkipToken(AsmToken::Comma))	0
5296	return TokError("arch name required, comma expected");	0	5296	return TokError("arch name required, comma expected");	0
5297		---	5297		---
5298	if (!parseString(ArchName, "invalid arch name"))	0	5298	if (!parseString(ArchName, "invalid arch name"))	0
5299	return true;	0	5299	return true;	0
5300		---	5300		---
5301	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,	0	5301	getTargetStreamer().EmitDirectiveHSACodeObjectISAV2(Major, Minor, Stepping,	0
5302	VendorName, ArchName);	---	5302	VendorName, ArchName);	---
5303	return false;	0	5303	return false;	0
5304	}	---	5304	}	---
5305		---	5305		---
5306	bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,	0	5306	bool AMDGPUAsmParser::ParseAMDKernelCodeTValue(StringRef ID,	0
5307	amd_kernel_code_t &Header) {	---	5307	amd_kernel_code_t &Header) {	---
5308	// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing	---	5308	// max_scratch_backing_memory_byte_size is deprecated. Ignore it while parsing	---
5309	// assembly for backwards compatibility.	---	5309	// assembly for backwards compatibility.	---
5310	if (ID == "max_scratch_backing_memory_byte_size") {	0	5310	if (ID == "max_scratch_backing_memory_byte_size") {	0
5311	Parser.eatToEndOfStatement();	0	5311	Parser.eatToEndOfStatement();	0
5312	return false;	0	5312	return false;	0
5313	}	---	5313	}	---
5314		---	5314		---
5315	SmallString<40> ErrStr;	0	5315	SmallString<40> ErrStr;	0
5316	raw_svector_ostream Err(ErrStr);	0	5316	raw_svector_ostream Err(ErrStr);	0
5317	if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {	0	5317	if (!parseAmdKernelCodeField(ID, getParser(), Header, Err)) {	0
5318	return TokError(Err.str());	0	5318	return TokError(Err.str());	0
5319	}	---	5319	}	---
5320	Lex();	0	5320	Lex();	0
5321		---	5321		---
5322	if (ID == "enable_wavefront_size32") {	0	5322	if (ID == "enable_wavefront_size32") {	0
5323	if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) {	0	5323	if (Header.code_properties & AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32) {	0
5324	if (!isGFX10Plus())	0	5324	if (!isGFX10Plus())	0
5325	return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");	0	5325	return TokError("enable_wavefront_size32=1 is only allowed on GFX10+");	0
5326	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	0	5326	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	0
5327	return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");	0	5327	return TokError("enable_wavefront_size32=1 requires +WavefrontSize32");	0
5328	} else {	---	5328	} else {	---
5329	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	0	5329	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	0
5330	return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");	0	5330	return TokError("enable_wavefront_size32=0 requires +WavefrontSize64");	0
5331	}	---	5331	}	---
5332	}	---	5332	}	---
5333		---	5333		---
5334	if (ID == "wavefront_size") {	0	5334	if (ID == "wavefront_size") {	0
5335	if (Header.wavefront_size == 5) {	0	5335	if (Header.wavefront_size == 5) {	0
5336	if (!isGFX10Plus())	0	5336	if (!isGFX10Plus())	0
5337	return TokError("wavefront_size=5 is only allowed on GFX10+");	0	5337	return TokError("wavefront_size=5 is only allowed on GFX10+");	0
5338	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	0	5338	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize32])	0
5339	return TokError("wavefront_size=5 requires +WavefrontSize32");	0	5339	return TokError("wavefront_size=5 requires +WavefrontSize32");	0
5340	} else if (Header.wavefront_size == 6) {	0	5340	} else if (Header.wavefront_size == 6) {	0
5341	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	0	5341	if (!getFeatureBits()[AMDGPU::FeatureWavefrontSize64])	0
5342	return TokError("wavefront_size=6 requires +WavefrontSize64");	0	5342	return TokError("wavefront_size=6 requires +WavefrontSize64");	0
5343	}	---	5343	}	---
5344	}	---	5344	}	---
5345		---	5345		---
5346	if (ID == "enable_wgp_mode") {	0	5346	if (ID == "enable_wgp_mode") {	0
5347	if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) &&	0	5347	if (G_00B848_WGP_MODE(Header.compute_pgm_resource_registers) &&	0
5348	!isGFX10Plus())	0	5348	!isGFX10Plus())	0
5349	return TokError("enable_wgp_mode=1 is only allowed on GFX10+");	0	5349	return TokError("enable_wgp_mode=1 is only allowed on GFX10+");	0
5350	}	---	5350	}	---
5351		---	5351		---
5352	if (ID == "enable_mem_ordered") {	0	5352	if (ID == "enable_mem_ordered") {	0
5353	if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) &&	0	5353	if (G_00B848_MEM_ORDERED(Header.compute_pgm_resource_registers) &&	0
5354	!isGFX10Plus())	0	5354	!isGFX10Plus())	0
5355	return TokError("enable_mem_ordered=1 is only allowed on GFX10+");	0	5355	return TokError("enable_mem_ordered=1 is only allowed on GFX10+");	0
5356	}	---	5356	}	---
5357		---	5357		---
5358	if (ID == "enable_fwd_progress") {	0	5358	if (ID == "enable_fwd_progress") {	0
5359	if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) &&	0	5359	if (G_00B848_FWD_PROGRESS(Header.compute_pgm_resource_registers) &&	0
5360	!isGFX10Plus())	0	5360	!isGFX10Plus())	0
5361	return TokError("enable_fwd_progress=1 is only allowed on GFX10+");	0	5361	return TokError("enable_fwd_progress=1 is only allowed on GFX10+");	0
5362	}	---	5362	}	---
5363		---	5363		---
5364	return false;	0	5364	return false;	0
5365	}	0	5365	}	0
5366		---	5366		---
5367	bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {	0	5367	bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {	0
5368	amd_kernel_code_t Header;	---	5368	amd_kernel_code_t Header;	---
5369	AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());	0	5369	AMDGPU::initDefaultAMDKernelCodeT(Header, &getSTI());	0
5370		---	5370		---
5371	while (true) {	---	5371	while (true) {	---
5372	// Lex EndOfStatement. This is in a while loop, because lexing a comment	---	5372	// Lex EndOfStatement. This is in a while loop, because lexing a comment	---
5373	// will set the current token to EndOfStatement.	---	5373	// will set the current token to EndOfStatement.	---
5374	while(trySkipToken(AsmToken::EndOfStatement));	0	5374	while(trySkipToken(AsmToken::EndOfStatement));	0
5375		---	5375		---
5376	StringRef ID;	0	5376	StringRef ID;	0
5377	if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))	0	5377	if (!parseId(ID, "expected value identifier or .end_amd_kernel_code_t"))	0
5378	return true;	0	5378	return true;	0
5379		---	5379		---
5380	if (ID == ".end_amd_kernel_code_t")	0	5380	if (ID == ".end_amd_kernel_code_t")	0
5381	break;	0	5381	break;	0
5382		---	5382		---
5383	if (ParseAMDKernelCodeTValue(ID, Header))	0	5383	if (ParseAMDKernelCodeTValue(ID, Header))	0
5384	return true;	0	5384	return true;	0
5385	}	0	5385	}	0
5386		---	5386		---
5387	getTargetStreamer().EmitAMDKernelCodeT(Header);	0	5387	getTargetStreamer().EmitAMDKernelCodeT(Header);	0
5388		---	5388		---
5389	return false;	0	5389	return false;	0
5390	}	---	5390	}	---
5391		---	5391		---
5392	bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {	0	5392	bool AMDGPUAsmParser::ParseDirectiveAMDGPUHsaKernel() {	0
5393	StringRef KernelName;	0	5393	StringRef KernelName;	0
5394	if (!parseId(KernelName, "expected symbol name"))	0	5394	if (!parseId(KernelName, "expected symbol name"))	0
5395	return true;	0	5395	return true;	0
5396		---	5396		---
5397	getTargetStreamer().EmitAMDGPUSymbolType(KernelName,	0	5397	getTargetStreamer().EmitAMDGPUSymbolType(KernelName,	0
5398	ELF::STT_AMDGPU_HSA_KERNEL);	---	5398	ELF::STT_AMDGPU_HSA_KERNEL);	---
5399		---	5399		---
5400	KernelScope.initialize(getContext());	0	5400	KernelScope.initialize(getContext());	0
5401	return false;	0	5401	return false;	0
5402	}	---	5402	}	---
5403		---	5403		---
5404	bool AMDGPUAsmParser::ParseDirectiveISAVersion() {	0	5404	bool AMDGPUAsmParser::ParseDirectiveISAVersion() {	0
5405	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {	0	5405	if (getSTI().getTargetTriple().getArch() != Triple::amdgcn) {	0
5406	return Error(getLoc(),	0	5406	return Error(getLoc(),	0
5407	".amd_amdgpu_isa directive is not available on non-amdgcn "	---	5407	".amd_amdgpu_isa directive is not available on non-amdgcn "	---
5408	"architectures");	0	5408	"architectures");	0
5409	}	---	5409	}	---
5410		---	5410		---
5411	auto TargetIDDirective = getLexer().getTok().getStringContents();	0	5411	auto TargetIDDirective = getLexer().getTok().getStringContents();	0
5412	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	0	5412	if (getTargetStreamer().getTargetID()->toString() != TargetIDDirective)	0
5413	return Error(getParser().getTok().getLoc(), "target id must match options");	0	5413	return Error(getParser().getTok().getLoc(), "target id must match options");	0
5414		---	5414		---
5415	getTargetStreamer().EmitISAVersion();	0	5415	getTargetStreamer().EmitISAVersion();	0
5416	Lex();	0	5416	Lex();	0
5417		---	5417		---
5418	return false;	0	5418	return false;	0
5419	}	---	5419	}	---
5420		---	5420		---
5421	bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {	0	5421	bool AMDGPUAsmParser::ParseDirectiveHSAMetadata() {	0
5422	const char *AssemblerDirectiveBegin;	---	5422	const char *AssemblerDirectiveBegin;	---
5423	const char *AssemblerDirectiveEnd;	---	5423	const char *AssemblerDirectiveEnd;	---
5424	std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =	0	5424	std::tie(AssemblerDirectiveBegin, AssemblerDirectiveEnd) =	0
5425	isHsaAbiVersion3AndAbove(&getSTI())	0	5425	isHsaAbiVersion3AndAbove(&getSTI())	0
5426	? std::pair(HSAMD::V3::AssemblerDirectiveBegin,	0	5426	? std::pair(HSAMD::V3::AssemblerDirectiveBegin,	0
5427	HSAMD::V3::AssemblerDirectiveEnd)	0	5427	HSAMD::V3::AssemblerDirectiveEnd)	0
5428	: std::pair(HSAMD::AssemblerDirectiveBegin,	0	5428	: std::pair(HSAMD::AssemblerDirectiveBegin,	0
5429	HSAMD::AssemblerDirectiveEnd);	0	5429	HSAMD::AssemblerDirectiveEnd);	0
5430		---	5430		---
5431	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {	0	5431	if (getSTI().getTargetTriple().getOS() != Triple::AMDHSA) {	0
5432	return Error(getLoc(),	0	5432	return Error(getLoc(),	0
5433	(Twine(AssemblerDirectiveBegin) + Twine(" directive is "	0	5433	(Twine(AssemblerDirectiveBegin) + Twine(" directive is "	0
5434	"not available on non-amdhsa OSes")).str());	0	5434	"not available on non-amdhsa OSes")).str());	0
5435	}	---	5435	}	---
5436		---	5436		---
5437	std::string HSAMetadataString;	0	5437	std::string HSAMetadataString;	0
5438	if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,	0	5438	if (ParseToEndDirective(AssemblerDirectiveBegin, AssemblerDirectiveEnd,	0
5439	HSAMetadataString))	---	5439	HSAMetadataString))	---
5440	return true;	0	5440	return true;	0
5441		---	5441		---
5442	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0	5442	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0
5443	if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))	0	5443	if (!getTargetStreamer().EmitHSAMetadataV3(HSAMetadataString))	0
5444	return Error(getLoc(), "invalid HSA metadata");	0	5444	return Error(getLoc(), "invalid HSA metadata");	0
5445	} else {	---	5445	} else {	---
5446	if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))	0	5446	if (!getTargetStreamer().EmitHSAMetadataV2(HSAMetadataString))	0
5447	return Error(getLoc(), "invalid HSA metadata");	0	5447	return Error(getLoc(), "invalid HSA metadata");	0
5448	}	---	5448	}	---
5449		---	5449		---
5450	return false;	0	5450	return false;	0
5451	}	0	5451	}	0
5452		---	5452		---
5453	/// Common code to parse out a block of text (typically YAML) between start and	---	5453	/// Common code to parse out a block of text (typically YAML) between start and	---
5454	/// end directives.	---	5454	/// end directives.	---
5455	bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,	0	5455	bool AMDGPUAsmParser::ParseToEndDirective(const char *AssemblerDirectiveBegin,	0
5456	const char *AssemblerDirectiveEnd,	---	5456	const char *AssemblerDirectiveEnd,	---
5457	std::string &CollectString) {	---	5457	std::string &CollectString) {	---
5458		---	5458		---
5459	raw_string_ostream CollectStream(CollectString);	0	5459	raw_string_ostream CollectStream(CollectString);	0
5460		---	5460		---
5461	getLexer().setSkipSpace(false);	0	5461	getLexer().setSkipSpace(false);	0
5462		---	5462		---
5463	bool FoundEnd = false;	0	5463	bool FoundEnd = false;	0
5464	while (!isToken(AsmToken::Eof)) {	0	5464	while (!isToken(AsmToken::Eof)) {	0
5465	while (isToken(AsmToken::Space)) {	0	5465	while (isToken(AsmToken::Space)) {	0
5466	CollectStream << getTokenStr();	0	5466	CollectStream << getTokenStr();	0
5467	Lex();	0	5467	Lex();	0
5468	}	---	5468	}	---
5469		---	5469		---
5470	if (trySkipId(AssemblerDirectiveEnd)) {	0	5470	if (trySkipId(AssemblerDirectiveEnd)) {	0
5471	FoundEnd = true;	0	5471	FoundEnd = true;	0
5472	break;	0	5472	break;	0
5473	}	---	5473	}	---
5474		---	5474		---
5475	CollectStream << Parser.parseStringToEndOfStatement()	0	5475	CollectStream << Parser.parseStringToEndOfStatement()	0
5476	<< getContext().getAsmInfo()->getSeparatorString();	0	5476	<< getContext().getAsmInfo()->getSeparatorString();	0
5477		---	5477		---
5478	Parser.eatToEndOfStatement();	0	5478	Parser.eatToEndOfStatement();	0
5479	}	---	5479	}	---
5480		---	5480		---
5481	getLexer().setSkipSpace(true);	0	5481	getLexer().setSkipSpace(true);	0
5482		---	5482		---
5483	if (isToken(AsmToken::Eof) && !FoundEnd) {	0	5483	if (isToken(AsmToken::Eof) && !FoundEnd) {	0
5484	return TokError(Twine("expected directive ") +	0	5484	return TokError(Twine("expected directive ") +	0
5485	Twine(AssemblerDirectiveEnd) + Twine(" not found"));	0	5485	Twine(AssemblerDirectiveEnd) + Twine(" not found"));	0
5486	}	---	5486	}	---
5487		---	5487		---
5488	CollectStream.flush();	0	5488	CollectStream.flush();	0
5489	return false;	0	5489	return false;	0
5490	}	0	5490	}	0
5491		---	5491		---
5492	/// Parse the assembler directive for new MsgPack-format PAL metadata.	---	5492	/// Parse the assembler directive for new MsgPack-format PAL metadata.	---
5493	bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {	0	5493	bool AMDGPUAsmParser::ParseDirectivePALMetadataBegin() {	0
5494	std::string String;	0	5494	std::string String;	0
5495	if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin,	0	5495	if (ParseToEndDirective(AMDGPU::PALMD::AssemblerDirectiveBegin,	0
5496	AMDGPU::PALMD::AssemblerDirectiveEnd, String))	---	5496	AMDGPU::PALMD::AssemblerDirectiveEnd, String))	---
5497	return true;	0	5497	return true;	0
5498		---	5498		---
5499	auto PALMetadata = getTargetStreamer().getPALMetadata();	0	5499	auto PALMetadata = getTargetStreamer().getPALMetadata();	0
5500	if (!PALMetadata->setFromString(String))	0	5500	if (!PALMetadata->setFromString(String))	0
5501	return Error(getLoc(), "invalid PAL metadata");	0	5501	return Error(getLoc(), "invalid PAL metadata");	0
5502	return false;	0	5502	return false;	0
5503	}	0	5503	}	0
5504		---	5504		---
5505	/// Parse the assembler directive for old linear-format PAL metadata.	---	5505	/// Parse the assembler directive for old linear-format PAL metadata.	---
5506	bool AMDGPUAsmParser::ParseDirectivePALMetadata() {	0	5506	bool AMDGPUAsmParser::ParseDirectivePALMetadata() {	0
5507	if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {	0	5507	if (getSTI().getTargetTriple().getOS() != Triple::AMDPAL) {	0
5508	return Error(getLoc(),	0	5508	return Error(getLoc(),	0
5509	(Twine(PALMD::AssemblerDirective) + Twine(" directive is "	0	5509	(Twine(PALMD::AssemblerDirective) + Twine(" directive is "	0
5510	"not available on non-amdpal OSes")).str());	0	5510	"not available on non-amdpal OSes")).str());	0
5511	}	---	5511	}	---
5512		---	5512		---
5513	auto PALMetadata = getTargetStreamer().getPALMetadata();	0	5513	auto PALMetadata = getTargetStreamer().getPALMetadata();	0
5514	PALMetadata->setLegacy();	0	5514	PALMetadata->setLegacy();	0
5515	for (;;) {	---	5515	for (;;) {	---
5516	uint32_t Key, Value;	---	5516	uint32_t Key, Value;	---
5517	if (ParseAsAbsoluteExpression(Key)) {	0	5517	if (ParseAsAbsoluteExpression(Key)) {	0
5518	return TokError(Twine("invalid value in ") +	0	5518	return TokError(Twine("invalid value in ") +	0
5519	Twine(PALMD::AssemblerDirective));	0	5519	Twine(PALMD::AssemblerDirective));	0
5520	}	---	5520	}	---
5521	if (!trySkipToken(AsmToken::Comma)) {	0	5521	if (!trySkipToken(AsmToken::Comma)) {	0
5522	return TokError(Twine("expected an even number of values in ") +	0	5522	return TokError(Twine("expected an even number of values in ") +	0
5523	Twine(PALMD::AssemblerDirective));	0	5523	Twine(PALMD::AssemblerDirective));	0
5524	}	---	5524	}	---
5525	if (ParseAsAbsoluteExpression(Value)) {	0	5525	if (ParseAsAbsoluteExpression(Value)) {	0
5526	return TokError(Twine("invalid value in ") +	0	5526	return TokError(Twine("invalid value in ") +	0
5527	Twine(PALMD::AssemblerDirective));	0	5527	Twine(PALMD::AssemblerDirective));	0
5528	}	---	5528	}	---
5529	PALMetadata->setRegister(Key, Value);	0	5529	PALMetadata->setRegister(Key, Value);	0
5530	if (!trySkipToken(AsmToken::Comma))	0	5530	if (!trySkipToken(AsmToken::Comma))	0
5531	break;	0	5531	break;	0
5532	}	0	5532	}	0
5533	return false;	0	5533	return false;	0
5534	}	---	5534	}	---
5535		---	5535		---
5536	/// ParseDirectiveAMDGPULDS	---	5536	/// ParseDirectiveAMDGPULDS	---
5537	/// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression]	---	5537	/// ::= .amdgpu_lds identifier ',' size_expression [',' align_expression]	---
5538	bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {	0	5538	bool AMDGPUAsmParser::ParseDirectiveAMDGPULDS() {	0
5539	if (getParser().checkForValidSection())	0	5539	if (getParser().checkForValidSection())	0
5540	return true;	0	5540	return true;	0
5541		---	5541		---
5542	StringRef Name;	0	5542	StringRef Name;	0
5543	SMLoc NameLoc = getLoc();	0	5543	SMLoc NameLoc = getLoc();	0
5544	if (getParser().parseIdentifier(Name))	0	5544	if (getParser().parseIdentifier(Name))	0
5545	return TokError("expected identifier in directive");	0	5545	return TokError("expected identifier in directive");	0
5546		---	5546		---
5547	MCSymbol *Symbol = getContext().getOrCreateSymbol(Name);	0	5547	MCSymbol *Symbol = getContext().getOrCreateSymbol(Name);	0
5548	if (getParser().parseComma())	0	5548	if (getParser().parseComma())	0
5549	return true;	0	5549	return true;	0
5550		---	5550		---
5551	unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());	0	5551	unsigned LocalMemorySize = AMDGPU::IsaInfo::getLocalMemorySize(&getSTI());	0
5552		---	5552		---
5553	int64_t Size;	---	5553	int64_t Size;	---
5554	SMLoc SizeLoc = getLoc();	0	5554	SMLoc SizeLoc = getLoc();	0
5555	if (getParser().parseAbsoluteExpression(Size))	0	5555	if (getParser().parseAbsoluteExpression(Size))	0
5556	return true;	0	5556	return true;	0
5557	if (Size < 0)	0	5557	if (Size < 0)	0
5558	return Error(SizeLoc, "size must be non-negative");	0	5558	return Error(SizeLoc, "size must be non-negative");	0
5559	if (Size > LocalMemorySize)	0	5559	if (Size > LocalMemorySize)	0
5560	return Error(SizeLoc, "size is too large");	0	5560	return Error(SizeLoc, "size is too large");	0
5561		---	5561		---
5562	int64_t Alignment = 4;	0	5562	int64_t Alignment = 4;	0
5563	if (trySkipToken(AsmToken::Comma)) {	0	5563	if (trySkipToken(AsmToken::Comma)) {	0
5564	SMLoc AlignLoc = getLoc();	0	5564	SMLoc AlignLoc = getLoc();	0
5565	if (getParser().parseAbsoluteExpression(Alignment))	0	5565	if (getParser().parseAbsoluteExpression(Alignment))	0
5566	return true;	0	5566	return true;	0
5567	if (Alignment < 0 \|\| !isPowerOf2_64(Alignment))	0	5567	if (Alignment < 0 \|\| !isPowerOf2_64(Alignment))	0
5568	return Error(AlignLoc, "alignment must be a power of two");	0	5568	return Error(AlignLoc, "alignment must be a power of two");	0
5569		---	5569		---
5570	// Alignment larger than the size of LDS is possible in theory, as long	---	5570	// Alignment larger than the size of LDS is possible in theory, as long	---
5571	// as the linker manages to place to symbol at address 0, but we do want	---	5571	// as the linker manages to place to symbol at address 0, but we do want	---
5572	// to make sure the alignment fits nicely into a 32-bit integer.	---	5572	// to make sure the alignment fits nicely into a 32-bit integer.	---
5573	if (Alignment >= 1u << 31)	0	5573	if (Alignment >= 1u << 31)	0
5574	return Error(AlignLoc, "alignment is too large");	0	5574	return Error(AlignLoc, "alignment is too large");	0
5575	}	---	5575	}	---
5576		---	5576		---
5577	if (parseEOL())	0	5577	if (parseEOL())	0
5578	return true;	0	5578	return true;	0
5579		---	5579		---
5580	Symbol->redefineIfPossible();	0	5580	Symbol->redefineIfPossible();	0
5581	if (!Symbol->isUndefined())	0	5581	if (!Symbol->isUndefined())	0
5582	return Error(NameLoc, "invalid symbol redefinition");	0	5582	return Error(NameLoc, "invalid symbol redefinition");	0
5583		---	5583		---
5584	getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));	0	5584	getTargetStreamer().emitAMDGPULDS(Symbol, Size, Align(Alignment));	0
5585	return false;	0	5585	return false;	0
5586	}	---	5586	}	---
5587		---	5587		---
5588	bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {	0	5588	bool AMDGPUAsmParser::ParseDirective(AsmToken DirectiveID) {	0
5589	StringRef IDVal = DirectiveID.getString();	0	5589	StringRef IDVal = DirectiveID.getString();	0
5590		---	5590		---
5591	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0	5591	if (isHsaAbiVersion3AndAbove(&getSTI())) {	0
5592	if (IDVal == ".amdhsa_kernel")	0	5592	if (IDVal == ".amdhsa_kernel")	0
5593	return ParseDirectiveAMDHSAKernel();	0	5593	return ParseDirectiveAMDHSAKernel();	0
5594		---	5594		---
5595	// TODO: Restructure/combine with PAL metadata directive.	---	5595	// TODO: Restructure/combine with PAL metadata directive.	---
5596	if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)	0	5596	if (IDVal == AMDGPU::HSAMD::V3::AssemblerDirectiveBegin)	0
5597	return ParseDirectiveHSAMetadata();	0	5597	return ParseDirectiveHSAMetadata();	0
5598	} else {	---	5598	} else {	---
5599	if (IDVal == ".hsa_code_object_version")	0	5599	if (IDVal == ".hsa_code_object_version")	0
5600	return ParseDirectiveHSACodeObjectVersion();	0	5600	return ParseDirectiveHSACodeObjectVersion();	0
5601		---	5601		---
5602	if (IDVal == ".hsa_code_object_isa")	0	5602	if (IDVal == ".hsa_code_object_isa")	0
5603	return ParseDirectiveHSACodeObjectISA();	0	5603	return ParseDirectiveHSACodeObjectISA();	0
5604		---	5604		---
5605	if (IDVal == ".amd_kernel_code_t")	0	5605	if (IDVal == ".amd_kernel_code_t")	0
5606	return ParseDirectiveAMDKernelCodeT();	0	5606	return ParseDirectiveAMDKernelCodeT();	0
5607		---	5607		---
5608	if (IDVal == ".amdgpu_hsa_kernel")	0	5608	if (IDVal == ".amdgpu_hsa_kernel")	0
5609	return ParseDirectiveAMDGPUHsaKernel();	0	5609	return ParseDirectiveAMDGPUHsaKernel();	0
5610		---	5610		---
5611	if (IDVal == ".amd_amdgpu_isa")	0	5611	if (IDVal == ".amd_amdgpu_isa")	0
5612	return ParseDirectiveISAVersion();	0	5612	return ParseDirectiveISAVersion();	0
5613		---	5613		---
5614	if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)	0	5614	if (IDVal == AMDGPU::HSAMD::AssemblerDirectiveBegin)	0
5615	return ParseDirectiveHSAMetadata();	0	5615	return ParseDirectiveHSAMetadata();	0
5616	}	---	5616	}	---
5617		---	5617		---
5618	if (IDVal == ".amdgcn_target")	0	5618	if (IDVal == ".amdgcn_target")	0
5619	return ParseDirectiveAMDGCNTarget();	0	5619	return ParseDirectiveAMDGCNTarget();	0
5620		---	5620		---
5621	if (IDVal == ".amdgpu_lds")	0	5621	if (IDVal == ".amdgpu_lds")	0
5622	return ParseDirectiveAMDGPULDS();	0	5622	return ParseDirectiveAMDGPULDS();	0
5623		---	5623		---
5624	if (IDVal == PALMD::AssemblerDirectiveBegin)	0	5624	if (IDVal == PALMD::AssemblerDirectiveBegin)	0
5625	return ParseDirectivePALMetadataBegin();	0	5625	return ParseDirectivePALMetadataBegin();	0
5626		---	5626		---
5627	if (IDVal == PALMD::AssemblerDirective)	0	5627	if (IDVal == PALMD::AssemblerDirective)	0
5628	return ParseDirectivePALMetadata();	0	5628	return ParseDirectivePALMetadata();	0
5629		---	5629		---
5630	return true;	0	5630	return true;	0
5631	}	---	5631	}	---
5632		---	5632		---
5633	bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,	0	5633	bool AMDGPUAsmParser::subtargetHasRegister(const MCRegisterInfo &MRI,	0
5634	unsigned RegNo) {	---	5634	unsigned RegNo) {	---
5635		---	5635		---
5636	if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))	0	5636	if (MRI.regsOverlap(AMDGPU::TTMP12_TTMP13_TTMP14_TTMP15, RegNo))	0
5637	return isGFX9Plus();	0	5637	return isGFX9Plus();	0
5638		---	5638		---
5639	// GFX10+ has 2 more SGPRs 104 and 105.	---	5639	// GFX10+ has 2 more SGPRs 104 and 105.	---
5640	if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))	0	5640	if (MRI.regsOverlap(AMDGPU::SGPR104_SGPR105, RegNo))	0
5641	return hasSGPR104_SGPR105();	0	5641	return hasSGPR104_SGPR105();	0
5642		---	5642		---
5643	switch (RegNo) {	0	5643	switch (RegNo) {	0
5644	case AMDGPU::SRC_SHARED_BASE_LO:	0	5644	case AMDGPU::SRC_SHARED_BASE_LO:	0
5645	case AMDGPU::SRC_SHARED_BASE:	---	5645	case AMDGPU::SRC_SHARED_BASE:	---
5646	case AMDGPU::SRC_SHARED_LIMIT_LO:	---	5646	case AMDGPU::SRC_SHARED_LIMIT_LO:	---
5647	case AMDGPU::SRC_SHARED_LIMIT:	---	5647	case AMDGPU::SRC_SHARED_LIMIT:	---
5648	case AMDGPU::SRC_PRIVATE_BASE_LO:	---	5648	case AMDGPU::SRC_PRIVATE_BASE_LO:	---
5649	case AMDGPU::SRC_PRIVATE_BASE:	---	5649	case AMDGPU::SRC_PRIVATE_BASE:	---
5650	case AMDGPU::SRC_PRIVATE_LIMIT_LO:	---	5650	case AMDGPU::SRC_PRIVATE_LIMIT_LO:	---
5651	case AMDGPU::SRC_PRIVATE_LIMIT:	---	5651	case AMDGPU::SRC_PRIVATE_LIMIT:	---
5652	return isGFX9Plus();	0	5652	return isGFX9Plus();	0
5653	case AMDGPU::SRC_POPS_EXITING_WAVE_ID:	0	5653	case AMDGPU::SRC_POPS_EXITING_WAVE_ID:	0
5654	return isGFX9Plus() && !isGFX11Plus();	0	5654	return isGFX9Plus() && !isGFX11Plus();	0
5655	case AMDGPU::TBA:	0	5655	case AMDGPU::TBA:	0
5656	case AMDGPU::TBA_LO:	---	5656	case AMDGPU::TBA_LO:	---
5657	case AMDGPU::TBA_HI:	---	5657	case AMDGPU::TBA_HI:	---
5658	case AMDGPU::TMA:	---	5658	case AMDGPU::TMA:	---
5659	case AMDGPU::TMA_LO:	---	5659	case AMDGPU::TMA_LO:	---
5660	case AMDGPU::TMA_HI:	---	5660	case AMDGPU::TMA_HI:	---
5661	return !isGFX9Plus();	0	5661	return !isGFX9Plus();	0
5662	case AMDGPU::XNACK_MASK:	0	5662	case AMDGPU::XNACK_MASK:	0
5663	case AMDGPU::XNACK_MASK_LO:	---	5663	case AMDGPU::XNACK_MASK_LO:	---
5664	case AMDGPU::XNACK_MASK_HI:	---	5664	case AMDGPU::XNACK_MASK_HI:	---
5665	return (isVI() \|\| isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();	0	5665	return (isVI() \|\| isGFX9()) && getTargetStreamer().getTargetID()->isXnackSupported();	0
5666	case AMDGPU::SGPR_NULL:	0	5666	case AMDGPU::SGPR_NULL:	0
5667	return isGFX10Plus();	0	5667	return isGFX10Plus();	0
5668	default:	0	5668	default:	0
5669	break;	0	5669	break;	0
5670	}	---	5670	}	---
5671		---	5671		---
5672	if (isCI())	0	5672	if (isCI())	0
5673	return true;	0	5673	return true;	0
5674		---	5674		---
5675	if (isSI() \|\| isGFX10Plus()) {	0	5675	if (isSI() \|\| isGFX10Plus()) {	0
5676	// No flat_scr on SI.	---	5676	// No flat_scr on SI.	---
5677	// On GFX10Plus flat scratch is not a valid register operand and can only be	---	5677	// On GFX10Plus flat scratch is not a valid register operand and can only be	---
5678	// accessed with s_setreg/s_getreg.	---	5678	// accessed with s_setreg/s_getreg.	---
5679	switch (RegNo) {	0	5679	switch (RegNo) {	0
5680	case AMDGPU::FLAT_SCR:	0	5680	case AMDGPU::FLAT_SCR:	0
5681	case AMDGPU::FLAT_SCR_LO:	---	5681	case AMDGPU::FLAT_SCR_LO:	---
5682	case AMDGPU::FLAT_SCR_HI:	---	5682	case AMDGPU::FLAT_SCR_HI:	---
5683	return false;	0	5683	return false;	0
5684	default:	0	5684	default:	0
5685	return true;	0	5685	return true;	0
5686	}	---	5686	}	---
5687	}	---	5687	}	---
5688		---	5688		---
5689	// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that	---	5689	// VI only has 102 SGPRs, so make sure we aren't trying to use the 2 more that	---
5690	// SI/CI have.	---	5690	// SI/CI have.	---
5691	if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))	0	5691	if (MRI.regsOverlap(AMDGPU::SGPR102_SGPR103, RegNo))	0
5692	return hasSGPR102_SGPR103();	0	5692	return hasSGPR102_SGPR103();	0
5693		---	5693		---
5694	return true;	0	5694	return true;	0
5695	}	---	5695	}	---
5696		---	5696		---
5697	ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,	0	5697	ParseStatus AMDGPUAsmParser::parseOperand(OperandVector &Operands,	0
5698	StringRef Mnemonic,	---	5698	StringRef Mnemonic,	---
5699	OperandMode Mode) {	---	5699	OperandMode Mode) {	---
5700	ParseStatus Res = parseVOPD(Operands);	0	5700	ParseStatus Res = parseVOPD(Operands);	0
5701	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	0	5701	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	0
5702	return Res;	0	5702	return Res;	0
5703		---	5703		---
5704	// Try to parse with a custom parser	---	5704	// Try to parse with a custom parser	---
5705	Res = MatchOperandParserImpl(Operands, Mnemonic);	0	5705	Res = MatchOperandParserImpl(Operands, Mnemonic);	0
5706		---	5706		---
5707	// If we successfully parsed the operand or if there as an error parsing,	---	5707	// If we successfully parsed the operand or if there as an error parsing,	---
5708	// we are done.	---	5708	// we are done.	---
5709	//	---	5709	//	---
5710	// If we are parsing after we reach EndOfStatement then this means we	---	5710	// If we are parsing after we reach EndOfStatement then this means we	---
5711	// are appending default values to the Operands list. This is only done	---	5711	// are appending default values to the Operands list. This is only done	---
5712	// by custom parser, so we shouldn't continue on to the generic parsing.	---	5712	// by custom parser, so we shouldn't continue on to the generic parsing.	---
5713	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	0	5713	if (Res.isSuccess() \|\| Res.isFailure() \|\| isToken(AsmToken::EndOfStatement))	0
5714	return Res;	0	5714	return Res;	0
5715		---	5715		---
5716	SMLoc RBraceLoc;	0	5716	SMLoc RBraceLoc;	0
5717	SMLoc LBraceLoc = getLoc();	0	5717	SMLoc LBraceLoc = getLoc();	0
5718	if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {	0	5718	if (Mode == OperandMode_NSA && trySkipToken(AsmToken::LBrac)) {	0
5719	unsigned Prefix = Operands.size();	0	5719	unsigned Prefix = Operands.size();	0
5720		---	5720		---
5721	for (;;) {	---	5721	for (;;) {	---
5722	auto Loc = getLoc();	0	5722	auto Loc = getLoc();	0
5723	Res = parseReg(Operands);	0	5723	Res = parseReg(Operands);	0
5724	if (Res.isNoMatch())	0	5724	if (Res.isNoMatch())	0
5725	Error(Loc, "expected a register");	0	5725	Error(Loc, "expected a register");	0
5726	if (!Res.isSuccess())	0	5726	if (!Res.isSuccess())	0
5727	return ParseStatus::Failure;	0	5727	return ParseStatus::Failure;	0
5728		---	5728		---
5729	RBraceLoc = getLoc();	0	5729	RBraceLoc = getLoc();	0
5730	if (trySkipToken(AsmToken::RBrac))	0	5730	if (trySkipToken(AsmToken::RBrac))	0
5731	break;	0	5731	break;	0
5732		---	5732		---
5733	if (!skipToken(AsmToken::Comma,	0	5733	if (!skipToken(AsmToken::Comma,	0
5734	"expected a comma or a closing square bracket"))	---	5734	"expected a comma or a closing square bracket"))	---
5735	return ParseStatus::Failure;	0	5735	return ParseStatus::Failure;	0
5736	}	0	5736	}	0
5737		---	5737		---
5738	if (Operands.size() - Prefix > 1) {	0	5738	if (Operands.size() - Prefix > 1) {	0
5739	Operands.insert(Operands.begin() + Prefix,	0	5739	Operands.insert(Operands.begin() + Prefix,	0
5740	AMDGPUOperand::CreateToken(this, "[", LBraceLoc));	0	5740	AMDGPUOperand::CreateToken(this, "[", LBraceLoc));	0
5741	Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));	0	5741	Operands.push_back(AMDGPUOperand::CreateToken(this, "]", RBraceLoc));	0
5742	}	---	5742	}	---
5743		---	5743		---
5744	return ParseStatus::Success;	0	5744	return ParseStatus::Success;	0
5745	}	---	5745	}	---
5746		---	5746		---
5747	return parseRegOrImm(Operands);	0	5747	return parseRegOrImm(Operands);	0
5748	}	---	5748	}	---
5749		---	5749		---
5750	StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {	0	5750	StringRef AMDGPUAsmParser::parseMnemonicSuffix(StringRef Name) {	0
5751	// Clear any forced encodings from the previous instruction.	---	5751	// Clear any forced encodings from the previous instruction.	---
5752	setForcedEncodingSize(0);	0	5752	setForcedEncodingSize(0);	0
5753	setForcedDPP(false);	0	5753	setForcedDPP(false);	0
5754	setForcedSDWA(false);	0	5754	setForcedSDWA(false);	0
5755		---	5755		---
5756	if (Name.endswith("_e64_dpp")) {	0	5756	if (Name.endswith("_e64_dpp")) {	0
5757	setForcedDPP(true);	0	5757	setForcedDPP(true);	0
5758	setForcedEncodingSize(64);	0	5758	setForcedEncodingSize(64);	0
5759	return Name.substr(0, Name.size() - 8);	0	5759	return Name.substr(0, Name.size() - 8);	0
5760	} else if (Name.endswith("_e64")) {	0	5760	} else if (Name.endswith("_e64")) {	0
5761	setForcedEncodingSize(64);	0	5761	setForcedEncodingSize(64);	0
5762	return Name.substr(0, Name.size() - 4);	0	5762	return Name.substr(0, Name.size() - 4);	0
5763	} else if (Name.endswith("_e32")) {	0	5763	} else if (Name.endswith("_e32")) {	0
5764	setForcedEncodingSize(32);	0	5764	setForcedEncodingSize(32);	0
5765	return Name.substr(0, Name.size() - 4);	0	5765	return Name.substr(0, Name.size() - 4);	0
5766	} else if (Name.endswith("_dpp")) {	0	5766	} else if (Name.endswith("_dpp")) {	0
5767	setForcedDPP(true);	0	5767	setForcedDPP(true);	0
5768	return Name.substr(0, Name.size() - 4);	0	5768	return Name.substr(0, Name.size() - 4);	0
5769	} else if (Name.endswith("_sdwa")) {	0	5769	} else if (Name.endswith("_sdwa")) {	0
5770	setForcedSDWA(true);	0	5770	setForcedSDWA(true);	0
5771	return Name.substr(0, Name.size() - 5);	0	5771	return Name.substr(0, Name.size() - 5);	0
5772	}	---	5772	}	---
5773	return Name;	0	5773	return Name;	0
5774	}	---	5774	}	---
5775		---	5775		---
5776	static void applyMnemonicAliases(StringRef &Mnemonic,	---	5776	static void applyMnemonicAliases(StringRef &Mnemonic,	---
5777	const FeatureBitset &Features,	---	5777	const FeatureBitset &Features,	---
5778	unsigned VariantID);	---	5778	unsigned VariantID);	---
5779		---	5779		---
5780	bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,	0	5780	bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,	0
5781	StringRef Name,	---	5781	StringRef Name,	---
5782	SMLoc NameLoc, OperandVector &Operands) {	---	5782	SMLoc NameLoc, OperandVector &Operands) {	---
5783	// Add the instruction mnemonic	---	5783	// Add the instruction mnemonic	---
5784	Name = parseMnemonicSuffix(Name);	0	5784	Name = parseMnemonicSuffix(Name);	0
5785		---	5785		---
5786	// If the target architecture uses MnemonicAlias, call it here to parse	---	5786	// If the target architecture uses MnemonicAlias, call it here to parse	---
5787	// operands correctly.	---	5787	// operands correctly.	---
5788	applyMnemonicAliases(Name, getAvailableFeatures(), 0);	0	5788	applyMnemonicAliases(Name, getAvailableFeatures(), 0);	0
5789		---	5789		---
5790	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));	0	5790	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc));	0
5791		---	5791		---
5792	bool IsMIMG = Name.startswith("image_");	0	5792	bool IsMIMG = Name.startswith("image_");	0
5793		---	5793		---
5794	while (!trySkipToken(AsmToken::EndOfStatement)) {	0	5794	while (!trySkipToken(AsmToken::EndOfStatement)) {	0
5795	OperandMode Mode = OperandMode_Default;	0	5795	OperandMode Mode = OperandMode_Default;	0
5796	if (IsMIMG && isGFX10Plus() && Operands.size() == 2)	0	5796	if (IsMIMG && isGFX10Plus() && Operands.size() == 2)	0
5797	Mode = OperandMode_NSA;	0	5797	Mode = OperandMode_NSA;	0
5798	ParseStatus Res = parseOperand(Operands, Name, Mode);	0	5798	ParseStatus Res = parseOperand(Operands, Name, Mode);	0
5799		---	5799		---
5800	if (!Res.isSuccess()) {	0	5800	if (!Res.isSuccess()) {	0
5801	checkUnsupportedInstruction(Name, NameLoc);	0	5801	checkUnsupportedInstruction(Name, NameLoc);	0
5802	if (!Parser.hasPendingError()) {	0	5802	if (!Parser.hasPendingError()) {	0
5803	// FIXME: use real operand location rather than the current location.	---	5803	// FIXME: use real operand location rather than the current location.	---
5804	StringRef Msg = Res.isFailure() ? "failed parsing operand."	0	5804	StringRef Msg = Res.isFailure() ? "failed parsing operand."	0
5805	: "not a valid operand.";	0	5805	: "not a valid operand.";	0
5806	Error(getLoc(), Msg);	0	5806	Error(getLoc(), Msg);	0
5807	}	---	5807	}	---
5808	while (!trySkipToken(AsmToken::EndOfStatement)) {	0	5808	while (!trySkipToken(AsmToken::EndOfStatement)) {	0
5809	lex();	0	5809	lex();	0
5810	}	---	5810	}	---
5811	return true;	0	5811	return true;	0
5812	}	---	5812	}	---
5813		---	5813		---
5814	// Eat the comma or space if there is one.	---	5814	// Eat the comma or space if there is one.	---
5815	trySkipToken(AsmToken::Comma);	0	5815	trySkipToken(AsmToken::Comma);	0
5816	}	---	5816	}	---
5817		---	5817		---
5818	return false;	0	5818	return false;	0
5819	}	---	5819	}	---
5820		---	5820		---
5821	//===----------------------------------------------------------------------===//	---	5821	//===----------------------------------------------------------------------===//	---
5822	// Utility functions	---	5822	// Utility functions	---
5823	//===----------------------------------------------------------------------===//	---	5823	//===----------------------------------------------------------------------===//	---
5824		---	5824		---
5825	ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,	0	5825	ParseStatus AMDGPUAsmParser::parseTokenOp(StringRef Name,	0
5826	OperandVector &Operands) {	---	5826	OperandVector &Operands) {	---
5827	SMLoc S = getLoc();	0	5827	SMLoc S = getLoc();	0
5828	if (!trySkipId(Name))	0	5828	if (!trySkipId(Name))	0
5829	return ParseStatus::NoMatch;	0	5829	return ParseStatus::NoMatch;	0
5830		---	5830		---
5831	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));	0	5831	Operands.push_back(AMDGPUOperand::CreateToken(this, Name, S));	0
5832	return ParseStatus::Success;	0	5832	return ParseStatus::Success;	0
5833	}	---	5833	}	---
5834		---	5834		---
5835	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,	0	5835	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix,	0
5836	int64_t &IntVal) {	---	5836	int64_t &IntVal) {	---
5837		---	5837		---
5838	if (!trySkipId(Prefix, AsmToken::Colon))	0	5838	if (!trySkipId(Prefix, AsmToken::Colon))	0
5839	return ParseStatus::NoMatch;	0	5839	return ParseStatus::NoMatch;	0
5840		---	5840		---
5841	return parseExpr(IntVal) ? ParseStatus::Success : ParseStatus::Failure;	0	5841	return parseExpr(IntVal) ? ParseStatus::Success : ParseStatus::Failure;	0
5842	}	---	5842	}	---
5843		---	5843		---
5844	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(	0	5844	ParseStatus AMDGPUAsmParser::parseIntWithPrefix(	0
5845	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	---	5845	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	---
5846	std::function ConvertResult) {	---	5846	std::function ConvertResult) {	---
5847	SMLoc S = getLoc();	0	5847	SMLoc S = getLoc();	0
5848	int64_t Value = 0;	0	5848	int64_t Value = 0;	0
5849		---	5849		---
5850	ParseStatus Res = parseIntWithPrefix(Prefix, Value);	0	5850	ParseStatus Res = parseIntWithPrefix(Prefix, Value);	0
5851	if (!Res.isSuccess())	0	5851	if (!Res.isSuccess())	0
5852	return Res;	0	5852	return Res;	0
5853		---	5853		---
5854	if (ConvertResult && !ConvertResult(Value)) {	0	5854	if (ConvertResult && !ConvertResult(Value)) {	0
5855	Error(S, "invalid " + StringRef(Prefix) + " value.");	0	5855	Error(S, "invalid " + StringRef(Prefix) + " value.");	0
5856	}	---	5856	}	---
5857		---	5857		---
5858	Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));	0	5858	Operands.push_back(AMDGPUOperand::CreateImm(this, Value, S, ImmTy));	0
5859	return ParseStatus::Success;	0	5859	return ParseStatus::Success;	0
5860	}	---	5860	}	---
5861		---	5861		---
5862	ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(	0	5862	ParseStatus AMDGPUAsmParser::parseOperandArrayWithPrefix(	0
5863	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	---	5863	const char *Prefix, OperandVector &Operands, AMDGPUOperand::ImmTy ImmTy,	---
5864	bool (*ConvertResult)(int64_t &)) {	---	5864	bool (*ConvertResult)(int64_t &)) {	---
5865	SMLoc S = getLoc();	0	5865	SMLoc S = getLoc();	0
5866	if (!trySkipId(Prefix, AsmToken::Colon))	0	5866	if (!trySkipId(Prefix, AsmToken::Colon))	0
5867	return ParseStatus::NoMatch;	0	5867	return ParseStatus::NoMatch;	0
5868		---	5868		---
5869	if (!skipToken(AsmToken::LBrac, "expected a left square bracket"))	0	5869	if (!skipToken(AsmToken::LBrac, "expected a left square bracket"))	0
5870	return ParseStatus::Failure;	0	5870	return ParseStatus::Failure;	0
5871		---	5871		---
5872	unsigned Val = 0;	0	5872	unsigned Val = 0;	0
5873	const unsigned MaxSize = 4;	0	5873	const unsigned MaxSize = 4;	0
5874		---	5874		---
5875	// FIXME: How to verify the number of elements matches the number of src	---	5875	// FIXME: How to verify the number of elements matches the number of src	---
5876	// operands?	---	5876	// operands?	---
5877	for (int I = 0; ; ++I) {	0	5877	for (int I = 0; ; ++I) {	0
5878	int64_t Op;	---	5878	int64_t Op;	---
5879	SMLoc Loc = getLoc();	0	5879	SMLoc Loc = getLoc();	0
5880	if (!parseExpr(Op))	0	5880	if (!parseExpr(Op))	0
5881	return ParseStatus::Failure;	0	5881	return ParseStatus::Failure;	0
5882		---	5882		---
5883	if (Op != 0 && Op != 1)	0	5883	if (Op != 0 && Op != 1)	0
5884	return Error(Loc, "invalid " + StringRef(Prefix) + " value.");	0	5884	return Error(Loc, "invalid " + StringRef(Prefix) + " value.");	0
5885		---	5885		---
5886	Val \|= (Op << I);	0	5886	Val \|= (Op << I);	0
5887		---	5887		---
5888	if (trySkipToken(AsmToken::RBrac))	0	5888	if (trySkipToken(AsmToken::RBrac))	0
5889	break;	0	5889	break;	0
5890		---	5890		---
5891	if (I + 1 == MaxSize)	0	5891	if (I + 1 == MaxSize)	0
5892	return Error(getLoc(), "expected a closing square bracket");	0	5892	return Error(getLoc(), "expected a closing square bracket");	0
5893		---	5893		---
5894	if (!skipToken(AsmToken::Comma, "expected a comma"))	0	5894	if (!skipToken(AsmToken::Comma, "expected a comma"))	0
5895	return ParseStatus::Failure;	0	5895	return ParseStatus::Failure;	0
5896	}	0	5896	}	0
5897		---	5897		---
5898	Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));	0	5898	Operands.push_back(AMDGPUOperand::CreateImm(this, Val, S, ImmTy));	0
5899	return ParseStatus::Success;	0	5899	return ParseStatus::Success;	0
5900	}	---	5900	}	---
5901		---	5901		---
5902	ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,	0	5902	ParseStatus AMDGPUAsmParser::parseNamedBit(StringRef Name,	0
5903	OperandVector &Operands,	---	5903	OperandVector &Operands,	---
5904	AMDGPUOperand::ImmTy ImmTy) {	---	5904	AMDGPUOperand::ImmTy ImmTy) {	---
5905	int64_t Bit;	---	5905	int64_t Bit;	---
5906	SMLoc S = getLoc();	0	5906	SMLoc S = getLoc();	0
5907		---	5907		---
5908	if (trySkipId(Name)) {	0	5908	if (trySkipId(Name)) {	0
5909	Bit = 1;	0	5909	Bit = 1;	0
5910	} else if (trySkipId("no", Name)) {	0	5910	} else if (trySkipId("no", Name)) {	0
5911	Bit = 0;	0	5911	Bit = 0;	0
5912	} else {	---	5912	} else {	---
5913	return ParseStatus::NoMatch;	0	5913	return ParseStatus::NoMatch;	0
5914	}	---	5914	}	---
5915		---	5915		---
5916	if (Name == "r128" && !hasMIMG_R128())	0	5916	if (Name == "r128" && !hasMIMG_R128())	0
5917	return Error(S, "r128 modifier is not supported on this GPU");	0	5917	return Error(S, "r128 modifier is not supported on this GPU");	0
5918	if (Name == "a16" && !hasA16())	0	5918	if (Name == "a16" && !hasA16())	0
5919	return Error(S, "a16 modifier is not supported on this GPU");	0	5919	return Error(S, "a16 modifier is not supported on this GPU");	0
5920		---	5920		---
5921	if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)	0	5921	if (isGFX9() && ImmTy == AMDGPUOperand::ImmTyA16)	0
5922	ImmTy = AMDGPUOperand::ImmTyR128A16;	0	5922	ImmTy = AMDGPUOperand::ImmTyR128A16;	0
5923		---	5923		---
5924	Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));	0	5924	Operands.push_back(AMDGPUOperand::CreateImm(this, Bit, S, ImmTy));	0
5925	return ParseStatus::Success;	0	5925	return ParseStatus::Success;	0
5926	}	---	5926	}	---
5927		---	5927		---
5928	unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,	0	5928	unsigned AMDGPUAsmParser::getCPolKind(StringRef Id, StringRef Mnemo,	0
5929	bool &Disabling) const {	---	5929	bool &Disabling) const {	---
5930	Disabling = Id.consume_front("no");	0	5930	Disabling = Id.consume_front("no");	0
5931		---	5931		---
5932	if (isGFX940() && !Mnemo.startswith("s_")) {	0	5932	if (isGFX940() && !Mnemo.startswith("s_")) {	0
5933	return StringSwitch(Id)	0	5933	return StringSwitch(Id)	0
5934	.Case("nt", AMDGPU::CPol::NT)	0	5934	.Case("nt", AMDGPU::CPol::NT)	0
5935	.Case("sc0", AMDGPU::CPol::SC0)	0	5935	.Case("sc0", AMDGPU::CPol::SC0)	0
5936	.Case("sc1", AMDGPU::CPol::SC1)	0	5936	.Case("sc1", AMDGPU::CPol::SC1)	0
5937	.Default(0);	0	5937	.Default(0);	0
5938	}	---	5938	}	---
5939		---	5939		---
5940	return StringSwitch(Id)	0	5940	return StringSwitch(Id)	0
5941	.Case("dlc", AMDGPU::CPol::DLC)	0	5941	.Case("dlc", AMDGPU::CPol::DLC)	0
5942	.Case("glc", AMDGPU::CPol::GLC)	0	5942	.Case("glc", AMDGPU::CPol::GLC)	0
5943	.Case("scc", AMDGPU::CPol::SCC)	0	5943	.Case("scc", AMDGPU::CPol::SCC)	0
5944	.Case("slc", AMDGPU::CPol::SLC)	0	5944	.Case("slc", AMDGPU::CPol::SLC)	0
5945	.Default(0);	0	5945	.Default(0);	0
5946	}	---	5946	}	---
5947		---	5947		---
5948	ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {	0	5948	ParseStatus AMDGPUAsmParser::parseCPol(OperandVector &Operands) {	0
5949	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	0	5949	StringRef Mnemo = ((AMDGPUOperand &)*Operands[0]).getToken();	0
5950	SMLoc OpLoc = getLoc();	0	5950	SMLoc OpLoc = getLoc();	0
5951	unsigned Enabled = 0, Seen = 0;	0	5951	unsigned Enabled = 0, Seen = 0;	0
5952	for (;;) {	---	5952	for (;;) {	---
5953	SMLoc S = getLoc();	0	5953	SMLoc S = getLoc();	0
5954	bool Disabling;	---	5954	bool Disabling;	---
5955	unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);	0	5955	unsigned CPol = getCPolKind(getId(), Mnemo, Disabling);	0
5956	if (!CPol)	0	5956	if (!CPol)	0
5957	break;	0	5957	break;	0
5958		---	5958		---
5959	lex();	0	5959	lex();	0
5960		---	5960		---
5961	if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)	0	5961	if (!isGFX10Plus() && CPol == AMDGPU::CPol::DLC)	0
5962	return Error(S, "dlc modifier is not supported on this GPU");	0	5962	return Error(S, "dlc modifier is not supported on this GPU");	0
5963		---	5963		---
5964	if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)	0	5964	if (!isGFX90A() && CPol == AMDGPU::CPol::SCC)	0
5965	return Error(S, "scc modifier is not supported on this GPU");	0	5965	return Error(S, "scc modifier is not supported on this GPU");	0
5966		---	5966		---
5967	if (Seen & CPol)	0	5967	if (Seen & CPol)	0
5968	return Error(S, "duplicate cache policy modifier");	0	5968	return Error(S, "duplicate cache policy modifier");	0
5969		---	5969		---
5970	if (!Disabling)	0	5970	if (!Disabling)	0
5971	Enabled \|= CPol;	0	5971	Enabled \|= CPol;	0
5972		---	5972		---
5973	Seen \|= CPol;	0	5973	Seen \|= CPol;	0
5974	}	0	5974	}	0
5975		---	5975		---
5976	if (!Seen)	0	5976	if (!Seen)	0
5977	return ParseStatus::NoMatch;	0	5977	return ParseStatus::NoMatch;	0
5978		---	5978		---
5979	Operands.push_back(	0	5979	Operands.push_back(	0
5980	AMDGPUOperand::CreateImm(this, Enabled, OpLoc, AMDGPUOperand::ImmTyCPol));	0	5980	AMDGPUOperand::CreateImm(this, Enabled, OpLoc, AMDGPUOperand::ImmTyCPol));	0
5981	return ParseStatus::Success;	0	5981	return ParseStatus::Success;	0
5982	}	---	5982	}	---
5983		---	5983		---
5984	static void addOptionalImmOperand(	0	5984	static void addOptionalImmOperand(	0
5985	MCInst& Inst, const OperandVector& Operands,	---	5985	MCInst& Inst, const OperandVector& Operands,	---
5986	AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,	---	5986	AMDGPUAsmParser::OptionalImmIndexMap& OptionalIdx,	---
5987	AMDGPUOperand::ImmTy ImmT,	---	5987	AMDGPUOperand::ImmTy ImmT,	---
5988	int64_t Default = 0) {	---	5988	int64_t Default = 0) {	---
5989	auto i = OptionalIdx.find(ImmT);	0	5989	auto i = OptionalIdx.find(ImmT);	0
5990	if (i != OptionalIdx.end()) {	0	5990	if (i != OptionalIdx.end()) {	0
5991	unsigned Idx = i->second;	0	5991	unsigned Idx = i->second;	0
5992	((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);	0	5992	((AMDGPUOperand &)*Operands[Idx]).addImmOperands(Inst, 1);	0
5993	} else {	---	5993	} else {	---
5994	Inst.addOperand(MCOperand::createImm(Default));	0	5994	Inst.addOperand(MCOperand::createImm(Default));	0
5995	}	---	5995	}	---
5996	}	0	5996	}	0
5997		---	5997		---
5998	ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,	0	5998	ParseStatus AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix,	0
5999	StringRef &Value,	---	5999	StringRef &Value,	---
6000	SMLoc &StringLoc) {	---	6000	SMLoc &StringLoc) {	---
6001	if (!trySkipId(Prefix, AsmToken::Colon))	0	6001	if (!trySkipId(Prefix, AsmToken::Colon))	0
6002	return ParseStatus::NoMatch;	0	6002	return ParseStatus::NoMatch;	0
6003		---	6003		---
6004	StringLoc = getLoc();	0	6004	StringLoc = getLoc();	0
6005	return parseId(Value, "expected an identifier") ? ParseStatus::Success	0	6005	return parseId(Value, "expected an identifier") ? ParseStatus::Success	0
6006	: ParseStatus::Failure;	0	6006	: ParseStatus::Failure;	0
6007	}	---	6007	}	---
6008		---	6008		---
6009	//===----------------------------------------------------------------------===//	---	6009	//===----------------------------------------------------------------------===//	---
6010	// MTBUF format	---	6010	// MTBUF format	---
6011	//===----------------------------------------------------------------------===//	---	6011	//===----------------------------------------------------------------------===//	---
6012		---	6012		---
6013	bool AMDGPUAsmParser::tryParseFmt(const char *Pref,	0	6013	bool AMDGPUAsmParser::tryParseFmt(const char *Pref,	0
6014	int64_t MaxVal,	---	6014	int64_t MaxVal,	---
6015	int64_t &Fmt) {	---	6015	int64_t &Fmt) {	---
6016	int64_t Val;	---	6016	int64_t Val;	---
6017	SMLoc Loc = getLoc();	0	6017	SMLoc Loc = getLoc();	0
6018		---	6018		---
6019	auto Res = parseIntWithPrefix(Pref, Val);	0	6019	auto Res = parseIntWithPrefix(Pref, Val);	0
6020	if (Res.isFailure())	0	6020	if (Res.isFailure())	0
6021	return false;	0	6021	return false;	0
6022	if (Res.isNoMatch())	0	6022	if (Res.isNoMatch())	0
6023	return true;	0	6023	return true;	0
6024		---	6024		---
6025	if (Val < 0 \|\| Val > MaxVal) {	0	6025	if (Val < 0 \|\| Val > MaxVal) {	0
6026	Error(Loc, Twine("out of range ", StringRef(Pref)));	0	6026	Error(Loc, Twine("out of range ", StringRef(Pref)));	0
6027	return false;	0	6027	return false;	0
6028	}	---	6028	}	---
6029		---	6029		---
6030	Fmt = Val;	0	6030	Fmt = Val;	0
6031	return true;	0	6031	return true;	0
6032	}	---	6032	}	---
6033		---	6033		---
6034	// dfmt and nfmt (in a tbuffer instruction) are parsed as one to allow their	---	6034	// dfmt and nfmt (in a tbuffer instruction) are parsed as one to allow their	---
6035	// values to live in a joint format operand in the MCInst encoding.	---	6035	// values to live in a joint format operand in the MCInst encoding.	---
6036	ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {	0	6036	ParseStatus AMDGPUAsmParser::parseDfmtNfmt(int64_t &Format) {	0
6037	using namespace llvm::AMDGPU::MTBUFFormat;	---	6037	using namespace llvm::AMDGPU::MTBUFFormat;	---
6038		---	6038		---
6039	int64_t Dfmt = DFMT_UNDEF;	0	6039	int64_t Dfmt = DFMT_UNDEF;	0
6040	int64_t Nfmt = NFMT_UNDEF;	0	6040	int64_t Nfmt = NFMT_UNDEF;	0
6041		---	6041		---
6042	// dfmt and nfmt can appear in either order, and each is optional.	---	6042	// dfmt and nfmt can appear in either order, and each is optional.	---
6043	for (int I = 0; I < 2; ++I) {	0	6043	for (int I = 0; I < 2; ++I) {	0
6044	if (Dfmt == DFMT_UNDEF && !tryParseFmt("dfmt", DFMT_MAX, Dfmt))	0	6044	if (Dfmt == DFMT_UNDEF && !tryParseFmt("dfmt", DFMT_MAX, Dfmt))	0
6045	return ParseStatus::Failure;	0	6045	return ParseStatus::Failure;	0
6046		---	6046		---
6047	if (Nfmt == NFMT_UNDEF && !tryParseFmt("nfmt", NFMT_MAX, Nfmt))	0	6047	if (Nfmt == NFMT_UNDEF && !tryParseFmt("nfmt", NFMT_MAX, Nfmt))	0
6048	return ParseStatus::Failure;	0	6048	return ParseStatus::Failure;	0
6049		---	6049		---
6050	// Skip optional comma between dfmt/nfmt	---	6050	// Skip optional comma between dfmt/nfmt	---
6051	// but guard against 2 commas following each other.	---	6051	// but guard against 2 commas following each other.	---
6052	if ((Dfmt == DFMT_UNDEF) != (Nfmt == NFMT_UNDEF) &&	0	6052	if ((Dfmt == DFMT_UNDEF) != (Nfmt == NFMT_UNDEF) &&	0
6053	!peekToken().is(AsmToken::Comma)) {	0	6053	!peekToken().is(AsmToken::Comma)) {	0
6054	trySkipToken(AsmToken::Comma);	0	6054	trySkipToken(AsmToken::Comma);	0
6055	}	---	6055	}	---
6056	}	---	6056	}	---
6057		---	6057		---
6058	if (Dfmt == DFMT_UNDEF && Nfmt == NFMT_UNDEF)	0	6058	if (Dfmt == DFMT_UNDEF && Nfmt == NFMT_UNDEF)	0
6059	return ParseStatus::NoMatch;	0	6059	return ParseStatus::NoMatch;	0
6060		---	6060		---
6061	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	0	6061	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	0
6062	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	0	6062	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	0
6063		---	6063		---
6064	Format = encodeDfmtNfmt(Dfmt, Nfmt);	0	6064	Format = encodeDfmtNfmt(Dfmt, Nfmt);	0
6065	return ParseStatus::Success;	0	6065	return ParseStatus::Success;	0
6066	}	---	6066	}	---
6067		---	6067		---
6068	ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {	0	6068	ParseStatus AMDGPUAsmParser::parseUfmt(int64_t &Format) {	0
6069	using namespace llvm::AMDGPU::MTBUFFormat;	---	6069	using namespace llvm::AMDGPU::MTBUFFormat;	---
6070		---	6070		---
6071	int64_t Fmt = UFMT_UNDEF;	0	6071	int64_t Fmt = UFMT_UNDEF;	0
6072		---	6072		---
6073	if (!tryParseFmt("format", UFMT_MAX, Fmt))	0	6073	if (!tryParseFmt("format", UFMT_MAX, Fmt))	0
6074	return ParseStatus::Failure;	0	6074	return ParseStatus::Failure;	0
6075		---	6075		---
6076	if (Fmt == UFMT_UNDEF)	0	6076	if (Fmt == UFMT_UNDEF)	0
6077	return ParseStatus::NoMatch;	0	6077	return ParseStatus::NoMatch;	0
6078		---	6078		---
6079	Format = Fmt;	0	6079	Format = Fmt;	0
6080	return ParseStatus::Success;	0	6080	return ParseStatus::Success;	0
6081	}	---	6081	}	---
6082		---	6082		---
6083	bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,	0	6083	bool AMDGPUAsmParser::matchDfmtNfmt(int64_t &Dfmt,	0
6084	int64_t &Nfmt,	---	6084	int64_t &Nfmt,	---
6085	StringRef FormatStr,	---	6085	StringRef FormatStr,	---
6086	SMLoc Loc) {	---	6086	SMLoc Loc) {	---
6087	using namespace llvm::AMDGPU::MTBUFFormat;	---	6087	using namespace llvm::AMDGPU::MTBUFFormat;	---
6088	int64_t Format;	---	6088	int64_t Format;	---
6089		---	6089		---
6090	Format = getDfmt(FormatStr);	0	6090	Format = getDfmt(FormatStr);	0
6091	if (Format != DFMT_UNDEF) {	0	6091	if (Format != DFMT_UNDEF) {	0
6092	Dfmt = Format;	0	6092	Dfmt = Format;	0
6093	return true;	0	6093	return true;	0
6094	}	---	6094	}	---
6095		---	6095		---
6096	Format = getNfmt(FormatStr, getSTI());	0	6096	Format = getNfmt(FormatStr, getSTI());	0
6097	if (Format != NFMT_UNDEF) {	0	6097	if (Format != NFMT_UNDEF) {	0
6098	Nfmt = Format;	0	6098	Nfmt = Format;	0
6099	return true;	0	6099	return true;	0
6100	}	---	6100	}	---
6101		---	6101		---
6102	Error(Loc, "unsupported format");	0	6102	Error(Loc, "unsupported format");	0
6103	return false;	0	6103	return false;	0
6104	}	---	6104	}	---
6105		---	6105		---
6106	ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,	0	6106	ParseStatus AMDGPUAsmParser::parseSymbolicSplitFormat(StringRef FormatStr,	0
6107	SMLoc FormatLoc,	---	6107	SMLoc FormatLoc,	---
6108	int64_t &Format) {	---	6108	int64_t &Format) {	---
6109	using namespace llvm::AMDGPU::MTBUFFormat;	---	6109	using namespace llvm::AMDGPU::MTBUFFormat;	---
6110		---	6110		---
6111	int64_t Dfmt = DFMT_UNDEF;	0	6111	int64_t Dfmt = DFMT_UNDEF;	0
6112	int64_t Nfmt = NFMT_UNDEF;	0	6112	int64_t Nfmt = NFMT_UNDEF;	0
6113	if (!matchDfmtNfmt(Dfmt, Nfmt, FormatStr, FormatLoc))	0	6113	if (!matchDfmtNfmt(Dfmt, Nfmt, FormatStr, FormatLoc))	0
6114	return ParseStatus::Failure;	0	6114	return ParseStatus::Failure;	0
6115		---	6115		---
6116	if (trySkipToken(AsmToken::Comma)) {	0	6116	if (trySkipToken(AsmToken::Comma)) {	0
6117	StringRef Str;	0	6117	StringRef Str;	0
6118	SMLoc Loc = getLoc();	0	6118	SMLoc Loc = getLoc();	0
6119	if (!parseId(Str, "expected a format string") \|\|	0	6119	if (!parseId(Str, "expected a format string") \|\|	0
6120	!matchDfmtNfmt(Dfmt, Nfmt, Str, Loc))	0	6120	!matchDfmtNfmt(Dfmt, Nfmt, Str, Loc))	0
6121	return ParseStatus::Failure;	0	6121	return ParseStatus::Failure;	0
6122	if (Dfmt == DFMT_UNDEF)	0	6122	if (Dfmt == DFMT_UNDEF)	0
6123	return Error(Loc, "duplicate numeric format");	0	6123	return Error(Loc, "duplicate numeric format");	0
6124	if (Nfmt == NFMT_UNDEF)	0	6124	if (Nfmt == NFMT_UNDEF)	0
6125	return Error(Loc, "duplicate data format");	0	6125	return Error(Loc, "duplicate data format");	0
6126	}	---	6126	}	---
6127		---	6127		---
6128	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	0	6128	Dfmt = (Dfmt == DFMT_UNDEF) ? DFMT_DEFAULT : Dfmt;	0
6129	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	0	6129	Nfmt = (Nfmt == NFMT_UNDEF) ? NFMT_DEFAULT : Nfmt;	0
6130		---	6130		---
6131	if (isGFX10Plus()) {	0	6131	if (isGFX10Plus()) {	0
6132	auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt, getSTI());	0	6132	auto Ufmt = convertDfmtNfmt2Ufmt(Dfmt, Nfmt, getSTI());	0
6133	if (Ufmt == UFMT_UNDEF)	0	6133	if (Ufmt == UFMT_UNDEF)	0
6134	return Error(FormatLoc, "unsupported format");	0	6134	return Error(FormatLoc, "unsupported format");	0
6135	Format = Ufmt;	0	6135	Format = Ufmt;	0
6136	} else {	---	6136	} else {	---
6137	Format = encodeDfmtNfmt(Dfmt, Nfmt);	0	6137	Format = encodeDfmtNfmt(Dfmt, Nfmt);	0
6138	}	---	6138	}	---
6139		---	6139		---
6140	return ParseStatus::Success;	0	6140	return ParseStatus::Success;	0
6141	}	---	6141	}	---
6142		---	6142		---
6143	ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,	0	6143	ParseStatus AMDGPUAsmParser::parseSymbolicUnifiedFormat(StringRef FormatStr,	0
6144	SMLoc Loc,	---	6144	SMLoc Loc,	---
6145	int64_t &Format) {	---	6145	int64_t &Format) {	---
6146	using namespace llvm::AMDGPU::MTBUFFormat;	---	6146	using namespace llvm::AMDGPU::MTBUFFormat;	---
6147		---	6147		---
6148	auto Id = getUnifiedFormat(FormatStr, getSTI());	0	6148	auto Id = getUnifiedFormat(FormatStr, getSTI());	0
6149	if (Id == UFMT_UNDEF)	0	6149	if (Id == UFMT_UNDEF)	0
6150	return ParseStatus::NoMatch;	0	6150	return ParseStatus::NoMatch;	0
6151		---	6151		---
6152	if (!isGFX10Plus())	0	6152	if (!isGFX10Plus())	0
6153	return Error(Loc, "unified format is not supported on this GPU");	0	6153	return Error(Loc, "unified format is not supported on this GPU");	0
6154		---	6154		---
6155	Format = Id;	0	6155	Format = Id;	0
6156	return ParseStatus::Success;	0	6156	return ParseStatus::Success;	0
6157	}	---	6157	}	---
6158		---	6158		---
6159	ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {	0	6159	ParseStatus AMDGPUAsmParser::parseNumericFormat(int64_t &Format) {	0
6160	using namespace llvm::AMDGPU::MTBUFFormat;	---	6160	using namespace llvm::AMDGPU::MTBUFFormat;	---
6161	SMLoc Loc = getLoc();	0	6161	SMLoc Loc = getLoc();	0
6162		---	6162		---
6163	if (!parseExpr(Format))	0	6163	if (!parseExpr(Format))	0
6164	return ParseStatus::Failure;	0	6164	return ParseStatus::Failure;	0
6165	if (!isValidFormatEncoding(Format, getSTI()))	0	6165	if (!isValidFormatEncoding(Format, getSTI()))	0
6166	return Error(Loc, "out of range format");	0	6166	return Error(Loc, "out of range format");	0
6167		---	6167		---
6168	return ParseStatus::Success;	0	6168	return ParseStatus::Success;	0
6169	}	---	6169	}	---
6170		---	6170		---
6171	ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {	0	6171	ParseStatus AMDGPUAsmParser::parseSymbolicOrNumericFormat(int64_t &Format) {	0
6172	using namespace llvm::AMDGPU::MTBUFFormat;	---	6172	using namespace llvm::AMDGPU::MTBUFFormat;	---
6173		---	6173		---
6174	if (!trySkipId("format", AsmToken::Colon))	0	6174	if (!trySkipId("format", AsmToken::Colon))	0
6175	return ParseStatus::NoMatch;	0	6175	return ParseStatus::NoMatch;	0
6176		---	6176		---
6177	if (trySkipToken(AsmToken::LBrac)) {	0	6177	if (trySkipToken(AsmToken::LBrac)) {	0
6178	StringRef FormatStr;	0	6178	StringRef FormatStr;	0
6179	SMLoc Loc = getLoc();	0	6179	SMLoc Loc = getLoc();	0
6180	if (!parseId(FormatStr, "expected a format string"))	0	6180	if (!parseId(FormatStr, "expected a format string"))	0
6181	return ParseStatus::Failure;	0	6181	return ParseStatus::Failure;	0
6182		---	6182		---
6183	auto Res = parseSymbolicUnifiedFormat(FormatStr, Loc, Format);	0	6183	auto Res = parseSymbolicUnifiedFormat(FormatStr, Loc, Format);	0
6184	if (Res.isNoMatch())	0	6184	if (Res.isNoMatch())	0
6185	Res = parseSymbolicSplitFormat(FormatStr, Loc, Format);	0	6185	Res = parseSymbolicSplitFormat(FormatStr, Loc, Format);	0
6186	if (!Res.isSuccess())	0	6186	if (!Res.isSuccess())	0
6187	return Res;	0	6187	return Res;	0
6188		---	6188		---
6189	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0	6189	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
6190	return ParseStatus::Failure;	0	6190	return ParseStatus::Failure;	0
6191		---	6191		---
6192	return ParseStatus::Success;	0	6192	return ParseStatus::Success;	0
6193	}	---	6193	}	---
6194		---	6194		---
6195	return parseNumericFormat(Format);	0	6195	return parseNumericFormat(Format);	0
6196	}	---	6196	}	---
6197		---	6197		---
6198	ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {	0	6198	ParseStatus AMDGPUAsmParser::parseFORMAT(OperandVector &Operands) {	0
6199	using namespace llvm::AMDGPU::MTBUFFormat;	---	6199	using namespace llvm::AMDGPU::MTBUFFormat;	---
6200		---	6200		---
6201	int64_t Format = getDefaultFormatEncoding(getSTI());	0	6201	int64_t Format = getDefaultFormatEncoding(getSTI());	0
6202	ParseStatus Res;	0	6202	ParseStatus Res;	0
6203	SMLoc Loc = getLoc();	0	6203	SMLoc Loc = getLoc();	0
6204		---	6204		---
6205	// Parse legacy format syntax.	---	6205	// Parse legacy format syntax.	---
6206	Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format);	0	6206	Res = isGFX10Plus() ? parseUfmt(Format) : parseDfmtNfmt(Format);	0
6207	if (Res.isFailure())	0	6207	if (Res.isFailure())	0
6208	return Res;	0	6208	return Res;	0
6209		---	6209		---
6210	bool FormatFound = Res.isSuccess();	0	6210	bool FormatFound = Res.isSuccess();	0
6211		---	6211		---
6212	Operands.push_back(	0	6212	Operands.push_back(	0
6213	AMDGPUOperand::CreateImm(this, Format, Loc, AMDGPUOperand::ImmTyFORMAT));	0	6213	AMDGPUOperand::CreateImm(this, Format, Loc, AMDGPUOperand::ImmTyFORMAT));	0
6214		---	6214		---
6215	if (FormatFound)	0	6215	if (FormatFound)	0
6216	trySkipToken(AsmToken::Comma);	0	6216	trySkipToken(AsmToken::Comma);	0
6217		---	6217		---
6218	if (isToken(AsmToken::EndOfStatement)) {	0	6218	if (isToken(AsmToken::EndOfStatement)) {	0
6219	// We are expecting an soffset operand,	---	6219	// We are expecting an soffset operand,	---
6220	// but let matcher handle the error.	---	6220	// but let matcher handle the error.	---
6221	return ParseStatus::Success;	0	6221	return ParseStatus::Success;	0
6222	}	---	6222	}	---
6223		---	6223		---
6224	// Parse soffset.	---	6224	// Parse soffset.	---
6225	Res = parseRegOrImm(Operands);	0	6225	Res = parseRegOrImm(Operands);	0
6226	if (!Res.isSuccess())	0	6226	if (!Res.isSuccess())	0
6227	return Res;	0	6227	return Res;	0
6228		---	6228		---
6229	trySkipToken(AsmToken::Comma);	0	6229	trySkipToken(AsmToken::Comma);	0
6230		---	6230		---
6231	if (!FormatFound) {	0	6231	if (!FormatFound) {	0
6232	Res = parseSymbolicOrNumericFormat(Format);	0	6232	Res = parseSymbolicOrNumericFormat(Format);	0
6233	if (Res.isFailure())	0	6233	if (Res.isFailure())	0
6234	return Res;	0	6234	return Res;	0
6235	if (Res.isSuccess()) {	0	6235	if (Res.isSuccess()) {	0
6236	auto Size = Operands.size();	0	6236	auto Size = Operands.size();	0
6237	AMDGPUOperand &Op = static_cast(*Operands[Size - 2]);	0	6237	AMDGPUOperand &Op = static_cast(*Operands[Size - 2]);	0
6238	assert(Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyFORMAT);	0	6238	assert(Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyFORMAT);	0
6239	Op.setImm(Format);	0	6239	Op.setImm(Format);	0
6240	}	---	6240	}	---
6241	return ParseStatus::Success;	0	6241	return ParseStatus::Success;	0
6242	}	---	6242	}	---
6243		---	6243		---
6244	if (isId("format") && peekToken().is(AsmToken::Colon))	0	6244	if (isId("format") && peekToken().is(AsmToken::Colon))	0
6245	return Error(getLoc(), "duplicate format");	0	6245	return Error(getLoc(), "duplicate format");	0
6246	return ParseStatus::Success;	0	6246	return ParseStatus::Success;	0
6247	}	---	6247	}	---
6248		---	6248		---
6249	ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {	0	6249	ParseStatus AMDGPUAsmParser::parseFlatOffset(OperandVector &Operands) {	0
6250	ParseStatus Res =	---	6250	ParseStatus Res =	---
6251	parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);	0	6251	parseIntWithPrefix("offset", Operands, AMDGPUOperand::ImmTyOffset);	0
6252	if (Res.isNoMatch()) {	0	6252	if (Res.isNoMatch()) {	0
6253	Res = parseIntWithPrefix("inst_offset", Operands,	0	6253	Res = parseIntWithPrefix("inst_offset", Operands,	0
6254	AMDGPUOperand::ImmTyInstOffset);	---	6254	AMDGPUOperand::ImmTyInstOffset);	---
6255	}	---	6255	}	---
6256	return Res;	0	6256	return Res;	0
6257	}	---	6257	}	---
6258		---	6258		---
6259	ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {	0	6259	ParseStatus AMDGPUAsmParser::parseR128A16(OperandVector &Operands) {	0
6260	ParseStatus Res =	---	6260	ParseStatus Res =	---
6261	parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);	0	6261	parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128A16);	0
6262	if (Res.isNoMatch())	0	6262	if (Res.isNoMatch())	0
6263	Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);	0	6263	Res = parseNamedBit("a16", Operands, AMDGPUOperand::ImmTyA16);	0
6264	return Res;	0	6264	return Res;	0
6265	}	---	6265	}	---
6266		---	6266		---
6267	ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {	0	6267	ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {	0
6268	ParseStatus Res =	---	6268	ParseStatus Res =	---
6269	parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);	0	6269	parseIntWithPrefix("blgp", Operands, AMDGPUOperand::ImmTyBLGP);	0
6270	if (Res.isNoMatch()) {	0	6270	if (Res.isNoMatch()) {	0
6271	Res =	---	6271	Res =	---
6272	parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);	0	6272	parseOperandArrayWithPrefix("neg", Operands, AMDGPUOperand::ImmTyBLGP);	0
6273	}	---	6273	}	---
6274	return Res;	0	6274	return Res;	0
6275	}	---	6275	}	---
6276		---	6276		---
6277	//===----------------------------------------------------------------------===//	---	6277	//===----------------------------------------------------------------------===//	---
6278	// Exp	---	6278	// Exp	---
6279	//===----------------------------------------------------------------------===//	---	6279	//===----------------------------------------------------------------------===//	---
6280		---	6280		---
6281	void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {	0	6281	void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {	0
6282	OptionalImmIndexMap OptionalIdx;	0	6282	OptionalImmIndexMap OptionalIdx;	0
6283		---	6283		---
6284	unsigned OperandIdx[4];	---	6284	unsigned OperandIdx[4];	---
6285	unsigned EnMask = 0;	0	6285	unsigned EnMask = 0;	0
6286	int SrcIdx = 0;	0	6286	int SrcIdx = 0;	0
6287		---	6287		---
6288	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0	6288	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
6289	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	6289	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
6290		---	6290		---
6291	// Add the register arguments	---	6291	// Add the register arguments	---
6292	if (Op.isReg()) {	0	6292	if (Op.isReg()) {	0
6293	assert(SrcIdx < 4);	0	6293	assert(SrcIdx < 4);	0
6294	OperandIdx[SrcIdx] = Inst.size();	0	6294	OperandIdx[SrcIdx] = Inst.size();	0
6295	Op.addRegOperands(Inst, 1);	0	6295	Op.addRegOperands(Inst, 1);	0
6296	++SrcIdx;	0	6296	++SrcIdx;	0
6297	continue;	0	6297	continue;	0
6298	}	---	6298	}	---
6299		---	6299		---
6300	if (Op.isOff()) {	0	6300	if (Op.isOff()) {	0
6301	assert(SrcIdx < 4);	0	6301	assert(SrcIdx < 4);	0
6302	OperandIdx[SrcIdx] = Inst.size();	0	6302	OperandIdx[SrcIdx] = Inst.size();	0
6303	Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));	0	6303	Inst.addOperand(MCOperand::createReg(AMDGPU::NoRegister));	0
6304	++SrcIdx;	0	6304	++SrcIdx;	0
6305	continue;	0	6305	continue;	0
6306	}	---	6306	}	---
6307		---	6307		---
6308	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {	0	6308	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyExpTgt) {	0
6309	Op.addImmOperands(Inst, 1);	0	6309	Op.addImmOperands(Inst, 1);	0
6310	continue;	0	6310	continue;	0
6311	}	---	6311	}	---
6312		---	6312		---
6313	if (Op.isToken() && (Op.getToken() == "done" \|\| Op.getToken() == "row_en"))	0	6313	if (Op.isToken() && (Op.getToken() == "done" \|\| Op.getToken() == "row_en"))	0
6314	continue;	0	6314	continue;	0
6315		---	6315		---
6316	// Handle optional arguments	---	6316	// Handle optional arguments	---
6317	OptionalIdx[Op.getImmTy()] = i;	0	6317	OptionalIdx[Op.getImmTy()] = i;	0
6318	}	---	6318	}	---
6319		---	6319		---
6320	assert(SrcIdx == 4);	0	6320	assert(SrcIdx == 4);	0
6321		---	6321		---
6322	bool Compr = false;	0	6322	bool Compr = false;	0
6323	if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {	0	6323	if (OptionalIdx.find(AMDGPUOperand::ImmTyExpCompr) != OptionalIdx.end()) {	0
6324	Compr = true;	0	6324	Compr = true;	0
6325	Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);	0	6325	Inst.getOperand(OperandIdx[1]) = Inst.getOperand(OperandIdx[2]);	0
6326	Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);	0	6326	Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);	0
6327	Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);	0	6327	Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);	0
6328	}	---	6328	}	---
6329		---	6329		---
6330	for (auto i = 0; i < SrcIdx; ++i) {	0	6330	for (auto i = 0; i < SrcIdx; ++i) {	0
6331	if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {	0	6331	if (Inst.getOperand(OperandIdx[i]).getReg() != AMDGPU::NoRegister) {	0
6332	EnMask \|= Compr? (0x3 << i * 2) : (0x1 << i);	0	6332	EnMask \|= Compr? (0x3 << i * 2) : (0x1 << i);	0
6333	}	---	6333	}	---
6334	}	---	6334	}	---
6335		---	6335		---
6336	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);	0	6336	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpVM);	0
6337	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);	0	6337	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyExpCompr);	0
6338		---	6338		---
6339	Inst.addOperand(MCOperand::createImm(EnMask));	0	6339	Inst.addOperand(MCOperand::createImm(EnMask));	0
6340	}	0	6340	}	0
6341		---	6341		---
6342	//===----------------------------------------------------------------------===//	---	6342	//===----------------------------------------------------------------------===//	---
6343	// s_waitcnt	---	6343	// s_waitcnt	---
6344	//===----------------------------------------------------------------------===//	---	6344	//===----------------------------------------------------------------------===//	---
6345		---	6345		---
6346	static bool	---	6346	static bool	---
6347	encodeCnt(	0	6347	encodeCnt(	0
6348	const AMDGPU::IsaVersion ISA,	---	6348	const AMDGPU::IsaVersion ISA,	---
6349	int64_t &IntVal,	---	6349	int64_t &IntVal,	---
6350	int64_t CntVal,	---	6350	int64_t CntVal,	---
6351	bool Saturate,	---	6351	bool Saturate,	---
6352	unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned),	---	6352	unsigned (*encode)(const IsaVersion &Version, unsigned, unsigned),	---
6353	unsigned (*decode)(const IsaVersion &Version, unsigned))	---	6353	unsigned (*decode)(const IsaVersion &Version, unsigned))	---
6354	{	---	6354	{	---
6355	bool Failed = false;	0	6355	bool Failed = false;	0
6356		---	6356		---
6357	IntVal = encode(ISA, IntVal, CntVal);	0	6357	IntVal = encode(ISA, IntVal, CntVal);	0
6358	if (CntVal != decode(ISA, IntVal)) {	0	6358	if (CntVal != decode(ISA, IntVal)) {	0
6359	if (Saturate) {	0	6359	if (Saturate) {	0
6360	IntVal = encode(ISA, IntVal, -1);	0	6360	IntVal = encode(ISA, IntVal, -1);	0
6361	} else {	---	6361	} else {	---
6362	Failed = true;	0	6362	Failed = true;	0
6363	}	---	6363	}	---
6364	}	---	6364	}	---
6365	return Failed;	0	6365	return Failed;	0
6366	}	---	6366	}	---
6367		---	6367		---
6368	bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {	0	6368	bool AMDGPUAsmParser::parseCnt(int64_t &IntVal) {	0
6369		---	6369		---
6370	SMLoc CntLoc = getLoc();	0	6370	SMLoc CntLoc = getLoc();	0
6371	StringRef CntName = getTokenStr();	0	6371	StringRef CntName = getTokenStr();	0
6372		---	6372		---
6373	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	0	6373	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	0
6374	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0	6374	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0
6375	return false;	0	6375	return false;	0
6376		---	6376		---
6377	int64_t CntVal;	---	6377	int64_t CntVal;	---
6378	SMLoc ValLoc = getLoc();	0	6378	SMLoc ValLoc = getLoc();	0
6379	if (!parseExpr(CntVal))	0	6379	if (!parseExpr(CntVal))	0
6380	return false;	0	6380	return false;	0
6381		---	6381		---
6382	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0	6382	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
6383		---	6383		---
6384	bool Failed = true;	0	6384	bool Failed = true;	0
6385	bool Sat = CntName.endswith("_sat");	0	6385	bool Sat = CntName.endswith("_sat");	0
6386		---	6386		---
6387	if (CntName == "vmcnt" \|\| CntName == "vmcnt_sat") {	0	6387	if (CntName == "vmcnt" \|\| CntName == "vmcnt_sat") {	0
6388	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeVmcnt, decodeVmcnt);	0	6388	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeVmcnt, decodeVmcnt);	0
6389	} else if (CntName == "expcnt" \|\| CntName == "expcnt_sat") {	0	6389	} else if (CntName == "expcnt" \|\| CntName == "expcnt_sat") {	0
6390	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeExpcnt, decodeExpcnt);	0	6390	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeExpcnt, decodeExpcnt);	0
6391	} else if (CntName == "lgkmcnt" \|\| CntName == "lgkmcnt_sat") {	0	6391	} else if (CntName == "lgkmcnt" \|\| CntName == "lgkmcnt_sat") {	0
6392	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeLgkmcnt, decodeLgkmcnt);	0	6392	Failed = encodeCnt(ISA, IntVal, CntVal, Sat, encodeLgkmcnt, decodeLgkmcnt);	0
6393	} else {	---	6393	} else {	---
6394	Error(CntLoc, "invalid counter name " + CntName);	0	6394	Error(CntLoc, "invalid counter name " + CntName);	0
6395	return false;	0	6395	return false;	0
6396	}	---	6396	}	---
6397		---	6397		---
6398	if (Failed) {	0	6398	if (Failed) {	0
6399	Error(ValLoc, "too large value for " + CntName);	0	6399	Error(ValLoc, "too large value for " + CntName);	0
6400	return false;	0	6400	return false;	0
6401	}	---	6401	}	---
6402		---	6402		---
6403	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	0	6403	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	0
6404	return false;	0	6404	return false;	0
6405		---	6405		---
6406	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	0	6406	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	0
6407	if (isToken(AsmToken::EndOfStatement)) {	0	6407	if (isToken(AsmToken::EndOfStatement)) {	0
6408	Error(getLoc(), "expected a counter name");	0	6408	Error(getLoc(), "expected a counter name");	0
6409	return false;	0	6409	return false;	0
6410	}	---	6410	}	---
6411	}	---	6411	}	---
6412		---	6412		---
6413	return true;	0	6413	return true;	0
6414	}	---	6414	}	---
6415		---	6415		---
6416	ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {	0	6416	ParseStatus AMDGPUAsmParser::parseSWaitCnt(OperandVector &Operands) {	0
6417	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0	6417	AMDGPU::IsaVersion ISA = AMDGPU::getIsaVersion(getSTI().getCPU());	0
6418	int64_t Waitcnt = getWaitcntBitMask(ISA);	0	6418	int64_t Waitcnt = getWaitcntBitMask(ISA);	0
6419	SMLoc S = getLoc();	0	6419	SMLoc S = getLoc();	0
6420		---	6420		---
6421	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0	6421	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0
6422	while (!isToken(AsmToken::EndOfStatement)) {	0	6422	while (!isToken(AsmToken::EndOfStatement)) {	0
6423	if (!parseCnt(Waitcnt))	0	6423	if (!parseCnt(Waitcnt))	0
6424	return ParseStatus::Failure;	0	6424	return ParseStatus::Failure;	0
6425	}	---	6425	}	---
6426	} else {	---	6426	} else {	---
6427	if (!parseExpr(Waitcnt))	0	6427	if (!parseExpr(Waitcnt))	0
6428	return ParseStatus::Failure;	0	6428	return ParseStatus::Failure;	0
6429	}	---	6429	}	---
6430		---	6430		---
6431	Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));	0	6431	Operands.push_back(AMDGPUOperand::CreateImm(this, Waitcnt, S));	0
6432	return ParseStatus::Success;	0	6432	return ParseStatus::Success;	0
6433	}	---	6433	}	---
6434		---	6434		---
6435	bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {	0	6435	bool AMDGPUAsmParser::parseDelay(int64_t &Delay) {	0
6436	SMLoc FieldLoc = getLoc();	0	6436	SMLoc FieldLoc = getLoc();	0
6437	StringRef FieldName = getTokenStr();	0	6437	StringRef FieldName = getTokenStr();	0
6438	if (!skipToken(AsmToken::Identifier, "expected a field name") \|\|	0	6438	if (!skipToken(AsmToken::Identifier, "expected a field name") \|\|	0
6439	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0	6439	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0
6440	return false;	0	6440	return false;	0
6441		---	6441		---
6442	SMLoc ValueLoc = getLoc();	0	6442	SMLoc ValueLoc = getLoc();	0
6443	StringRef ValueName = getTokenStr();	0	6443	StringRef ValueName = getTokenStr();	0
6444	if (!skipToken(AsmToken::Identifier, "expected a value name") \|\|	0	6444	if (!skipToken(AsmToken::Identifier, "expected a value name") \|\|	0
6445	!skipToken(AsmToken::RParen, "expected a right parenthesis"))	0	6445	!skipToken(AsmToken::RParen, "expected a right parenthesis"))	0
6446	return false;	0	6446	return false;	0
6447		---	6447		---
6448	unsigned Shift;	---	6448	unsigned Shift;	---
6449	if (FieldName == "instid0") {	0	6449	if (FieldName == "instid0") {	0
6450	Shift = 0;	0	6450	Shift = 0;	0
6451	} else if (FieldName == "instskip") {	0	6451	} else if (FieldName == "instskip") {	0
6452	Shift = 4;	0	6452	Shift = 4;	0
6453	} else if (FieldName == "instid1") {	0	6453	} else if (FieldName == "instid1") {	0
6454	Shift = 7;	0	6454	Shift = 7;	0
6455	} else {	---	6455	} else {	---
6456	Error(FieldLoc, "invalid field name " + FieldName);	0	6456	Error(FieldLoc, "invalid field name " + FieldName);	0
6457	return false;	0	6457	return false;	0
6458	}	---	6458	}	---
6459		---	6459		---
6460	int Value;	---	6460	int Value;	---
6461	if (Shift == 4) {	0	6461	if (Shift == 4) {	0
6462	// Parse values for instskip.	---	6462	// Parse values for instskip.	---
6463	Value = StringSwitch(ValueName)	0	6463	Value = StringSwitch(ValueName)	0
6464	.Case("SAME", 0)	0	6464	.Case("SAME", 0)	0
6465	.Case("NEXT", 1)	0	6465	.Case("NEXT", 1)	0
6466	.Case("SKIP_1", 2)	0	6466	.Case("SKIP_1", 2)	0
6467	.Case("SKIP_2", 3)	0	6467	.Case("SKIP_2", 3)	0
6468	.Case("SKIP_3", 4)	0	6468	.Case("SKIP_3", 4)	0
6469	.Case("SKIP_4", 5)	0	6469	.Case("SKIP_4", 5)	0
6470	.Default(-1);	0	6470	.Default(-1);	0
6471	} else {	---	6471	} else {	---
6472	// Parse values for instid0 and instid1.	---	6472	// Parse values for instid0 and instid1.	---
6473	Value = StringSwitch(ValueName)	0	6473	Value = StringSwitch(ValueName)	0
6474	.Case("NO_DEP", 0)	0	6474	.Case("NO_DEP", 0)	0
6475	.Case("VALU_DEP_1", 1)	0	6475	.Case("VALU_DEP_1", 1)	0
6476	.Case("VALU_DEP_2", 2)	0	6476	.Case("VALU_DEP_2", 2)	0
6477	.Case("VALU_DEP_3", 3)	0	6477	.Case("VALU_DEP_3", 3)	0
6478	.Case("VALU_DEP_4", 4)	0	6478	.Case("VALU_DEP_4", 4)	0
6479	.Case("TRANS32_DEP_1", 5)	0	6479	.Case("TRANS32_DEP_1", 5)	0
6480	.Case("TRANS32_DEP_2", 6)	0	6480	.Case("TRANS32_DEP_2", 6)	0
6481	.Case("TRANS32_DEP_3", 7)	0	6481	.Case("TRANS32_DEP_3", 7)	0
6482	.Case("FMA_ACCUM_CYCLE_1", 8)	0	6482	.Case("FMA_ACCUM_CYCLE_1", 8)	0
6483	.Case("SALU_CYCLE_1", 9)	0	6483	.Case("SALU_CYCLE_1", 9)	0
6484	.Case("SALU_CYCLE_2", 10)	0	6484	.Case("SALU_CYCLE_2", 10)	0
6485	.Case("SALU_CYCLE_3", 11)	0	6485	.Case("SALU_CYCLE_3", 11)	0
6486	.Default(-1);	0	6486	.Default(-1);	0
6487	}	---	6487	}	---
6488	if (Value < 0) {	0	6488	if (Value < 0) {	0
6489	Error(ValueLoc, "invalid value name " + ValueName);	0	6489	Error(ValueLoc, "invalid value name " + ValueName);	0
6490	return false;	0	6490	return false;	0
6491	}	---	6491	}	---
6492		---	6492		---
6493	Delay \|= Value << Shift;	0	6493	Delay \|= Value << Shift;	0
6494	return true;	0	6494	return true;	0
6495	}	---	6495	}	---
6496		---	6496		---
6497	ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {	0	6497	ParseStatus AMDGPUAsmParser::parseSDelayALU(OperandVector &Operands) {	0
6498	int64_t Delay = 0;	0	6498	int64_t Delay = 0;	0
6499	SMLoc S = getLoc();	0	6499	SMLoc S = getLoc();	0
6500		---	6500		---
6501	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0	6501	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0
6502	do {	---	6502	do {	---
6503	if (!parseDelay(Delay))	0	6503	if (!parseDelay(Delay))	0
6504	return ParseStatus::Failure;	0	6504	return ParseStatus::Failure;	0
6505	} while (trySkipToken(AsmToken::Pipe));	0	6505	} while (trySkipToken(AsmToken::Pipe));	0
6506	} else {	---	6506	} else {	---
6507	if (!parseExpr(Delay))	0	6507	if (!parseExpr(Delay))	0
6508	return ParseStatus::Failure;	0	6508	return ParseStatus::Failure;	0
6509	}	---	6509	}	---
6510		---	6510		---
6511	Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));	0	6511	Operands.push_back(AMDGPUOperand::CreateImm(this, Delay, S));	0
6512	return ParseStatus::Success;	0	6512	return ParseStatus::Success;	0
6513	}	---	6513	}	---
6514		---	6514		---
6515	bool	---	6515	bool	---
6516	AMDGPUOperand::isSWaitCnt() const {	0	6516	AMDGPUOperand::isSWaitCnt() const {	0
6517	return isImm();	0	6517	return isImm();	0
6518	}	---	6518	}	---
6519		---	6519		---
6520	bool AMDGPUOperand::isSDelayALU() const { return isImm(); }	0	6520	bool AMDGPUOperand::isSDelayALU() const { return isImm(); }	0
6521		---	6521		---
6522	//===----------------------------------------------------------------------===//	---	6522	//===----------------------------------------------------------------------===//	---
6523	// DepCtr	---	6523	// DepCtr	---
6524	//===----------------------------------------------------------------------===//	---	6524	//===----------------------------------------------------------------------===//	---
6525		---	6525		---
6526	void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,	0	6526	void AMDGPUAsmParser::depCtrError(SMLoc Loc, int ErrorId,	0
6527	StringRef DepCtrName) {	---	6527	StringRef DepCtrName) {	---
6528	switch (ErrorId) {	0	6528	switch (ErrorId) {	0
6529	case OPR_ID_UNKNOWN:	0	6529	case OPR_ID_UNKNOWN:	0
6530	Error(Loc, Twine("invalid counter name ", DepCtrName));	0	6530	Error(Loc, Twine("invalid counter name ", DepCtrName));	0
6531	return;	0	6531	return;	0
6532	case OPR_ID_UNSUPPORTED:	0	6532	case OPR_ID_UNSUPPORTED:	0
6533	Error(Loc, Twine(DepCtrName, " is not supported on this GPU"));	0	6533	Error(Loc, Twine(DepCtrName, " is not supported on this GPU"));	0
6534	return;	0	6534	return;	0
6535	case OPR_ID_DUPLICATE:	0	6535	case OPR_ID_DUPLICATE:	0
6536	Error(Loc, Twine("duplicate counter name ", DepCtrName));	0	6536	Error(Loc, Twine("duplicate counter name ", DepCtrName));	0
6537	return;	0	6537	return;	0
6538	case OPR_VAL_INVALID:	0	6538	case OPR_VAL_INVALID:	0
6539	Error(Loc, Twine("invalid value for ", DepCtrName));	0	6539	Error(Loc, Twine("invalid value for ", DepCtrName));	0
6540	return;	0	6540	return;	0
6541	default:	0	6541	default:	0
6542	assert(false);	0	6542	assert(false);	0
6543	}	---	6543	}	---
6544	}	---	6544	}	---
6545		---	6545		---
6546	bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {	0	6546	bool AMDGPUAsmParser::parseDepCtr(int64_t &DepCtr, unsigned &UsedOprMask) {	0
6547		---	6547		---
6548	using namespace llvm::AMDGPU::DepCtr;	---	6548	using namespace llvm::AMDGPU::DepCtr;	---
6549		---	6549		---
6550	SMLoc DepCtrLoc = getLoc();	0	6550	SMLoc DepCtrLoc = getLoc();	0
6551	StringRef DepCtrName = getTokenStr();	0	6551	StringRef DepCtrName = getTokenStr();	0
6552		---	6552		---
6553	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	0	6553	if (!skipToken(AsmToken::Identifier, "expected a counter name") \|\|	0
6554	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0	6554	!skipToken(AsmToken::LParen, "expected a left parenthesis"))	0
6555	return false;	0	6555	return false;	0
6556		---	6556		---
6557	int64_t ExprVal;	---	6557	int64_t ExprVal;	---
6558	if (!parseExpr(ExprVal))	0	6558	if (!parseExpr(ExprVal))	0
6559	return false;	0	6559	return false;	0
6560		---	6560		---
6561	unsigned PrevOprMask = UsedOprMask;	0	6561	unsigned PrevOprMask = UsedOprMask;	0
6562	int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());	0	6562	int CntVal = encodeDepCtr(DepCtrName, ExprVal, UsedOprMask, getSTI());	0
6563		---	6563		---
6564	if (CntVal < 0) {	0	6564	if (CntVal < 0) {	0
6565	depCtrError(DepCtrLoc, CntVal, DepCtrName);	0	6565	depCtrError(DepCtrLoc, CntVal, DepCtrName);	0
6566	return false;	0	6566	return false;	0
6567	}	---	6567	}	---
6568		---	6568		---
6569	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	0	6569	if (!skipToken(AsmToken::RParen, "expected a closing parenthesis"))	0
6570	return false;	0	6570	return false;	0
6571		---	6571		---
6572	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	0	6572	if (trySkipToken(AsmToken::Amp) \|\| trySkipToken(AsmToken::Comma)) {	0
6573	if (isToken(AsmToken::EndOfStatement)) {	0	6573	if (isToken(AsmToken::EndOfStatement)) {	0
6574	Error(getLoc(), "expected a counter name");	0	6574	Error(getLoc(), "expected a counter name");	0
6575	return false;	0	6575	return false;	0
6576	}	---	6576	}	---
6577	}	---	6577	}	---
6578		---	6578		---
6579	unsigned CntValMask = PrevOprMask ^ UsedOprMask;	0	6579	unsigned CntValMask = PrevOprMask ^ UsedOprMask;	0
6580	DepCtr = (DepCtr & ~CntValMask) \| CntVal;	0	6580	DepCtr = (DepCtr & ~CntValMask) \| CntVal;	0
6581	return true;	0	6581	return true;	0
6582	}	---	6582	}	---
6583		---	6583		---
6584	ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {	0	6584	ParseStatus AMDGPUAsmParser::parseDepCtr(OperandVector &Operands) {	0
6585	using namespace llvm::AMDGPU::DepCtr;	---	6585	using namespace llvm::AMDGPU::DepCtr;	---
6586		---	6586		---
6587	int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());	0	6587	int64_t DepCtr = getDefaultDepCtrEncoding(getSTI());	0
6588	SMLoc Loc = getLoc();	0	6588	SMLoc Loc = getLoc();	0
6589		---	6589		---
6590	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0	6590	if (isToken(AsmToken::Identifier) && peekToken().is(AsmToken::LParen)) {	0
6591	unsigned UsedOprMask = 0;	0	6591	unsigned UsedOprMask = 0;	0
6592	while (!isToken(AsmToken::EndOfStatement)) {	0	6592	while (!isToken(AsmToken::EndOfStatement)) {	0
6593	if (!parseDepCtr(DepCtr, UsedOprMask))	0	6593	if (!parseDepCtr(DepCtr, UsedOprMask))	0
6594	return ParseStatus::Failure;	0	6594	return ParseStatus::Failure;	0
6595	}	---	6595	}	---
6596	} else {	---	6596	} else {	---
6597	if (!parseExpr(DepCtr))	0	6597	if (!parseExpr(DepCtr))	0
6598	return ParseStatus::Failure;	0	6598	return ParseStatus::Failure;	0
6599	}	---	6599	}	---
6600		---	6600		---
6601	Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));	0	6601	Operands.push_back(AMDGPUOperand::CreateImm(this, DepCtr, Loc));	0
6602	return ParseStatus::Success;	0	6602	return ParseStatus::Success;	0
6603	}	---	6603	}	---
6604		---	6604		---
6605	bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }	0	6605	bool AMDGPUOperand::isDepCtr() const { return isS16Imm(); }	0
6606		---	6606		---
6607	//===----------------------------------------------------------------------===//	---	6607	//===----------------------------------------------------------------------===//	---
6608	// hwreg	---	6608	// hwreg	---
6609	//===----------------------------------------------------------------------===//	---	6609	//===----------------------------------------------------------------------===//	---
6610		---	6610		---
6611	bool	---	6611	bool	---
6612	AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,	0	6612	AMDGPUAsmParser::parseHwregBody(OperandInfoTy &HwReg,	0
6613	OperandInfoTy &Offset,	---	6613	OperandInfoTy &Offset,	---
6614	OperandInfoTy &Width) {	---	6614	OperandInfoTy &Width) {	---
6615	using namespace llvm::AMDGPU::Hwreg;	---	6615	using namespace llvm::AMDGPU::Hwreg;	---
6616		---	6616		---
6617	// The register may be specified by name or using a numeric code	---	6617	// The register may be specified by name or using a numeric code	---
6618	HwReg.Loc = getLoc();	0	6618	HwReg.Loc = getLoc();	0
6619	if (isToken(AsmToken::Identifier) &&	0	6619	if (isToken(AsmToken::Identifier) &&	0
6620	(HwReg.Id = getHwregId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	0	6620	(HwReg.Id = getHwregId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	0
6621	HwReg.IsSymbolic = true;	0	6621	HwReg.IsSymbolic = true;	0
6622	lex(); // skip register name	0	6622	lex(); // skip register name	0
6623	} else if (!parseExpr(HwReg.Id, "a register name")) {	0	6623	} else if (!parseExpr(HwReg.Id, "a register name")) {	0
6624	return false;	0	6624	return false;	0
6625	}	---	6625	}	---
6626		---	6626		---
6627	if (trySkipToken(AsmToken::RParen))	0	6627	if (trySkipToken(AsmToken::RParen))	0
6628	return true;	0	6628	return true;	0
6629		---	6629		---
6630	// parse optional params	---	6630	// parse optional params	---
6631	if (!skipToken(AsmToken::Comma, "expected a comma or a closing parenthesis"))	0	6631	if (!skipToken(AsmToken::Comma, "expected a comma or a closing parenthesis"))	0
6632	return false;	0	6632	return false;	0
6633		---	6633		---
6634	Offset.Loc = getLoc();	0	6634	Offset.Loc = getLoc();	0
6635	if (!parseExpr(Offset.Id))	0	6635	if (!parseExpr(Offset.Id))	0
6636	return false;	0	6636	return false;	0
6637		---	6637		---
6638	if (!skipToken(AsmToken::Comma, "expected a comma"))	0	6638	if (!skipToken(AsmToken::Comma, "expected a comma"))	0
6639	return false;	0	6639	return false;	0
6640		---	6640		---
6641	Width.Loc = getLoc();	0	6641	Width.Loc = getLoc();	0
6642	return parseExpr(Width.Id) &&	0	6642	return parseExpr(Width.Id) &&	0
6643	skipToken(AsmToken::RParen, "expected a closing parenthesis");	0	6643	skipToken(AsmToken::RParen, "expected a closing parenthesis");	0
6644	}	---	6644	}	---
6645		---	6645		---
6646	bool	---	6646	bool	---
6647	AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,	0	6647	AMDGPUAsmParser::validateHwreg(const OperandInfoTy &HwReg,	0
6648	const OperandInfoTy &Offset,	---	6648	const OperandInfoTy &Offset,	---
6649	const OperandInfoTy &Width) {	---	6649	const OperandInfoTy &Width) {	---
6650		---	6650		---
6651	using namespace llvm::AMDGPU::Hwreg;	---	6651	using namespace llvm::AMDGPU::Hwreg;	---
6652		---	6652		---
6653	if (HwReg.IsSymbolic) {	0	6653	if (HwReg.IsSymbolic) {	0
6654	if (HwReg.Id == OPR_ID_UNSUPPORTED) {	0	6654	if (HwReg.Id == OPR_ID_UNSUPPORTED) {	0
6655	Error(HwReg.Loc,	0	6655	Error(HwReg.Loc,	0
6656	"specified hardware register is not supported on this GPU");	---	6656	"specified hardware register is not supported on this GPU");	---
6657	return false;	0	6657	return false;	0
6658	}	---	6658	}	---
6659	} else {	---	6659	} else {	---
6660	if (!isValidHwreg(HwReg.Id)) {	0	6660	if (!isValidHwreg(HwReg.Id)) {	0
6661	Error(HwReg.Loc,	0	6661	Error(HwReg.Loc,	0
6662	"invalid code of hardware register: only 6-bit values are legal");	---	6662	"invalid code of hardware register: only 6-bit values are legal");	---
6663	return false;	0	6663	return false;	0
6664	}	---	6664	}	---
6665	}	---	6665	}	---
6666	if (!isValidHwregOffset(Offset.Id)) {	0	6666	if (!isValidHwregOffset(Offset.Id)) {	0
6667	Error(Offset.Loc, "invalid bit offset: only 5-bit values are legal");	0	6667	Error(Offset.Loc, "invalid bit offset: only 5-bit values are legal");	0
6668	return false;	0	6668	return false;	0
6669	}	---	6669	}	---
6670	if (!isValidHwregWidth(Width.Id)) {	0	6670	if (!isValidHwregWidth(Width.Id)) {	0
6671	Error(Width.Loc,	0	6671	Error(Width.Loc,	0
6672	"invalid bitfield width: only values from 1 to 32 are legal");	---	6672	"invalid bitfield width: only values from 1 to 32 are legal");	---
6673	return false;	0	6673	return false;	0
6674	}	---	6674	}	---
6675	return true;	0	6675	return true;	0
6676	}	---	6676	}	---
6677		---	6677		---
6678	ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {	0	6678	ParseStatus AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {	0
6679	using namespace llvm::AMDGPU::Hwreg;	---	6679	using namespace llvm::AMDGPU::Hwreg;	---
6680		---	6680		---
6681	int64_t ImmVal = 0;	0	6681	int64_t ImmVal = 0;	0
6682	SMLoc Loc = getLoc();	0	6682	SMLoc Loc = getLoc();	0
6683		---	6683		---
6684	if (trySkipId("hwreg", AsmToken::LParen)) {	0	6684	if (trySkipId("hwreg", AsmToken::LParen)) {	0
6685	OperandInfoTy HwReg(OPR_ID_UNKNOWN);	0	6685	OperandInfoTy HwReg(OPR_ID_UNKNOWN);	0
6686	OperandInfoTy Offset(OFFSET_DEFAULT_);	0	6686	OperandInfoTy Offset(OFFSET_DEFAULT_);	0
6687	OperandInfoTy Width(WIDTH_DEFAULT_);	0	6687	OperandInfoTy Width(WIDTH_DEFAULT_);	0
6688	if (parseHwregBody(HwReg, Offset, Width) &&	0	6688	if (parseHwregBody(HwReg, Offset, Width) &&	0
6689	validateHwreg(HwReg, Offset, Width)) {	0	6689	validateHwreg(HwReg, Offset, Width)) {	0
6690	ImmVal = encodeHwreg(HwReg.Id, Offset.Id, Width.Id);	0	6690	ImmVal = encodeHwreg(HwReg.Id, Offset.Id, Width.Id);	0
6691	} else {	---	6691	} else {	---
6692	return ParseStatus::Failure;	0	6692	return ParseStatus::Failure;	0
6693	}	---	6693	}	---
6694	} else if (parseExpr(ImmVal, "a hwreg macro")) {	0	6694	} else if (parseExpr(ImmVal, "a hwreg macro")) {	0
6695	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	0	6695	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	0
6696	return Error(Loc, "invalid immediate: only 16-bit values are legal");	0	6696	return Error(Loc, "invalid immediate: only 16-bit values are legal");	0
6697	} else {	---	6697	} else {	---
6698	return ParseStatus::Failure;	0	6698	return ParseStatus::Failure;	0
6699	}	---	6699	}	---
6700		---	6700		---
6701	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg));	0	6701	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTyHwreg));	0
6702	return ParseStatus::Success;	0	6702	return ParseStatus::Success;	0
6703	}	---	6703	}	---
6704		---	6704		---
6705	bool AMDGPUOperand::isHwreg() const {	0	6705	bool AMDGPUOperand::isHwreg() const {	0
6706	return isImmTy(ImmTyHwreg);	0	6706	return isImmTy(ImmTyHwreg);	0
6707	}	---	6707	}	---
6708		---	6708		---
6709	//===----------------------------------------------------------------------===//	---	6709	//===----------------------------------------------------------------------===//	---
6710	// sendmsg	---	6710	// sendmsg	---
6711	//===----------------------------------------------------------------------===//	---	6711	//===----------------------------------------------------------------------===//	---
6712		---	6712		---
6713	bool	---	6713	bool	---
6714	AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,	0	6714	AMDGPUAsmParser::parseSendMsgBody(OperandInfoTy &Msg,	0
6715	OperandInfoTy &Op,	---	6715	OperandInfoTy &Op,	---
6716	OperandInfoTy &Stream) {	---	6716	OperandInfoTy &Stream) {	---
6717	using namespace llvm::AMDGPU::SendMsg;	---	6717	using namespace llvm::AMDGPU::SendMsg;	---
6718		---	6718		---
6719	Msg.Loc = getLoc();	0	6719	Msg.Loc = getLoc();	0
6720	if (isToken(AsmToken::Identifier) &&	0	6720	if (isToken(AsmToken::Identifier) &&	0
6721	(Msg.Id = getMsgId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	0	6721	(Msg.Id = getMsgId(getTokenStr(), getSTI())) != OPR_ID_UNKNOWN) {	0
6722	Msg.IsSymbolic = true;	0	6722	Msg.IsSymbolic = true;	0
6723	lex(); // skip message name	0	6723	lex(); // skip message name	0
6724	} else if (!parseExpr(Msg.Id, "a message name")) {	0	6724	} else if (!parseExpr(Msg.Id, "a message name")) {	0
6725	return false;	0	6725	return false;	0
6726	}	---	6726	}	---
6727		---	6727		---
6728	if (trySkipToken(AsmToken::Comma)) {	0	6728	if (trySkipToken(AsmToken::Comma)) {	0
6729	Op.IsDefined = true;	0	6729	Op.IsDefined = true;	0
6730	Op.Loc = getLoc();	0	6730	Op.Loc = getLoc();	0
6731	if (isToken(AsmToken::Identifier) &&	0	6731	if (isToken(AsmToken::Identifier) &&	0
6732	(Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {	0	6732	(Op.Id = getMsgOpId(Msg.Id, getTokenStr())) >= 0) {	0
6733	lex(); // skip operation name	0	6733	lex(); // skip operation name	0
6734	} else if (!parseExpr(Op.Id, "an operation name")) {	0	6734	} else if (!parseExpr(Op.Id, "an operation name")) {	0
6735	return false;	0	6735	return false;	0
6736	}	---	6736	}	---
6737		---	6737		---
6738	if (trySkipToken(AsmToken::Comma)) {	0	6738	if (trySkipToken(AsmToken::Comma)) {	0
6739	Stream.IsDefined = true;	0	6739	Stream.IsDefined = true;	0
6740	Stream.Loc = getLoc();	0	6740	Stream.Loc = getLoc();	0
6741	if (!parseExpr(Stream.Id))	0	6741	if (!parseExpr(Stream.Id))	0
6742	return false;	0	6742	return false;	0
6743	}	---	6743	}	---
6744	}	---	6744	}	---
6745		---	6745		---
6746	return skipToken(AsmToken::RParen, "expected a closing parenthesis");	0	6746	return skipToken(AsmToken::RParen, "expected a closing parenthesis");	0
6747	}	---	6747	}	---
6748		---	6748		---
6749	bool	---	6749	bool	---
6750	AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,	0	6750	AMDGPUAsmParser::validateSendMsg(const OperandInfoTy &Msg,	0
6751	const OperandInfoTy &Op,	---	6751	const OperandInfoTy &Op,	---
6752	const OperandInfoTy &Stream) {	---	6752	const OperandInfoTy &Stream) {	---
6753	using namespace llvm::AMDGPU::SendMsg;	---	6753	using namespace llvm::AMDGPU::SendMsg;	---
6754		---	6754		---
6755	// Validation strictness depends on whether message is specified	---	6755	// Validation strictness depends on whether message is specified	---
6756	// in a symbolic or in a numeric form. In the latter case	---	6756	// in a symbolic or in a numeric form. In the latter case	---
6757	// only encoding possibility is checked.	---	6757	// only encoding possibility is checked.	---
6758	bool Strict = Msg.IsSymbolic;	0	6758	bool Strict = Msg.IsSymbolic;	0
6759		---	6759		---
6760	if (Strict) {	0	6760	if (Strict) {	0
6761	if (Msg.Id == OPR_ID_UNSUPPORTED) {	0	6761	if (Msg.Id == OPR_ID_UNSUPPORTED) {	0
6762	Error(Msg.Loc, "specified message id is not supported on this GPU");	0	6762	Error(Msg.Loc, "specified message id is not supported on this GPU");	0
6763	return false;	0	6763	return false;	0
6764	}	---	6764	}	---
6765	} else {	---	6765	} else {	---
6766	if (!isValidMsgId(Msg.Id, getSTI())) {	0	6766	if (!isValidMsgId(Msg.Id, getSTI())) {	0
6767	Error(Msg.Loc, "invalid message id");	0	6767	Error(Msg.Loc, "invalid message id");	0
6768	return false;	0	6768	return false;	0
6769	}	---	6769	}	---
6770	}	---	6770	}	---
6771	if (Strict && (msgRequiresOp(Msg.Id, getSTI()) != Op.IsDefined)) {	0	6771	if (Strict && (msgRequiresOp(Msg.Id, getSTI()) != Op.IsDefined)) {	0
6772	if (Op.IsDefined) {	0	6772	if (Op.IsDefined) {	0
6773	Error(Op.Loc, "message does not support operations");	0	6773	Error(Op.Loc, "message does not support operations");	0
6774	} else {	---	6774	} else {	---
6775	Error(Msg.Loc, "missing message operation");	0	6775	Error(Msg.Loc, "missing message operation");	0
6776	}	---	6776	}	---
6777	return false;	0	6777	return false;	0
6778	}	---	6778	}	---
6779	if (!isValidMsgOp(Msg.Id, Op.Id, getSTI(), Strict)) {	0	6779	if (!isValidMsgOp(Msg.Id, Op.Id, getSTI(), Strict)) {	0
6780	Error(Op.Loc, "invalid operation id");	0	6780	Error(Op.Loc, "invalid operation id");	0
6781	return false;	0	6781	return false;	0
6782	}	---	6782	}	---
6783	if (Strict && !msgSupportsStream(Msg.Id, Op.Id, getSTI()) &&	0	6783	if (Strict && !msgSupportsStream(Msg.Id, Op.Id, getSTI()) &&	0
6784	Stream.IsDefined) {	0	6784	Stream.IsDefined) {	0
6785	Error(Stream.Loc, "message operation does not support streams");	0	6785	Error(Stream.Loc, "message operation does not support streams");	0
6786	return false;	0	6786	return false;	0
6787	}	---	6787	}	---
6788	if (!isValidMsgStream(Msg.Id, Op.Id, Stream.Id, getSTI(), Strict)) {	0	6788	if (!isValidMsgStream(Msg.Id, Op.Id, Stream.Id, getSTI(), Strict)) {	0
6789	Error(Stream.Loc, "invalid message stream id");	0	6789	Error(Stream.Loc, "invalid message stream id");	0
6790	return false;	0	6790	return false;	0
6791	}	---	6791	}	---
6792	return true;	0	6792	return true;	0
6793	}	---	6793	}	---
6794		---	6794		---
6795	ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {	0	6795	ParseStatus AMDGPUAsmParser::parseSendMsg(OperandVector &Operands) {	0
6796	using namespace llvm::AMDGPU::SendMsg;	---	6796	using namespace llvm::AMDGPU::SendMsg;	---
6797		---	6797		---
6798	int64_t ImmVal = 0;	0	6798	int64_t ImmVal = 0;	0
6799	SMLoc Loc = getLoc();	0	6799	SMLoc Loc = getLoc();	0
6800		---	6800		---
6801	if (trySkipId("sendmsg", AsmToken::LParen)) {	0	6801	if (trySkipId("sendmsg", AsmToken::LParen)) {	0
6802	OperandInfoTy Msg(OPR_ID_UNKNOWN);	0	6802	OperandInfoTy Msg(OPR_ID_UNKNOWN);	0
6803	OperandInfoTy Op(OP_NONE_);	0	6803	OperandInfoTy Op(OP_NONE_);	0
6804	OperandInfoTy Stream(STREAM_ID_NONE_);	0	6804	OperandInfoTy Stream(STREAM_ID_NONE_);	0
6805	if (parseSendMsgBody(Msg, Op, Stream) &&	0	6805	if (parseSendMsgBody(Msg, Op, Stream) &&	0
6806	validateSendMsg(Msg, Op, Stream)) {	0	6806	validateSendMsg(Msg, Op, Stream)) {	0
6807	ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id);	0	6807	ImmVal = encodeMsg(Msg.Id, Op.Id, Stream.Id);	0
6808	} else {	---	6808	} else {	---
6809	return ParseStatus::Failure;	0	6809	return ParseStatus::Failure;	0
6810	}	---	6810	}	---
6811	} else if (parseExpr(ImmVal, "a sendmsg macro")) {	0	6811	} else if (parseExpr(ImmVal, "a sendmsg macro")) {	0
6812	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	0	6812	if (ImmVal < 0 \|\| !isUInt<16>(ImmVal))	0
6813	return Error(Loc, "invalid immediate: only 16-bit values are legal");	0	6813	return Error(Loc, "invalid immediate: only 16-bit values are legal");	0
6814	} else {	---	6814	} else {	---
6815	return ParseStatus::Failure;	0	6815	return ParseStatus::Failure;	0
6816	}	---	6816	}	---
6817		---	6817		---
6818	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));	0	6818	Operands.push_back(AMDGPUOperand::CreateImm(this, ImmVal, Loc, AMDGPUOperand::ImmTySendMsg));	0
6819	return ParseStatus::Success;	0	6819	return ParseStatus::Success;	0
6820	}	---	6820	}	---
6821		---	6821		---
6822	bool AMDGPUOperand::isSendMsg() const {	0	6822	bool AMDGPUOperand::isSendMsg() const {	0
6823	return isImmTy(ImmTySendMsg);	0	6823	return isImmTy(ImmTySendMsg);	0
6824	}	---	6824	}	---
6825		---	6825		---
6826	//===----------------------------------------------------------------------===//	---	6826	//===----------------------------------------------------------------------===//	---
6827	// v_interp	---	6827	// v_interp	---
6828	//===----------------------------------------------------------------------===//	---	6828	//===----------------------------------------------------------------------===//	---
6829		---	6829		---
6830	ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {	0	6830	ParseStatus AMDGPUAsmParser::parseInterpSlot(OperandVector &Operands) {	0
6831	StringRef Str;	0	6831	StringRef Str;	0
6832	SMLoc S = getLoc();	0	6832	SMLoc S = getLoc();	0
6833		---	6833		---
6834	if (!parseId(Str))	0	6834	if (!parseId(Str))	0
6835	return ParseStatus::NoMatch;	0	6835	return ParseStatus::NoMatch;	0
6836		---	6836		---
6837	int Slot = StringSwitch(Str)	0	6837	int Slot = StringSwitch(Str)	0
6838	.Case("p10", 0)	0	6838	.Case("p10", 0)	0
6839	.Case("p20", 1)	0	6839	.Case("p20", 1)	0
6840	.Case("p0", 2)	0	6840	.Case("p0", 2)	0
6841	.Default(-1);	0	6841	.Default(-1);	0
6842		---	6842		---
6843	if (Slot == -1)	0	6843	if (Slot == -1)	0
6844	return Error(S, "invalid interpolation slot");	0	6844	return Error(S, "invalid interpolation slot");	0
6845		---	6845		---
6846	Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,	0	6846	Operands.push_back(AMDGPUOperand::CreateImm(this, Slot, S,	0
6847	AMDGPUOperand::ImmTyInterpSlot));	---	6847	AMDGPUOperand::ImmTyInterpSlot));	---
6848	return ParseStatus::Success;	0	6848	return ParseStatus::Success;	0
6849	}	---	6849	}	---
6850		---	6850		---
6851	ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {	0	6851	ParseStatus AMDGPUAsmParser::parseInterpAttr(OperandVector &Operands) {	0
6852	StringRef Str;	0	6852	StringRef Str;	0
6853	SMLoc S = getLoc();	0	6853	SMLoc S = getLoc();	0
6854		---	6854		---
6855	if (!parseId(Str))	0	6855	if (!parseId(Str))	0
6856	return ParseStatus::NoMatch;	0	6856	return ParseStatus::NoMatch;	0
6857		---	6857		---
6858	if (!Str.startswith("attr"))	0	6858	if (!Str.startswith("attr"))	0
6859	return Error(S, "invalid interpolation attribute");	0	6859	return Error(S, "invalid interpolation attribute");	0
6860		---	6860		---
6861	StringRef Chan = Str.take_back(2);	0	6861	StringRef Chan = Str.take_back(2);	0
6862	int AttrChan = StringSwitch(Chan)	0	6862	int AttrChan = StringSwitch(Chan)	0
6863	.Case(".x", 0)	0	6863	.Case(".x", 0)	0
6864	.Case(".y", 1)	0	6864	.Case(".y", 1)	0
6865	.Case(".z", 2)	0	6865	.Case(".z", 2)	0
6866	.Case(".w", 3)	0	6866	.Case(".w", 3)	0
6867	.Default(-1);	0	6867	.Default(-1);	0
6868	if (AttrChan == -1)	0	6868	if (AttrChan == -1)	0
6869	return Error(S, "invalid or missing interpolation attribute channel");	0	6869	return Error(S, "invalid or missing interpolation attribute channel");	0
6870		---	6870		---
6871	Str = Str.drop_back(2).drop_front(4);	0	6871	Str = Str.drop_back(2).drop_front(4);	0
6872		---	6872		---
6873	uint8_t Attr;	---	6873	uint8_t Attr;	---
6874	if (Str.getAsInteger(10, Attr))	0	6874	if (Str.getAsInteger(10, Attr))	0
6875	return Error(S, "invalid or missing interpolation attribute number");	0	6875	return Error(S, "invalid or missing interpolation attribute number");	0
6876		---	6876		---
6877	if (Attr > 32)	0	6877	if (Attr > 32)	0
6878	return Error(S, "out of bounds interpolation attribute number");	0	6878	return Error(S, "out of bounds interpolation attribute number");	0
6879		---	6879		---
6880	SMLoc SChan = SMLoc::getFromPointer(Chan.data());	0	6880	SMLoc SChan = SMLoc::getFromPointer(Chan.data());	0
6881		---	6881		---
6882	Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,	0	6882	Operands.push_back(AMDGPUOperand::CreateImm(this, Attr, S,	0
6883	AMDGPUOperand::ImmTyInterpAttr));	---	6883	AMDGPUOperand::ImmTyInterpAttr));	---
6884	Operands.push_back(AMDGPUOperand::CreateImm(	0	6884	Operands.push_back(AMDGPUOperand::CreateImm(	0
6885	this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));	---	6885	this, AttrChan, SChan, AMDGPUOperand::ImmTyInterpAttrChan));	---
6886	return ParseStatus::Success;	0	6886	return ParseStatus::Success;	0
6887	}	---	6887	}	---
6888		---	6888		---
6889	//===----------------------------------------------------------------------===//	---	6889	//===----------------------------------------------------------------------===//	---
6890	// exp	---	6890	// exp	---
6891	//===----------------------------------------------------------------------===//	---	6891	//===----------------------------------------------------------------------===//	---
6892		---	6892		---
6893	ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {	0	6893	ParseStatus AMDGPUAsmParser::parseExpTgt(OperandVector &Operands) {	0
6894	using namespace llvm::AMDGPU::Exp;	---	6894	using namespace llvm::AMDGPU::Exp;	---
6895		---	6895		---
6896	StringRef Str;	0	6896	StringRef Str;	0
6897	SMLoc S = getLoc();	0	6897	SMLoc S = getLoc();	0
6898		---	6898		---
6899	if (!parseId(Str))	0	6899	if (!parseId(Str))	0
6900	return ParseStatus::NoMatch;	0	6900	return ParseStatus::NoMatch;	0
6901		---	6901		---
6902	unsigned Id = getTgtId(Str);	0	6902	unsigned Id = getTgtId(Str);	0
6903	if (Id == ET_INVALID \|\| !isSupportedTgtId(Id, getSTI()))	0	6903	if (Id == ET_INVALID \|\| !isSupportedTgtId(Id, getSTI()))	0
6904	return Error(S, (Id == ET_INVALID)	0	6904	return Error(S, (Id == ET_INVALID)	0
6905	? "invalid exp target"	---	6905	? "invalid exp target"	---
6906	: "exp target is not supported on this GPU");	0	6906	: "exp target is not supported on this GPU");	0
6907		---	6907		---
6908	Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,	0	6908	Operands.push_back(AMDGPUOperand::CreateImm(this, Id, S,	0
6909	AMDGPUOperand::ImmTyExpTgt));	---	6909	AMDGPUOperand::ImmTyExpTgt));	---
6910	return ParseStatus::Success;	0	6910	return ParseStatus::Success;	0
6911	}	---	6911	}	---
6912		---	6912		---
6913	//===----------------------------------------------------------------------===//	---	6913	//===----------------------------------------------------------------------===//	---
6914	// parser helpers	---	6914	// parser helpers	---
6915	//===----------------------------------------------------------------------===//	---	6915	//===----------------------------------------------------------------------===//	---
6916		---	6916		---
6917	bool	---	6917	bool	---
6918	AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {	0	6918	AMDGPUAsmParser::isId(const AsmToken &Token, const StringRef Id) const {	0
6919	return Token.is(AsmToken::Identifier) && Token.getString() == Id;	0	6919	return Token.is(AsmToken::Identifier) && Token.getString() == Id;	0
6920	}	---	6920	}	---
6921		---	6921		---
6922	bool	---	6922	bool	---
6923	AMDGPUAsmParser::isId(const StringRef Id) const {	0	6923	AMDGPUAsmParser::isId(const StringRef Id) const {	0
6924	return isId(getToken(), Id);	0	6924	return isId(getToken(), Id);	0
6925	}	---	6925	}	---
6926		---	6926		---
6927	bool	---	6927	bool	---
6928	AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {	0	6928	AMDGPUAsmParser::isToken(const AsmToken::TokenKind Kind) const {	0
6929	return getTokenKind() == Kind;	0	6929	return getTokenKind() == Kind;	0
6930	}	---	6930	}	---
6931		---	6931		---
6932	StringRef AMDGPUAsmParser::getId() const {	0	6932	StringRef AMDGPUAsmParser::getId() const {	0
6933	return isToken(AsmToken::Identifier) ? getTokenStr() : StringRef();	0	6933	return isToken(AsmToken::Identifier) ? getTokenStr() : StringRef();	0
6934	}	---	6934	}	---
6935		---	6935		---
6936	bool	---	6936	bool	---
6937	AMDGPUAsmParser::trySkipId(const StringRef Id) {	0	6937	AMDGPUAsmParser::trySkipId(const StringRef Id) {	0
6938	if (isId(Id)) {	0	6938	if (isId(Id)) {	0
6939	lex();	0	6939	lex();	0
6940	return true;	0	6940	return true;	0
6941	}	---	6941	}	---
6942	return false;	0	6942	return false;	0
6943	}	---	6943	}	---
6944		---	6944		---
6945	bool	---	6945	bool	---
6946	AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {	0	6946	AMDGPUAsmParser::trySkipId(const StringRef Pref, const StringRef Id) {	0
6947	if (isToken(AsmToken::Identifier)) {	0	6947	if (isToken(AsmToken::Identifier)) {	0
6948	StringRef Tok = getTokenStr();	0	6948	StringRef Tok = getTokenStr();	0
6949	if (Tok.startswith(Pref) && Tok.drop_front(Pref.size()) == Id) {	0	6949	if (Tok.startswith(Pref) && Tok.drop_front(Pref.size()) == Id) {	0
6950	lex();	0	6950	lex();	0
6951	return true;	0	6951	return true;	0
6952	}	---	6952	}	---
6953	}	---	6953	}	---
6954	return false;	0	6954	return false;	0
6955	}	---	6955	}	---
6956		---	6956		---
6957	bool	---	6957	bool	---
6958	AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {	0	6958	AMDGPUAsmParser::trySkipId(const StringRef Id, const AsmToken::TokenKind Kind) {	0
6959	if (isId(Id) && peekToken().is(Kind)) {	0	6959	if (isId(Id) && peekToken().is(Kind)) {	0
6960	lex();	0	6960	lex();	0
6961	lex();	0	6961	lex();	0
6962	return true;	0	6962	return true;	0
6963	}	---	6963	}	---
6964	return false;	0	6964	return false;	0
6965	}	---	6965	}	---
6966		---	6966		---
6967	bool	---	6967	bool	---
6968	AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {	0	6968	AMDGPUAsmParser::trySkipToken(const AsmToken::TokenKind Kind) {	0
6969	if (isToken(Kind)) {	0	6969	if (isToken(Kind)) {	0
6970	lex();	0	6970	lex();	0
6971	return true;	0	6971	return true;	0
6972	}	---	6972	}	---
6973	return false;	0	6973	return false;	0
6974	}	---	6974	}	---
6975		---	6975		---
6976	bool	---	6976	bool	---
6977	AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,	0	6977	AMDGPUAsmParser::skipToken(const AsmToken::TokenKind Kind,	0
6978	const StringRef ErrMsg) {	---	6978	const StringRef ErrMsg) {	---
6979	if (!trySkipToken(Kind)) {	0	6979	if (!trySkipToken(Kind)) {	0
6980	Error(getLoc(), ErrMsg);	0	6980	Error(getLoc(), ErrMsg);	0
6981	return false;	0	6981	return false;	0
6982	}	---	6982	}	---
6983	return true;	0	6983	return true;	0
6984	}	---	6984	}	---
6985		---	6985		---
6986	bool	---	6986	bool	---
6987	AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {	0	6987	AMDGPUAsmParser::parseExpr(int64_t &Imm, StringRef Expected) {	0
6988	SMLoc S = getLoc();	0	6988	SMLoc S = getLoc();	0
6989		---	6989		---
6990	const MCExpr *Expr;	---	6990	const MCExpr *Expr;	---
6991	if (Parser.parseExpression(Expr))	0	6991	if (Parser.parseExpression(Expr))	0
6992	return false;	0	6992	return false;	0
6993		---	6993		---
6994	if (Expr->evaluateAsAbsolute(Imm))	0	6994	if (Expr->evaluateAsAbsolute(Imm))	0
6995	return true;	0	6995	return true;	0
6996		---	6996		---
6997	if (Expected.empty()) {	0	6997	if (Expected.empty()) {	0
6998	Error(S, "expected absolute expression");	0	6998	Error(S, "expected absolute expression");	0
6999	} else {	---	6999	} else {	---
7000	Error(S, Twine("expected ", Expected) +	0	7000	Error(S, Twine("expected ", Expected) +	0
7001	Twine(" or an absolute expression"));	0	7001	Twine(" or an absolute expression"));	0
7002	}	---	7002	}	---
7003	return false;	0	7003	return false;	0
7004	}	---	7004	}	---
7005		---	7005		---
7006	bool	---	7006	bool	---
7007	AMDGPUAsmParser::parseExpr(OperandVector &Operands) {	0	7007	AMDGPUAsmParser::parseExpr(OperandVector &Operands) {	0
7008	SMLoc S = getLoc();	0	7008	SMLoc S = getLoc();	0
7009		---	7009		---
7010	const MCExpr *Expr;	---	7010	const MCExpr *Expr;	---
7011	if (Parser.parseExpression(Expr))	0	7011	if (Parser.parseExpression(Expr))	0
7012	return false;	0	7012	return false;	0
7013		---	7013		---
7014	int64_t IntVal;	---	7014	int64_t IntVal;	---
7015	if (Expr->evaluateAsAbsolute(IntVal)) {	0	7015	if (Expr->evaluateAsAbsolute(IntVal)) {	0
7016	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	0	7016	Operands.push_back(AMDGPUOperand::CreateImm(this, IntVal, S));	0
7017	} else {	---	7017	} else {	---
7018	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	0	7018	Operands.push_back(AMDGPUOperand::CreateExpr(this, Expr, S));	0
7019	}	---	7019	}	---
7020	return true;	0	7020	return true;	0
7021	}	---	7021	}	---
7022		---	7022		---
7023	bool	---	7023	bool	---
7024	AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {	0	7024	AMDGPUAsmParser::parseString(StringRef &Val, const StringRef ErrMsg) {	0
7025	if (isToken(AsmToken::String)) {	0	7025	if (isToken(AsmToken::String)) {	0
7026	Val = getToken().getStringContents();	0	7026	Val = getToken().getStringContents();	0
7027	lex();	0	7027	lex();	0
7028	return true;	0	7028	return true;	0
7029	} else {	---	7029	} else {	---
7030	Error(getLoc(), ErrMsg);	0	7030	Error(getLoc(), ErrMsg);	0
7031	return false;	0	7031	return false;	0
7032	}	---	7032	}	---
7033	}	---	7033	}	---
7034		---	7034		---
7035	bool	---	7035	bool	---
7036	AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {	0	7036	AMDGPUAsmParser::parseId(StringRef &Val, const StringRef ErrMsg) {	0
7037	if (isToken(AsmToken::Identifier)) {	0	7037	if (isToken(AsmToken::Identifier)) {	0
7038	Val = getTokenStr();	0	7038	Val = getTokenStr();	0
7039	lex();	0	7039	lex();	0
7040	return true;	0	7040	return true;	0
7041	} else {	---	7041	} else {	---
7042	if (!ErrMsg.empty())	0	7042	if (!ErrMsg.empty())	0
7043	Error(getLoc(), ErrMsg);	0	7043	Error(getLoc(), ErrMsg);	0
7044	return false;	0	7044	return false;	0
7045	}	---	7045	}	---
7046	}	---	7046	}	---
7047		---	7047		---
7048	AsmToken	---	7048	AsmToken	---
7049	AMDGPUAsmParser::getToken() const {	0	7049	AMDGPUAsmParser::getToken() const {	0
7050	return Parser.getTok();	0	7050	return Parser.getTok();	0
7051	}	---	7051	}	---
7052		---	7052		---
7053	AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {	0	7053	AsmToken AMDGPUAsmParser::peekToken(bool ShouldSkipSpace) {	0
7054	return isToken(AsmToken::EndOfStatement)	0	7054	return isToken(AsmToken::EndOfStatement)	0
7055	? getToken()	---	7055	? getToken()	---
7056	: getLexer().peekTok(ShouldSkipSpace);	0	7056	: getLexer().peekTok(ShouldSkipSpace);	0
7057	}	---	7057	}	---
7058		---	7058		---
7059	void	---	7059	void	---
7060	AMDGPUAsmParser::peekTokens(MutableArrayRef Tokens) {	0	7060	AMDGPUAsmParser::peekTokens(MutableArrayRef Tokens) {	0
7061	auto TokCount = getLexer().peekTokens(Tokens);	0	7061	auto TokCount = getLexer().peekTokens(Tokens);	0
7062		---	7062		---
7063	for (auto Idx = TokCount; Idx < Tokens.size(); ++Idx)	0	7063	for (auto Idx = TokCount; Idx < Tokens.size(); ++Idx)	0
7064	Tokens[Idx] = AsmToken(AsmToken::Error, "");	0	7064	Tokens[Idx] = AsmToken(AsmToken::Error, "");	0
7065	}	0	7065	}	0
7066		---	7066		---
7067	AsmToken::TokenKind	---	7067	AsmToken::TokenKind	---
7068	AMDGPUAsmParser::getTokenKind() const {	0	7068	AMDGPUAsmParser::getTokenKind() const {	0
7069	return getLexer().getKind();	0	7069	return getLexer().getKind();	0
7070	}	---	7070	}	---
7071		---	7071		---
7072	SMLoc	---	7072	SMLoc	---
7073	AMDGPUAsmParser::getLoc() const {	0	7073	AMDGPUAsmParser::getLoc() const {	0
7074	return getToken().getLoc();	0	7074	return getToken().getLoc();	0
7075	}	---	7075	}	---
7076		---	7076		---
7077	StringRef	---	7077	StringRef	---
7078	AMDGPUAsmParser::getTokenStr() const {	0	7078	AMDGPUAsmParser::getTokenStr() const {	0
7079	return getToken().getString();	0	7079	return getToken().getString();	0
7080	}	---	7080	}	---
7081		---	7081		---
7082	void	---	7082	void	---
7083	AMDGPUAsmParser::lex() {	0	7083	AMDGPUAsmParser::lex() {	0
7084	Parser.Lex();	0	7084	Parser.Lex();	0
7085	}	0	7085	}	0
7086		---	7086		---
7087	SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {	0	7087	SMLoc AMDGPUAsmParser::getInstLoc(const OperandVector &Operands) const {	0
7088	return ((AMDGPUOperand &)*Operands[0]).getStartLoc();	0	7088	return ((AMDGPUOperand &)*Operands[0]).getStartLoc();	0
7089	}	---	7089	}	---
7090		---	7090		---
7091	SMLoc	---	7091	SMLoc	---
7092	AMDGPUAsmParser::getOperandLoc(std::function Test,	0	7092	AMDGPUAsmParser::getOperandLoc(std::function Test,	0
7093	const OperandVector &Operands) const {	---	7093	const OperandVector &Operands) const {	---
7094	for (unsigned i = Operands.size() - 1; i > 0; --i) {	0	7094	for (unsigned i = Operands.size() - 1; i > 0; --i) {	0
7095	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	7095	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7096	if (Test(Op))	0	7096	if (Test(Op))	0
7097	return Op.getStartLoc();	0	7097	return Op.getStartLoc();	0
7098	}	---	7098	}	---
7099	return getInstLoc(Operands);	0	7099	return getInstLoc(Operands);	0
7100	}	---	7100	}	---
7101		---	7101		---
7102	SMLoc	---	7102	SMLoc	---
7103	AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,	0	7103	AMDGPUAsmParser::getImmLoc(AMDGPUOperand::ImmTy Type,	0
7104	const OperandVector &Operands) const {	---	7104	const OperandVector &Operands) const {	---
7105	auto Test = [=](const AMDGPUOperand& Op) { return Op.isImmTy(Type); };	0	7105	auto Test = [=](const AMDGPUOperand& Op) { return Op.isImmTy(Type); };	0
7106	return getOperandLoc(Test, Operands);	0	7106	return getOperandLoc(Test, Operands);	0
7107	}	---	7107	}	---
7108		---	7108		---
7109	SMLoc	---	7109	SMLoc	---
7110	AMDGPUAsmParser::getRegLoc(unsigned Reg,	0	7110	AMDGPUAsmParser::getRegLoc(unsigned Reg,	0
7111	const OperandVector &Operands) const {	---	7111	const OperandVector &Operands) const {	---
7112	auto Test = [=](const AMDGPUOperand& Op) {	0	7112	auto Test = [=](const AMDGPUOperand& Op) {	0
7113	return Op.isRegKind() && Op.getReg() == Reg;	0	7113	return Op.isRegKind() && Op.getReg() == Reg;	0
7114	};	0	7114	};	0
7115	return getOperandLoc(Test, Operands);	0	7115	return getOperandLoc(Test, Operands);	0
7116	}	---	7116	}	---
7117		---	7117		---
7118	SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,	0	7118	SMLoc AMDGPUAsmParser::getLitLoc(const OperandVector &Operands,	0
7119	bool SearchMandatoryLiterals) const {	---	7119	bool SearchMandatoryLiterals) const {	---
7120	auto Test = [](const AMDGPUOperand& Op) {	0	7120	auto Test = [](const AMDGPUOperand& Op) {	0
7121	return Op.IsImmKindLiteral() \|\| Op.isExpr();	0	7121	return Op.IsImmKindLiteral() \|\| Op.isExpr();	0
7122	};	---	7122	};	---
7123	SMLoc Loc = getOperandLoc(Test, Operands);	0	7123	SMLoc Loc = getOperandLoc(Test, Operands);	0
7124	if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))	0	7124	if (SearchMandatoryLiterals && Loc == getInstLoc(Operands))	0
7125	Loc = getMandatoryLitLoc(Operands);	0	7125	Loc = getMandatoryLitLoc(Operands);	0
7126	return Loc;	0	7126	return Loc;	0
7127	}	---	7127	}	---
7128		---	7128		---
7129	SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {	0	7129	SMLoc AMDGPUAsmParser::getMandatoryLitLoc(const OperandVector &Operands) const {	0
7130	auto Test = [](const AMDGPUOperand &Op) {	0	7130	auto Test = [](const AMDGPUOperand &Op) {	0
7131	return Op.IsImmKindMandatoryLiteral();	0	7131	return Op.IsImmKindMandatoryLiteral();	0
7132	};	---	7132	};	---
7133	return getOperandLoc(Test, Operands);	0	7133	return getOperandLoc(Test, Operands);	0
7134	}	---	7134	}	---
7135		---	7135		---
7136	SMLoc	---	7136	SMLoc	---
7137	AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {	0	7137	AMDGPUAsmParser::getConstLoc(const OperandVector &Operands) const {	0
7138	auto Test = [](const AMDGPUOperand& Op) {	0	7138	auto Test = [](const AMDGPUOperand& Op) {	0
7139	return Op.isImmKindConst();	0	7139	return Op.isImmKindConst();	0
7140	};	---	7140	};	---
7141	return getOperandLoc(Test, Operands);	0	7141	return getOperandLoc(Test, Operands);	0
7142	}	---	7142	}	---
7143		---	7143		---
7144	//===----------------------------------------------------------------------===//	---	7144	//===----------------------------------------------------------------------===//	---
7145	// swizzle	---	7145	// swizzle	---
7146	//===----------------------------------------------------------------------===//	---	7146	//===----------------------------------------------------------------------===//	---
7147		---	7147		---
7148	LLVM_READNONE	---	7148	LLVM_READNONE	---
7149	static unsigned	---	7149	static unsigned	---
7150	encodeBitmaskPerm(const unsigned AndMask,	0	7150	encodeBitmaskPerm(const unsigned AndMask,	0
7151	const unsigned OrMask,	---	7151	const unsigned OrMask,	---
7152	const unsigned XorMask) {	---	7152	const unsigned XorMask) {	---
7153	using namespace llvm::AMDGPU::Swizzle;	---	7153	using namespace llvm::AMDGPU::Swizzle;	---
7154		---	7154		---
7155	return BITMASK_PERM_ENC \|	---	7155	return BITMASK_PERM_ENC \|	---
7156	(AndMask << BITMASK_AND_SHIFT) \|	0	7156	(AndMask << BITMASK_AND_SHIFT) \|	0
7157	(OrMask << BITMASK_OR_SHIFT) \|	0	7157	(OrMask << BITMASK_OR_SHIFT) \|	0
7158	(XorMask << BITMASK_XOR_SHIFT);	0	7158	(XorMask << BITMASK_XOR_SHIFT);	0
7159	}	---	7159	}	---
7160		---	7160		---
7161	bool	---	7161	bool	---
7162	AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,	0	7162	AMDGPUAsmParser::parseSwizzleOperand(int64_t &Op,	0
7163	const unsigned MinVal,	---	7163	const unsigned MinVal,	---
7164	const unsigned MaxVal,	---	7164	const unsigned MaxVal,	---
7165	const StringRef ErrMsg,	---	7165	const StringRef ErrMsg,	---
7166	SMLoc &Loc) {	---	7166	SMLoc &Loc) {	---
7167	if (!skipToken(AsmToken::Comma, "expected a comma")) {	0	7167	if (!skipToken(AsmToken::Comma, "expected a comma")) {	0
7168	return false;	0	7168	return false;	0
7169	}	---	7169	}	---
7170	Loc = getLoc();	0	7170	Loc = getLoc();	0
7171	if (!parseExpr(Op)) {	0	7171	if (!parseExpr(Op)) {	0
7172	return false;	0	7172	return false;	0
7173	}	---	7173	}	---
7174	if (Op < MinVal \|\| Op > MaxVal) {	0	7174	if (Op < MinVal \|\| Op > MaxVal) {	0
7175	Error(Loc, ErrMsg);	0	7175	Error(Loc, ErrMsg);	0
7176	return false;	0	7176	return false;	0
7177	}	---	7177	}	---
7178		---	7178		---
7179	return true;	0	7179	return true;	0
7180	}	---	7180	}	---
7181		---	7181		---
7182	bool	---	7182	bool	---
7183	AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	0	7183	AMDGPUAsmParser::parseSwizzleOperands(const unsigned OpNum, int64_t* Op,	0
7184	const unsigned MinVal,	---	7184	const unsigned MinVal,	---
7185	const unsigned MaxVal,	---	7185	const unsigned MaxVal,	---
7186	const StringRef ErrMsg) {	---	7186	const StringRef ErrMsg) {	---
7187	SMLoc Loc;	0	7187	SMLoc Loc;	0
7188	for (unsigned i = 0; i < OpNum; ++i) {	0	7188	for (unsigned i = 0; i < OpNum; ++i) {	0
7189	if (!parseSwizzleOperand(Op[i], MinVal, MaxVal, ErrMsg, Loc))	0	7189	if (!parseSwizzleOperand(Op[i], MinVal, MaxVal, ErrMsg, Loc))	0
7190	return false;	0	7190	return false;	0
7191	}	---	7191	}	---
7192		---	7192		---
7193	return true;	0	7193	return true;	0
7194	}	---	7194	}	---
7195		---	7195		---
7196	bool	---	7196	bool	---
7197	AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {	0	7197	AMDGPUAsmParser::parseSwizzleQuadPerm(int64_t &Imm) {	0
7198	using namespace llvm::AMDGPU::Swizzle;	---	7198	using namespace llvm::AMDGPU::Swizzle;	---
7199		---	7199		---
7200	int64_t Lane[LANE_NUM];	---	7200	int64_t Lane[LANE_NUM];	---
7201	if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,	0	7201	if (parseSwizzleOperands(LANE_NUM, Lane, 0, LANE_MAX,	0
7202	"expected a 2-bit lane id")) {	---	7202	"expected a 2-bit lane id")) {	---
7203	Imm = QUAD_PERM_ENC;	0	7203	Imm = QUAD_PERM_ENC;	0
7204	for (unsigned I = 0; I < LANE_NUM; ++I) {	0	7204	for (unsigned I = 0; I < LANE_NUM; ++I) {	0
7205	Imm \|= Lane[I] << (LANE_SHIFT * I);	0	7205	Imm \|= Lane[I] << (LANE_SHIFT * I);	0
7206	}	---	7206	}	---
7207	return true;	0	7207	return true;	0
7208	}	---	7208	}	---
7209	return false;	0	7209	return false;	0
7210	}	---	7210	}	---
7211		---	7211		---
7212	bool	---	7212	bool	---
7213	AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {	0	7213	AMDGPUAsmParser::parseSwizzleBroadcast(int64_t &Imm) {	0
7214	using namespace llvm::AMDGPU::Swizzle;	---	7214	using namespace llvm::AMDGPU::Swizzle;	---
7215		---	7215		---
7216	SMLoc Loc;	0	7216	SMLoc Loc;	0
7217	int64_t GroupSize;	---	7217	int64_t GroupSize;	---
7218	int64_t LaneIdx;	---	7218	int64_t LaneIdx;	---
7219		---	7219		---
7220	if (!parseSwizzleOperand(GroupSize,	0	7220	if (!parseSwizzleOperand(GroupSize,	0
7221	2, 32,	---	7221	2, 32,	---
7222	"group size must be in the interval [2,32]",	---	7222	"group size must be in the interval [2,32]",	---
7223	Loc)) {	---	7223	Loc)) {	---
7224	return false;	0	7224	return false;	0
7225	}	---	7225	}	---
7226	if (!isPowerOf2_64(GroupSize)) {	0	7226	if (!isPowerOf2_64(GroupSize)) {	0
7227	Error(Loc, "group size must be a power of two");	0	7227	Error(Loc, "group size must be a power of two");	0
7228	return false;	0	7228	return false;	0
7229	}	---	7229	}	---
7230	if (parseSwizzleOperand(LaneIdx,	0	7230	if (parseSwizzleOperand(LaneIdx,	0
7231	0, GroupSize - 1,	---	7231	0, GroupSize - 1,	---
7232	"lane id must be in the interval [0,group size - 1]",	---	7232	"lane id must be in the interval [0,group size - 1]",	---
7233	Loc)) {	---	7233	Loc)) {	---
7234	Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);	0	7234	Imm = encodeBitmaskPerm(BITMASK_MAX - GroupSize + 1, LaneIdx, 0);	0
7235	return true;	0	7235	return true;	0
7236	}	---	7236	}	---
7237	return false;	0	7237	return false;	0
7238	}	---	7238	}	---
7239		---	7239		---
7240	bool	---	7240	bool	---
7241	AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {	0	7241	AMDGPUAsmParser::parseSwizzleReverse(int64_t &Imm) {	0
7242	using namespace llvm::AMDGPU::Swizzle;	---	7242	using namespace llvm::AMDGPU::Swizzle;	---
7243		---	7243		---
7244	SMLoc Loc;	0	7244	SMLoc Loc;	0
7245	int64_t GroupSize;	---	7245	int64_t GroupSize;	---
7246		---	7246		---
7247	if (!parseSwizzleOperand(GroupSize,	0	7247	if (!parseSwizzleOperand(GroupSize,	0
7248	2, 32,	---	7248	2, 32,	---
7249	"group size must be in the interval [2,32]",	---	7249	"group size must be in the interval [2,32]",	---
7250	Loc)) {	---	7250	Loc)) {	---
7251	return false;	0	7251	return false;	0
7252	}	---	7252	}	---
7253	if (!isPowerOf2_64(GroupSize)) {	0	7253	if (!isPowerOf2_64(GroupSize)) {	0
7254	Error(Loc, "group size must be a power of two");	0	7254	Error(Loc, "group size must be a power of two");	0
7255	return false;	0	7255	return false;	0
7256	}	---	7256	}	---
7257		---	7257		---
7258	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);	0	7258	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize - 1);	0
7259	return true;	0	7259	return true;	0
7260	}	---	7260	}	---
7261		---	7261		---
7262	bool	---	7262	bool	---
7263	AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {	0	7263	AMDGPUAsmParser::parseSwizzleSwap(int64_t &Imm) {	0
7264	using namespace llvm::AMDGPU::Swizzle;	---	7264	using namespace llvm::AMDGPU::Swizzle;	---
7265		---	7265		---
7266	SMLoc Loc;	0	7266	SMLoc Loc;	0
7267	int64_t GroupSize;	---	7267	int64_t GroupSize;	---
7268		---	7268		---
7269	if (!parseSwizzleOperand(GroupSize,	0	7269	if (!parseSwizzleOperand(GroupSize,	0
7270	1, 16,	---	7270	1, 16,	---
7271	"group size must be in the interval [1,16]",	---	7271	"group size must be in the interval [1,16]",	---
7272	Loc)) {	---	7272	Loc)) {	---
7273	return false;	0	7273	return false;	0
7274	}	---	7274	}	---
7275	if (!isPowerOf2_64(GroupSize)) {	0	7275	if (!isPowerOf2_64(GroupSize)) {	0
7276	Error(Loc, "group size must be a power of two");	0	7276	Error(Loc, "group size must be a power of two");	0
7277	return false;	0	7277	return false;	0
7278	}	---	7278	}	---
7279		---	7279		---
7280	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize);	0	7280	Imm = encodeBitmaskPerm(BITMASK_MAX, 0, GroupSize);	0
7281	return true;	0	7281	return true;	0
7282	}	---	7282	}	---
7283		---	7283		---
7284	bool	---	7284	bool	---
7285	AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {	0	7285	AMDGPUAsmParser::parseSwizzleBitmaskPerm(int64_t &Imm) {	0
7286	using namespace llvm::AMDGPU::Swizzle;	---	7286	using namespace llvm::AMDGPU::Swizzle;	---
7287		---	7287		---
7288	if (!skipToken(AsmToken::Comma, "expected a comma")) {	0	7288	if (!skipToken(AsmToken::Comma, "expected a comma")) {	0
7289	return false;	0	7289	return false;	0
7290	}	---	7290	}	---
7291		---	7291		---
7292	StringRef Ctl;	0	7292	StringRef Ctl;	0
7293	SMLoc StrLoc = getLoc();	0	7293	SMLoc StrLoc = getLoc();	0
7294	if (!parseString(Ctl)) {	0	7294	if (!parseString(Ctl)) {	0
7295	return false;	0	7295	return false;	0
7296	}	---	7296	}	---
7297	if (Ctl.size() != BITMASK_WIDTH) {	0	7297	if (Ctl.size() != BITMASK_WIDTH) {	0
7298	Error(StrLoc, "expected a 5-character mask");	0	7298	Error(StrLoc, "expected a 5-character mask");	0
7299	return false;	0	7299	return false;	0
7300	}	---	7300	}	---
7301		---	7301		---
7302	unsigned AndMask = 0;	0	7302	unsigned AndMask = 0;	0
7303	unsigned OrMask = 0;	0	7303	unsigned OrMask = 0;	0
7304	unsigned XorMask = 0;	0	7304	unsigned XorMask = 0;	0
7305		---	7305		---
7306	for (size_t i = 0; i < Ctl.size(); ++i) {	0	7306	for (size_t i = 0; i < Ctl.size(); ++i) {	0
7307	unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);	0	7307	unsigned Mask = 1 << (BITMASK_WIDTH - 1 - i);	0
7308	switch(Ctl[i]) {	0	7308	switch(Ctl[i]) {	0
7309	default:	0	7309	default:	0
7310	Error(StrLoc, "invalid mask");	0	7310	Error(StrLoc, "invalid mask");	0
7311	return false;	0	7311	return false;	0
7312	case '0':	0	7312	case '0':	0
7313	break;	0	7313	break;	0
7314	case '1':	0	7314	case '1':	0
7315	OrMask \|= Mask;	0	7315	OrMask \|= Mask;	0
7316	break;	0	7316	break;	0
7317	case 'p':	0	7317	case 'p':	0
7318	AndMask \|= Mask;	0	7318	AndMask \|= Mask;	0
7319	break;	0	7319	break;	0
7320	case 'i':	0	7320	case 'i':	0
7321	AndMask \|= Mask;	0	7321	AndMask \|= Mask;	0
7322	XorMask \|= Mask;	0	7322	XorMask \|= Mask;	0
7323	break;	0	7323	break;	0
7324	}	---	7324	}	---
7325	}	---	7325	}	---
7326		---	7326		---
7327	Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask);	0	7327	Imm = encodeBitmaskPerm(AndMask, OrMask, XorMask);	0
7328	return true;	0	7328	return true;	0
7329	}	---	7329	}	---
7330		---	7330		---
7331	bool	---	7331	bool	---
7332	AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {	0	7332	AMDGPUAsmParser::parseSwizzleOffset(int64_t &Imm) {	0
7333		---	7333		---
7334	SMLoc OffsetLoc = getLoc();	0	7334	SMLoc OffsetLoc = getLoc();	0
7335		---	7335		---
7336	if (!parseExpr(Imm, "a swizzle macro")) {	0	7336	if (!parseExpr(Imm, "a swizzle macro")) {	0
7337	return false;	0	7337	return false;	0
7338	}	---	7338	}	---
7339	if (!isUInt<16>(Imm)) {	0	7339	if (!isUInt<16>(Imm)) {	0
7340	Error(OffsetLoc, "expected a 16-bit offset");	0	7340	Error(OffsetLoc, "expected a 16-bit offset");	0
7341	return false;	0	7341	return false;	0
7342	}	---	7342	}	---
7343	return true;	0	7343	return true;	0
7344	}	---	7344	}	---
7345		---	7345		---
7346	bool	---	7346	bool	---
7347	AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {	0	7347	AMDGPUAsmParser::parseSwizzleMacro(int64_t &Imm) {	0
7348	using namespace llvm::AMDGPU::Swizzle;	---	7348	using namespace llvm::AMDGPU::Swizzle;	---
7349		---	7349		---
7350	if (skipToken(AsmToken::LParen, "expected a left parentheses")) {	0	7350	if (skipToken(AsmToken::LParen, "expected a left parentheses")) {	0
7351		---	7351		---
7352	SMLoc ModeLoc = getLoc();	0	7352	SMLoc ModeLoc = getLoc();	0
7353	bool Ok = false;	0	7353	bool Ok = false;	0
7354		---	7354		---
7355	if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {	0	7355	if (trySkipId(IdSymbolic[ID_QUAD_PERM])) {	0
7356	Ok = parseSwizzleQuadPerm(Imm);	0	7356	Ok = parseSwizzleQuadPerm(Imm);	0
7357	} else if (trySkipId(IdSymbolic[ID_BITMASK_PERM])) {	0	7357	} else if (trySkipId(IdSymbolic[ID_BITMASK_PERM])) {	0
7358	Ok = parseSwizzleBitmaskPerm(Imm);	0	7358	Ok = parseSwizzleBitmaskPerm(Imm);	0
7359	} else if (trySkipId(IdSymbolic[ID_BROADCAST])) {	0	7359	} else if (trySkipId(IdSymbolic[ID_BROADCAST])) {	0
7360	Ok = parseSwizzleBroadcast(Imm);	0	7360	Ok = parseSwizzleBroadcast(Imm);	0
7361	} else if (trySkipId(IdSymbolic[ID_SWAP])) {	0	7361	} else if (trySkipId(IdSymbolic[ID_SWAP])) {	0
7362	Ok = parseSwizzleSwap(Imm);	0	7362	Ok = parseSwizzleSwap(Imm);	0
7363	} else if (trySkipId(IdSymbolic[ID_REVERSE])) {	0	7363	} else if (trySkipId(IdSymbolic[ID_REVERSE])) {	0
7364	Ok = parseSwizzleReverse(Imm);	0	7364	Ok = parseSwizzleReverse(Imm);	0
7365	} else {	---	7365	} else {	---
7366	Error(ModeLoc, "expected a swizzle mode");	0	7366	Error(ModeLoc, "expected a swizzle mode");	0
7367	}	---	7367	}	---
7368		---	7368		---
7369	return Ok && skipToken(AsmToken::RParen, "expected a closing parentheses");	0	7369	return Ok && skipToken(AsmToken::RParen, "expected a closing parentheses");	0
7370	}	---	7370	}	---
7371		---	7371		---
7372	return false;	0	7372	return false;	0
7373	}	---	7373	}	---
7374		---	7374		---
7375	ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {	0	7375	ParseStatus AMDGPUAsmParser::parseSwizzle(OperandVector &Operands) {	0
7376	SMLoc S = getLoc();	0	7376	SMLoc S = getLoc();	0
7377	int64_t Imm = 0;	0	7377	int64_t Imm = 0;	0
7378		---	7378		---
7379	if (trySkipId("offset")) {	0	7379	if (trySkipId("offset")) {	0
7380		---	7380		---
7381	bool Ok = false;	0	7381	bool Ok = false;	0
7382	if (skipToken(AsmToken::Colon, "expected a colon")) {	0	7382	if (skipToken(AsmToken::Colon, "expected a colon")) {	0
7383	if (trySkipId("swizzle")) {	0	7383	if (trySkipId("swizzle")) {	0
7384	Ok = parseSwizzleMacro(Imm);	0	7384	Ok = parseSwizzleMacro(Imm);	0
7385	} else {	---	7385	} else {	---
7386	Ok = parseSwizzleOffset(Imm);	0	7386	Ok = parseSwizzleOffset(Imm);	0
7387	}	---	7387	}	---
7388	}	---	7388	}	---
7389		---	7389		---
7390	Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));	0	7390	Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));	0
7391		---	7391		---
7392	return Ok ? ParseStatus::Success : ParseStatus::Failure;	0	7392	return Ok ? ParseStatus::Success : ParseStatus::Failure;	0
7393	}	---	7393	}	---
7394	return ParseStatus::NoMatch;	0	7394	return ParseStatus::NoMatch;	0
7395	}	---	7395	}	---
7396		---	7396		---
7397	bool	---	7397	bool	---
7398	AMDGPUOperand::isSwizzle() const {	0	7398	AMDGPUOperand::isSwizzle() const {	0
7399	return isImmTy(ImmTySwizzle);	0	7399	return isImmTy(ImmTySwizzle);	0
7400	}	---	7400	}	---
7401		---	7401		---
7402	//===----------------------------------------------------------------------===//	---	7402	//===----------------------------------------------------------------------===//	---
7403	// VGPR Index Mode	---	7403	// VGPR Index Mode	---
7404	//===----------------------------------------------------------------------===//	---	7404	//===----------------------------------------------------------------------===//	---
7405		---	7405		---
7406	int64_t AMDGPUAsmParser::parseGPRIdxMacro() {	0	7406	int64_t AMDGPUAsmParser::parseGPRIdxMacro() {	0
7407		---	7407		---
7408	using namespace llvm::AMDGPU::VGPRIndexMode;	---	7408	using namespace llvm::AMDGPU::VGPRIndexMode;	---
7409		---	7409		---
7410	if (trySkipToken(AsmToken::RParen)) {	0	7410	if (trySkipToken(AsmToken::RParen)) {	0
7411	return OFF;	0	7411	return OFF;	0
7412	}	---	7412	}	---
7413		---	7413		---
7414	int64_t Imm = 0;	0	7414	int64_t Imm = 0;	0
7415		---	7415		---
7416	while (true) {	---	7416	while (true) {	---
7417	unsigned Mode = 0;	0	7417	unsigned Mode = 0;	0
7418	SMLoc S = getLoc();	0	7418	SMLoc S = getLoc();	0
7419		---	7419		---
7420	for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {	0	7420	for (unsigned ModeId = ID_MIN; ModeId <= ID_MAX; ++ModeId) {	0
7421	if (trySkipId(IdSymbolic[ModeId])) {	0	7421	if (trySkipId(IdSymbolic[ModeId])) {	0
7422	Mode = 1 << ModeId;	0	7422	Mode = 1 << ModeId;	0
7423	break;	0	7423	break;	0
7424	}	---	7424	}	---
7425	}	---	7425	}	---
7426		---	7426		---
7427	if (Mode == 0) {	0	7427	if (Mode == 0) {	0
7428	Error(S, (Imm == 0)?	0	7428	Error(S, (Imm == 0)?	0
7429	"expected a VGPR index mode or a closing parenthesis" :	---	7429	"expected a VGPR index mode or a closing parenthesis" :	---
7430	"expected a VGPR index mode");	---	7430	"expected a VGPR index mode");	---
7431	return UNDEF;	0	7431	return UNDEF;	0
7432	}	---	7432	}	---
7433		---	7433		---
7434	if (Imm & Mode) {	0	7434	if (Imm & Mode) {	0
7435	Error(S, "duplicate VGPR index mode");	0	7435	Error(S, "duplicate VGPR index mode");	0
7436	return UNDEF;	0	7436	return UNDEF;	0
7437	}	---	7437	}	---
7438	Imm \|= Mode;	0	7438	Imm \|= Mode;	0
7439		---	7439		---
7440	if (trySkipToken(AsmToken::RParen))	0	7440	if (trySkipToken(AsmToken::RParen))	0
7441	break;	0	7441	break;	0
7442	if (!skipToken(AsmToken::Comma,	0	7442	if (!skipToken(AsmToken::Comma,	0
7443	"expected a comma or a closing parenthesis"))	---	7443	"expected a comma or a closing parenthesis"))	---
7444	return UNDEF;	0	7444	return UNDEF;	0
7445	}	0	7445	}	0
7446		---	7446		---
7447	return Imm;	0	7447	return Imm;	0
7448	}	---	7448	}	---
7449		---	7449		---
7450	ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {	0	7450	ParseStatus AMDGPUAsmParser::parseGPRIdxMode(OperandVector &Operands) {	0
7451		---	7451		---
7452	using namespace llvm::AMDGPU::VGPRIndexMode;	---	7452	using namespace llvm::AMDGPU::VGPRIndexMode;	---
7453		---	7453		---
7454	int64_t Imm = 0;	0	7454	int64_t Imm = 0;	0
7455	SMLoc S = getLoc();	0	7455	SMLoc S = getLoc();	0
7456		---	7456		---
7457	if (trySkipId("gpr_idx", AsmToken::LParen)) {	0	7457	if (trySkipId("gpr_idx", AsmToken::LParen)) {	0
7458	Imm = parseGPRIdxMacro();	0	7458	Imm = parseGPRIdxMacro();	0
7459	if (Imm == UNDEF)	0	7459	if (Imm == UNDEF)	0
7460	return ParseStatus::Failure;	0	7460	return ParseStatus::Failure;	0
7461	} else {	---	7461	} else {	---
7462	if (getParser().parseAbsoluteExpression(Imm))	0	7462	if (getParser().parseAbsoluteExpression(Imm))	0
7463	return ParseStatus::Failure;	0	7463	return ParseStatus::Failure;	0
7464	if (Imm < 0 \|\| !isUInt<4>(Imm))	0	7464	if (Imm < 0 \|\| !isUInt<4>(Imm))	0
7465	return Error(S, "invalid immediate: only 4-bit values are legal");	0	7465	return Error(S, "invalid immediate: only 4-bit values are legal");	0
7466	}	---	7466	}	---
7467		---	7467		---
7468	Operands.push_back(	0	7468	Operands.push_back(	0
7469	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode));	0	7469	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyGprIdxMode));	0
7470	return ParseStatus::Success;	0	7470	return ParseStatus::Success;	0
7471	}	---	7471	}	---
7472		---	7472		---
7473	bool AMDGPUOperand::isGPRIdxMode() const {	0	7473	bool AMDGPUOperand::isGPRIdxMode() const {	0
7474	return isImmTy(ImmTyGprIdxMode);	0	7474	return isImmTy(ImmTyGprIdxMode);	0
7475	}	---	7475	}	---
7476		---	7476		---
7477	//===----------------------------------------------------------------------===//	---	7477	//===----------------------------------------------------------------------===//	---
7478	// sopp branch targets	---	7478	// sopp branch targets	---
7479	//===----------------------------------------------------------------------===//	---	7479	//===----------------------------------------------------------------------===//	---
7480		---	7480		---
7481	ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {	0	7481	ParseStatus AMDGPUAsmParser::parseSOPPBrTarget(OperandVector &Operands) {	0
7482		---	7482		---
7483	// Make sure we are not parsing something	---	7483	// Make sure we are not parsing something	---
7484	// that looks like a label or an expression but is not.	---	7484	// that looks like a label or an expression but is not.	---
7485	// This will improve error messages.	---	7485	// This will improve error messages.	---
7486	if (isRegister() \|\| isModifier())	0	7486	if (isRegister() \|\| isModifier())	0
7487	return ParseStatus::NoMatch;	0	7487	return ParseStatus::NoMatch;	0
7488		---	7488		---
7489	if (!parseExpr(Operands))	0	7489	if (!parseExpr(Operands))	0
7490	return ParseStatus::Failure;	0	7490	return ParseStatus::Failure;	0
7491		---	7491		---
7492	AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);	0	7492	AMDGPUOperand &Opr = ((AMDGPUOperand &)*Operands[Operands.size() - 1]);	0
7493	assert(Opr.isImm() \|\| Opr.isExpr());	0	7493	assert(Opr.isImm() \|\| Opr.isExpr());	0
7494	SMLoc Loc = Opr.getStartLoc();	0	7494	SMLoc Loc = Opr.getStartLoc();	0
7495		---	7495		---
7496	// Currently we do not support arbitrary expressions as branch targets.	---	7496	// Currently we do not support arbitrary expressions as branch targets.	---
7497	// Only labels and absolute expressions are accepted.	---	7497	// Only labels and absolute expressions are accepted.	---
7498	if (Opr.isExpr() && !Opr.isSymbolRefExpr()) {	0	7498	if (Opr.isExpr() && !Opr.isSymbolRefExpr()) {	0
7499	Error(Loc, "expected an absolute expression or a label");	0	7499	Error(Loc, "expected an absolute expression or a label");	0
7500	} else if (Opr.isImm() && !Opr.isS16Imm()) {	0	7500	} else if (Opr.isImm() && !Opr.isS16Imm()) {	0
7501	Error(Loc, "expected a 16-bit signed jump offset");	0	7501	Error(Loc, "expected a 16-bit signed jump offset");	0
7502	}	---	7502	}	---
7503		---	7503		---
7504	return ParseStatus::Success;	0	7504	return ParseStatus::Success;	0
7505	}	---	7505	}	---
7506		---	7506		---
7507	//===----------------------------------------------------------------------===//	---	7507	//===----------------------------------------------------------------------===//	---
7508	// Boolean holding registers	---	7508	// Boolean holding registers	---
7509	//===----------------------------------------------------------------------===//	---	7509	//===----------------------------------------------------------------------===//	---
7510		---	7510		---
7511	ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {	0	7511	ParseStatus AMDGPUAsmParser::parseBoolReg(OperandVector &Operands) {	0
7512	return parseReg(Operands);	0	7512	return parseReg(Operands);	0
7513	}	---	7513	}	---
7514		---	7514		---
7515	//===----------------------------------------------------------------------===//	---	7515	//===----------------------------------------------------------------------===//	---
7516	// mubuf	---	7516	// mubuf	---
7517	//===----------------------------------------------------------------------===//	---	7517	//===----------------------------------------------------------------------===//	---
7518		---	7518		---
7519	void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,	0	7519	void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,	0
7520	const OperandVector &Operands,	---	7520	const OperandVector &Operands,	---
7521	bool IsAtomic) {	---	7521	bool IsAtomic) {	---
7522	OptionalImmIndexMap OptionalIdx;	0	7522	OptionalImmIndexMap OptionalIdx;	0
7523	unsigned FirstOperandIdx = 1;	0	7523	unsigned FirstOperandIdx = 1;	0
7524	bool IsAtomicReturn = false;	0	7524	bool IsAtomicReturn = false;	0
7525		---	7525		---
7526	if (IsAtomic) {	0	7526	if (IsAtomic) {	0
7527	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	0	7527	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	0
7528	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	7528	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7529	if (!Op.isCPol())	0	7529	if (!Op.isCPol())	0
7530	continue;	0	7530	continue;	0
7531	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	0	7531	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	0
7532	break;	0	7532	break;	0
7533	}	---	7533	}	---
7534		---	7534		---
7535	if (!IsAtomicReturn) {	0	7535	if (!IsAtomicReturn) {	0
7536	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	0	7536	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	0
7537	if (NewOpc != -1)	0	7537	if (NewOpc != -1)	0
7538	Inst.setOpcode(NewOpc);	0	7538	Inst.setOpcode(NewOpc);	0
7539	}	---	7539	}	---
7540		---	7540		---
7541	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	0	7541	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	0
7542	SIInstrFlags::IsAtomicRet;	---	7542	SIInstrFlags::IsAtomicRet;	---
7543	}	---	7543	}	---
7544		---	7544		---
7545	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	0	7545	for (unsigned i = FirstOperandIdx, e = Operands.size(); i != e; ++i) {	0
7546	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	7546	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7547		---	7547		---
7548	// Add the register arguments	---	7548	// Add the register arguments	---
7549	if (Op.isReg()) {	0	7549	if (Op.isReg()) {	0
7550	Op.addRegOperands(Inst, 1);	0	7550	Op.addRegOperands(Inst, 1);	0
7551	// Insert a tied src for atomic return dst.	---	7551	// Insert a tied src for atomic return dst.	---
7552	// This cannot be postponed as subsequent calls to	---	7552	// This cannot be postponed as subsequent calls to	---
7553	// addImmOperands rely on correct number of MC operands.	---	7553	// addImmOperands rely on correct number of MC operands.	---
7554	if (IsAtomicReturn && i == FirstOperandIdx)	0	7554	if (IsAtomicReturn && i == FirstOperandIdx)	0
7555	Op.addRegOperands(Inst, 1);	0	7555	Op.addRegOperands(Inst, 1);	0
7556	continue;	0	7556	continue;	0
7557	}	---	7557	}	---
7558		---	7558		---
7559	// Handle the case where soffset is an immediate	---	7559	// Handle the case where soffset is an immediate	---
7560	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	0	7560	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	0
7561	Op.addImmOperands(Inst, 1);	0	7561	Op.addImmOperands(Inst, 1);	0
7562	continue;	0	7562	continue;	0
7563	}	---	7563	}	---
7564		---	7564		---
7565	// Handle tokens like 'offen' which are sometimes hard-coded into the	---	7565	// Handle tokens like 'offen' which are sometimes hard-coded into the	---
7566	// asm string. There are no MCInst operands for these.	---	7566	// asm string. There are no MCInst operands for these.	---
7567	if (Op.isToken()) {	0	7567	if (Op.isToken()) {	0
7568	continue;	0	7568	continue;	0
7569	}	---	7569	}	---
7570	assert(Op.isImm());	0	7570	assert(Op.isImm());	0
7571		---	7571		---
7572	// Handle optional arguments	---	7572	// Handle optional arguments	---
7573	OptionalIdx[Op.getImmTy()] = i;	0	7573	OptionalIdx[Op.getImmTy()] = i;	0
7574	}	---	7574	}	---
7575		---	7575		---
7576	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);	0	7576	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset);	0
7577	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	0	7577	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	0
7578	}	0	7578	}	0
7579		---	7579		---
7580	//===----------------------------------------------------------------------===//	---	7580	//===----------------------------------------------------------------------===//	---
7581	// SMEM	---	7581	// SMEM	---
7582	//===----------------------------------------------------------------------===//	---	7582	//===----------------------------------------------------------------------===//	---
7583		---	7583		---
7584	void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {	0	7584	void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {	0
7585	OptionalImmIndexMap OptionalIdx;	0	7585	OptionalImmIndexMap OptionalIdx;	0
7586	bool IsAtomicReturn = false;	0	7586	bool IsAtomicReturn = false;	0
7587		---	7587		---
7588	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0	7588	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
7589	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	7589	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7590	if (!Op.isCPol())	0	7590	if (!Op.isCPol())	0
7591	continue;	0	7591	continue;	0
7592	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	0	7592	IsAtomicReturn = Op.getImm() & AMDGPU::CPol::GLC;	0
7593	break;	0	7593	break;	0
7594	}	---	7594	}	---
7595		---	7595		---
7596	if (!IsAtomicReturn) {	0	7596	if (!IsAtomicReturn) {	0
7597	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	0	7597	int NewOpc = AMDGPU::getAtomicNoRetOp(Inst.getOpcode());	0
7598	if (NewOpc != -1)	0	7598	if (NewOpc != -1)	0
7599	Inst.setOpcode(NewOpc);	0	7599	Inst.setOpcode(NewOpc);	0
7600	}	---	7600	}	---
7601		---	7601		---
7602	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	0	7602	IsAtomicReturn = MII.get(Inst.getOpcode()).TSFlags &	0
7603	SIInstrFlags::IsAtomicRet;	---	7603	SIInstrFlags::IsAtomicRet;	---
7604		---	7604		---
7605	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0	7605	for (unsigned i = 1, e = Operands.size(); i != e; ++i) {	0
7606	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0	7606	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);	0
7607		---	7607		---
7608	// Add the register arguments	---	7608	// Add the register arguments	---
7609	if (Op.isReg()) {	0	7609	if (Op.isReg()) {	0
7610	Op.addRegOperands(Inst, 1);	0	7610	Op.addRegOperands(Inst, 1);	0
7611	if (IsAtomicReturn && i == 1)	0	7611	if (IsAtomicReturn && i == 1)	0
7612	Op.addRegOperands(Inst, 1);	0	7612	Op.addRegOperands(Inst, 1);	0
7613	continue;	0	7613	continue;	0
7614	}	---	7614	}	---
7615		---	7615		---
7616	// Handle the case where soffset is an immediate	---	7616	// Handle the case where soffset is an immediate	---
7617	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	0	7617	if (Op.isImm() && Op.getImmTy() == AMDGPUOperand::ImmTyNone) {	0
7618	Op.addImmOperands(Inst, 1);	0	7618	Op.addImmOperands(Inst, 1);	0
7619	continue;	0	7619	continue;	0
7620	}	---	7620	}	---
7621		---	7621		---
7622	// Handle tokens like 'offen' which are sometimes hard-coded into the	---	7622	// Handle tokens like 'offen' which are sometimes hard-coded into the	---
7623	// asm string. There are no MCInst operands for these.	---	7623	// asm string. There are no MCInst operands for these.	---
7624	if (Op.isToken()) {	0	7624	if (Op.isToken()) {	0
7625	continue;	0	7625	continue;	0
7626	}	---	7626	}	---
7627	assert(Op.isImm());	0	7627	assert(Op.isImm());	0
7628		---	7628		---
7629	// Handle optional arguments	---	7629	// Handle optional arguments	---
7630	OptionalIdx[Op.getImmTy()] = i;	0	7630	OptionalIdx[Op.getImmTy()] = i;	0
7631	}	---	7631	}	---
7632		---	7632		---
7633	if ((int)Inst.getNumOperands() <=	0	7633	if ((int)Inst.getNumOperands() <=	0
7634	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset))	0	7634	AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::offset))	0
7635	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	7635	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7636	AMDGPUOperand::ImmTySMEMOffsetMod);	---	7636	AMDGPUOperand::ImmTySMEMOffsetMod);	---
7637	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	0	7637	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol, 0);	0
7638	}	0	7638	}	0
7639		---	7639		---
7640	//===----------------------------------------------------------------------===//	---	7640	//===----------------------------------------------------------------------===//	---
7641	// smrd	---	7641	// smrd	---
7642	//===----------------------------------------------------------------------===//	---	7642	//===----------------------------------------------------------------------===//	---
7643		---	7643		---
7644	bool AMDGPUOperand::isSMRDOffset8() const {	0	7644	bool AMDGPUOperand::isSMRDOffset8() const {	0
7645	return isImmLiteral() && isUInt<8>(getImm());	0	7645	return isImmLiteral() && isUInt<8>(getImm());	0
7646	}	---	7646	}	---
7647		---	7647		---
7648	bool AMDGPUOperand::isSMEMOffset() const {	0	7648	bool AMDGPUOperand::isSMEMOffset() const {	0
7649	// Offset range is checked later by validator.	---	7649	// Offset range is checked later by validator.	---
7650	return isImmLiteral();	0	7650	return isImmLiteral();	0
7651	}	---	7651	}	---
7652		---	7652		---
7653	bool AMDGPUOperand::isSMRDLiteralOffset() const {	0	7653	bool AMDGPUOperand::isSMRDLiteralOffset() const {	0
7654	// 32-bit literals are only supported on CI and we only want to use them	---	7654	// 32-bit literals are only supported on CI and we only want to use them	---
7655	// when the offset is > 8-bits.	---	7655	// when the offset is > 8-bits.	---
7656	return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());	0	7656	return isImmLiteral() && !isUInt<8>(getImm()) && isUInt<32>(getImm());	0
7657	}	---	7657	}	---
7658		---	7658		---
7659	//===----------------------------------------------------------------------===//	---	7659	//===----------------------------------------------------------------------===//	---
7660	// vop3	---	7660	// vop3	---
7661	//===----------------------------------------------------------------------===//	---	7661	//===----------------------------------------------------------------------===//	---
7662		---	7662		---
7663	static bool ConvertOmodMul(int64_t &Mul) {	0	7663	static bool ConvertOmodMul(int64_t &Mul) {	0
7664	if (Mul != 1 && Mul != 2 && Mul != 4)	0	7664	if (Mul != 1 && Mul != 2 && Mul != 4)	0
7665	return false;	0	7665	return false;	0
7666		---	7666		---
7667	Mul >>= 1;	0	7667	Mul >>= 1;	0
7668	return true;	0	7668	return true;	0
7669	}	---	7669	}	---
7670		---	7670		---
7671	static bool ConvertOmodDiv(int64_t &Div) {	0	7671	static bool ConvertOmodDiv(int64_t &Div) {	0
7672	if (Div == 1) {	0	7672	if (Div == 1) {	0
7673	Div = 0;	0	7673	Div = 0;	0
7674	return true;	0	7674	return true;	0
7675	}	---	7675	}	---
7676		---	7676		---
7677	if (Div == 2) {	0	7677	if (Div == 2) {	0
7678	Div = 3;	0	7678	Div = 3;	0
7679	return true;	0	7679	return true;	0
7680	}	---	7680	}	---
7681		---	7681		---
7682	return false;	0	7682	return false;	0
7683	}	---	7683	}	---
7684		---	7684		---
7685	// For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.	---	7685	// For pre-gfx11 targets, both bound_ctrl:0 and bound_ctrl:1 are encoded as 1.	---
7686	// This is intentional and ensures compatibility with sp3.	---	7686	// This is intentional and ensures compatibility with sp3.	---
7687	// See bug 35397 for details.	---	7687	// See bug 35397 for details.	---
7688	bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {	0	7688	bool AMDGPUAsmParser::convertDppBoundCtrl(int64_t &BoundCtrl) {	0
7689	if (BoundCtrl == 0 \|\| BoundCtrl == 1) {	0	7689	if (BoundCtrl == 0 \|\| BoundCtrl == 1) {	0
7690	if (!isGFX11Plus())	0	7690	if (!isGFX11Plus())	0
7691	BoundCtrl = 1;	0	7691	BoundCtrl = 1;	0
7692	return true;	0	7692	return true;	0
7693	}	---	7693	}	---
7694	return false;	0	7694	return false;	0
7695	}	---	7695	}	---
7696		---	7696		---
7697	void AMDGPUAsmParser::onBeginOfFile() {	0	7697	void AMDGPUAsmParser::onBeginOfFile() {	0
7698	if (!getParser().getStreamer().getTargetStreamer() \|\|	0	7698	if (!getParser().getStreamer().getTargetStreamer() \|\|	0
7699	getSTI().getTargetTriple().getArch() == Triple::r600)	0	7699	getSTI().getTargetTriple().getArch() == Triple::r600)	0
7700	return;	0	7700	return;	0
7701		---	7701		---
7702	if (!getTargetStreamer().getTargetID())	0	7702	if (!getTargetStreamer().getTargetID())	0
7703	getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(),	0	7703	getTargetStreamer().initializeTargetID(getSTI(), getSTI().getFeatureString(),	0
7704	// TODO: Should try to check code object version from directive???	---	7704	// TODO: Should try to check code object version from directive???	---
7705	AMDGPU::getAmdhsaCodeObjectVersion());	---	7705	AMDGPU::getAmdhsaCodeObjectVersion());	---
7706		---	7706		---
7707	if (isHsaAbiVersion3AndAbove(&getSTI()))	0	7707	if (isHsaAbiVersion3AndAbove(&getSTI()))	0
7708	getTargetStreamer().EmitDirectiveAMDGCNTarget();	0	7708	getTargetStreamer().EmitDirectiveAMDGCNTarget();	0
7709	}	---	7709	}	---
7710		---	7710		---
7711	ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {	0	7711	ParseStatus AMDGPUAsmParser::parseOModSI(OperandVector &Operands) {	0
7712	StringRef Name = getTokenStr();	0	7712	StringRef Name = getTokenStr();	0
7713	if (Name == "mul") {	0	7713	if (Name == "mul") {	0
7714	return parseIntWithPrefix("mul", Operands,	0	7714	return parseIntWithPrefix("mul", Operands,	0
7715	AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);	0	7715	AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);	0
7716	}	---	7716	}	---
7717		---	7717		---
7718	if (Name == "div") {	0	7718	if (Name == "div") {	0
7719	return parseIntWithPrefix("div", Operands,	0	7719	return parseIntWithPrefix("div", Operands,	0
7720	AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);	0	7720	AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);	0
7721	}	---	7721	}	---
7722		---	7722		---
7723	return ParseStatus::NoMatch;	0	7723	return ParseStatus::NoMatch;	0
7724	}	---	7724	}	---
7725		---	7725		---
7726	// Determines which bit DST_OP_SEL occupies in the op_sel operand according to	---	7726	// Determines which bit DST_OP_SEL occupies in the op_sel operand according to	---
7727	// the number of src operands present, then copies that bit into src0_modifiers.	---	7727	// the number of src operands present, then copies that bit into src0_modifiers.	---
7728	void cvtVOP3DstOpSelOnly(MCInst &Inst) {	0	7728	void cvtVOP3DstOpSelOnly(MCInst &Inst) {	0
7729	int Opc = Inst.getOpcode();	0	7729	int Opc = Inst.getOpcode();	0
7730	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0	7730	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
7731	if (OpSelIdx == -1)	0	7731	if (OpSelIdx == -1)	0
7732	return;	0	7732	return;	0
7733		---	7733		---
7734	int SrcNum;	---	7734	int SrcNum;	---
7735	const int Ops[] = { AMDGPU::OpName::src0,	0	7735	const int Ops[] = { AMDGPU::OpName::src0,	0
7736	AMDGPU::OpName::src1,	---	7736	AMDGPU::OpName::src1,	---
7737	AMDGPU::OpName::src2 };	---	7737	AMDGPU::OpName::src2 };	---
7738	for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);	0	7738	for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);	0
7739	++SrcNum)	---	7739	++SrcNum)	---
7740	;	---	7740	;	---
7741	assert(SrcNum > 0);	0	7741	assert(SrcNum > 0);	0
7742		---	7742		---
7743	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0	7743	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
7744		---	7744		---
7745	if ((OpSel & (1 << SrcNum)) != 0) {	0	7745	if ((OpSel & (1 << SrcNum)) != 0) {	0
7746	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);	0	7746	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);	0
7747	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	0	7747	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	0
7748	Inst.getOperand(ModIdx).setImm(ModVal \| SISrcMods::DST_OP_SEL);	0	7748	Inst.getOperand(ModIdx).setImm(ModVal \| SISrcMods::DST_OP_SEL);	0
7749	}	---	7749	}	---
7750	}	---	7750	}	---
7751		---	7751		---
7752	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,	0	7752	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst,	0
7753	const OperandVector &Operands) {	---	7753	const OperandVector &Operands) {	---
7754	cvtVOP3P(Inst, Operands);	0	7754	cvtVOP3P(Inst, Operands);	0
7755	cvtVOP3DstOpSelOnly(Inst);	0	7755	cvtVOP3DstOpSelOnly(Inst);	0
7756	}	0	7756	}	0
7757		---	7757		---
7758	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	0	7758	void AMDGPUAsmParser::cvtVOP3OpSel(MCInst &Inst, const OperandVector &Operands,	0
7759	OptionalImmIndexMap &OptionalIdx) {	---	7759	OptionalImmIndexMap &OptionalIdx) {	---
7760	cvtVOP3P(Inst, Operands, OptionalIdx);	0	7760	cvtVOP3P(Inst, Operands, OptionalIdx);	0
7761	cvtVOP3DstOpSelOnly(Inst);	0	7761	cvtVOP3DstOpSelOnly(Inst);	0
7762	}	0	7762	}	0
7763		---	7763		---
7764	static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {	0	7764	static bool isRegOrImmWithInputMods(const MCInstrDesc &Desc, unsigned OpNum) {	0
7765	return	---	7765	return	---
7766	// 1. This operand is input modifiers	---	7766	// 1. This operand is input modifiers	---
7767	Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS	0	7767	Desc.operands()[OpNum].OperandType == AMDGPU::OPERAND_INPUT_MODS	0
7768	// 2. This is not last operand	---	7768	// 2. This is not last operand	---
7769	&& Desc.NumOperands > (OpNum + 1)	0	7769	&& Desc.NumOperands > (OpNum + 1)	0
7770	// 3. Next operand is register class	---	7770	// 3. Next operand is register class	---
7771	&& Desc.operands()[OpNum + 1].RegClass != -1	0	7771	&& Desc.operands()[OpNum + 1].RegClass != -1	0
7772	// 4. Next register is not tied to any other operand	---	7772	// 4. Next register is not tied to any other operand	---
7773	&& Desc.getOperandConstraint(OpNum + 1,	0	7773	&& Desc.getOperandConstraint(OpNum + 1,	0
7774	MCOI::OperandConstraint::TIED_TO) == -1;	0	7774	MCOI::OperandConstraint::TIED_TO) == -1;	0
7775	}	---	7775	}	---
7776		---	7776		---
7777	void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)	0	7777	void AMDGPUAsmParser::cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands)	0
7778	{	---	7778	{	---
7779	OptionalImmIndexMap OptionalIdx;	0	7779	OptionalImmIndexMap OptionalIdx;	0
7780	unsigned Opc = Inst.getOpcode();	0	7780	unsigned Opc = Inst.getOpcode();	0
7781		---	7781		---
7782	unsigned I = 1;	0	7782	unsigned I = 1;	0
7783	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	7783	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
7784	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0	7784	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
7785	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0	7785	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
7786	}	---	7786	}	---
7787		---	7787		---
7788	for (unsigned E = Operands.size(); I != E; ++I) {	0	7788	for (unsigned E = Operands.size(); I != E; ++I) {	0
7789	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0	7789	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
7790	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	7790	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
7791	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0	7791	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
7792	} else if (Op.isInterpSlot() \|\| Op.isInterpAttr() \|\|	0	7792	} else if (Op.isInterpSlot() \|\| Op.isInterpAttr() \|\|	0
7793	Op.isInterpAttrChan()) {	0	7793	Op.isInterpAttrChan()) {	0
7794	Inst.addOperand(MCOperand::createImm(Op.getImm()));	0	7794	Inst.addOperand(MCOperand::createImm(Op.getImm()));	0
7795	} else if (Op.isImmModifier()) {	0	7795	} else if (Op.isImmModifier()) {	0
7796	OptionalIdx[Op.getImmTy()] = I;	0	7796	OptionalIdx[Op.getImmTy()] = I;	0
7797	} else {	---	7797	} else {	---
7798	llvm_unreachable("unhandled operand type");	0	7798	llvm_unreachable("unhandled operand type");	0
7799	}	---	7799	}	---
7800	}	---	7800	}	---
7801		---	7801		---
7802	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))	0	7802	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))	0
7803	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	7803	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7804	AMDGPUOperand::ImmTyHigh);	---	7804	AMDGPUOperand::ImmTyHigh);	---
7805		---	7805		---
7806	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0	7806	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
7807	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	7807	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7808	AMDGPUOperand::ImmTyClampSI);	---	7808	AMDGPUOperand::ImmTyClampSI);	---
7809		---	7809		---
7810	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0	7810	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
7811	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	7811	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7812	AMDGPUOperand::ImmTyOModSI);	---	7812	AMDGPUOperand::ImmTyOModSI);	---
7813	}	0	7813	}	0
7814		---	7814		---
7815	void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)	0	7815	void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)	0
7816	{	---	7816	{	---
7817	OptionalImmIndexMap OptionalIdx;	0	7817	OptionalImmIndexMap OptionalIdx;	0
7818	unsigned Opc = Inst.getOpcode();	0	7818	unsigned Opc = Inst.getOpcode();	0
7819		---	7819		---
7820	unsigned I = 1;	0	7820	unsigned I = 1;	0
7821	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	7821	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
7822	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0	7822	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
7823	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0	7823	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
7824	}	---	7824	}	---
7825		---	7825		---
7826	for (unsigned E = Operands.size(); I != E; ++I) {	0	7826	for (unsigned E = Operands.size(); I != E; ++I) {	0
7827	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0	7827	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
7828	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	7828	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
7829	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0	7829	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
7830	} else if (Op.isImmModifier()) {	0	7830	} else if (Op.isImmModifier()) {	0
7831	OptionalIdx[Op.getImmTy()] = I;	0	7831	OptionalIdx[Op.getImmTy()] = I;	0
7832	} else {	---	7832	} else {	---
7833	llvm_unreachable("unhandled operand type");	0	7833	llvm_unreachable("unhandled operand type");	0
7834	}	---	7834	}	---
7835	}	---	7835	}	---
7836		---	7836		---
7837	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	0	7837	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	0
7838		---	7838		---
7839	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0	7839	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
7840	if (OpSelIdx != -1)	0	7840	if (OpSelIdx != -1)	0
7841	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	0	7841	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	0
7842		---	7842		---
7843	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);	0	7843	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyWaitEXP);	0
7844		---	7844		---
7845	if (OpSelIdx == -1)	0	7845	if (OpSelIdx == -1)	0
7846	return;	0	7846	return;	0
7847		---	7847		---
7848	const int Ops[] = { AMDGPU::OpName::src0,	0	7848	const int Ops[] = { AMDGPU::OpName::src0,	0
7849	AMDGPU::OpName::src1,	---	7849	AMDGPU::OpName::src1,	---
7850	AMDGPU::OpName::src2 };	---	7850	AMDGPU::OpName::src2 };	---
7851	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	0	7851	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	0
7852	AMDGPU::OpName::src1_modifiers,	---	7852	AMDGPU::OpName::src1_modifiers,	---
7853	AMDGPU::OpName::src2_modifiers };	---	7853	AMDGPU::OpName::src2_modifiers };	---
7854		---	7854		---
7855	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0	7855	unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();	0
7856		---	7856		---
7857	for (int J = 0; J < 3; ++J) {	0	7857	for (int J = 0; J < 3; ++J) {	0
7858	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	0	7858	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	0
7859	if (OpIdx == -1)	0	7859	if (OpIdx == -1)	0
7860	break;	0	7860	break;	0
7861		---	7861		---
7862	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	0	7862	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	0
7863	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	0	7863	uint32_t ModVal = Inst.getOperand(ModIdx).getImm();	0
7864		---	7864		---
7865	if ((OpSel & (1 << J)) != 0)	0	7865	if ((OpSel & (1 << J)) != 0)	0
7866	ModVal \|= SISrcMods::OP_SEL_0;	0	7866	ModVal \|= SISrcMods::OP_SEL_0;	0
7867	if (ModOps[J] == AMDGPU::OpName::src0_modifiers &&	0	7867	if (ModOps[J] == AMDGPU::OpName::src0_modifiers &&	0
7868	(OpSel & (1 << 3)) != 0)	0	7868	(OpSel & (1 << 3)) != 0)	0
7869	ModVal \|= SISrcMods::DST_OP_SEL;	0	7869	ModVal \|= SISrcMods::DST_OP_SEL;	0
7870		---	7870		---
7871	Inst.getOperand(ModIdx).setImm(ModVal);	0	7871	Inst.getOperand(ModIdx).setImm(ModVal);	0
7872	}	---	7872	}	---
7873	}	0	7873	}	0
7874		---	7874		---
7875	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,	0	7875	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,	0
7876	OptionalImmIndexMap &OptionalIdx) {	---	7876	OptionalImmIndexMap &OptionalIdx) {	---
7877	unsigned Opc = Inst.getOpcode();	0	7877	unsigned Opc = Inst.getOpcode();	0
7878		---	7878		---
7879	unsigned I = 1;	0	7879	unsigned I = 1;	0
7880	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	7880	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
7881	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0	7881	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
7882	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0	7882	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
7883	}	---	7883	}	---
7884		---	7884		---
7885	for (unsigned E = Operands.size(); I != E; ++I) {	0	7885	for (unsigned E = Operands.size(); I != E; ++I) {	0
7886	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0	7886	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
7887	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	7887	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
7888	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0	7888	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
7889	} else if (Op.isImmModifier()) {	0	7889	} else if (Op.isImmModifier()) {	0
7890	OptionalIdx[Op.getImmTy()] = I;	0	7890	OptionalIdx[Op.getImmTy()] = I;	0
7891	} else if (Op.isRegOrImm()) {	0	7891	} else if (Op.isRegOrImm()) {	0
7892	Op.addRegOrImmOperands(Inst, 1);	0	7892	Op.addRegOrImmOperands(Inst, 1);	0
7893	} else {	---	7893	} else {	---
7894	llvm_unreachable("unhandled operand type");	0	7894	llvm_unreachable("unhandled operand type");	0
7895	}	---	7895	}	---
7896	}	---	7896	}	---
7897		---	7897		---
7898	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0	7898	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
7899	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	7899	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7900	AMDGPUOperand::ImmTyClampSI);	---	7900	AMDGPUOperand::ImmTyClampSI);	---
7901		---	7901		---
7902	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0	7902	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
7903	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	7903	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
7904	AMDGPUOperand::ImmTyOModSI);	---	7904	AMDGPUOperand::ImmTyOModSI);	---
7905		---	7905		---
7906	// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):	---	7906	// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):	---
7907	// it has src2 register operand that is tied to dst operand	---	7907	// it has src2 register operand that is tied to dst operand	---
7908	// we don't allow modifiers for this operand in assembler so src2_modifiers	---	7908	// we don't allow modifiers for this operand in assembler so src2_modifiers	---
7909	// should be 0.	---	7909	// should be 0.	---
7910	if (isMAC(Opc)) {	0	7910	if (isMAC(Opc)) {	0
7911	auto it = Inst.begin();	0	7911	auto it = Inst.begin();	0
7912	std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));	0	7912	std::advance(it, AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers));	0
7913	it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2	0	7913	it = Inst.insert(it, MCOperand::createImm(0)); // no modifiers for src2	0
7914	++it;	0	7914	++it;	0
7915	// Copy the operand to ensure it's not invalidated when Inst grows.	---	7915	// Copy the operand to ensure it's not invalidated when Inst grows.	---
7916	Inst.insert(it, MCOperand(Inst.getOperand(0))); // src2 = dst	0	7916	Inst.insert(it, MCOperand(Inst.getOperand(0))); // src2 = dst	0
7917	}	---	7917	}	---
7918	}	0	7918	}	0
7919		---	7919		---
7920	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {	0	7920	void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands) {	0
7921	OptionalImmIndexMap OptionalIdx;	0	7921	OptionalImmIndexMap OptionalIdx;	0
7922	cvtVOP3(Inst, Operands, OptionalIdx);	0	7922	cvtVOP3(Inst, Operands, OptionalIdx);	0
7923	}	0	7923	}	0
7924		---	7924		---
7925	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	0	7925	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,	0
7926	OptionalImmIndexMap &OptIdx) {	---	7926	OptionalImmIndexMap &OptIdx) {	---
7927	const int Opc = Inst.getOpcode();	0	7927	const int Opc = Inst.getOpcode();	0
7928	const MCInstrDesc &Desc = MII.get(Opc);	0	7928	const MCInstrDesc &Desc = MII.get(Opc);	0
7929		---	7929		---
7930	const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;	0	7930	const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;	0
7931		---	7931		---
7932	if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi \|\|	0	7932	if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi \|\|	0
7933	Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) {	---	7933	Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) {	---
7934	Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods	0	7934	Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods	0
7935	Inst.addOperand(Inst.getOperand(0));	0	7935	Inst.addOperand(Inst.getOperand(0));	0
7936	}	---	7936	}	---
7937		---	7937		---
7938	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {	0	7938	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {	0
7939	assert(!IsPacked);	0	7939	assert(!IsPacked);	0
7940	Inst.addOperand(Inst.getOperand(0));	0	7940	Inst.addOperand(Inst.getOperand(0));	0
7941	}	---	7941	}	---
7942		---	7942		---
7943	// FIXME: This is messy. Parse the modifiers as if it was a normal VOP3	---	7943	// FIXME: This is messy. Parse the modifiers as if it was a normal VOP3	---
7944	// instruction, and then figure out where to actually put the modifiers	---	7944	// instruction, and then figure out where to actually put the modifiers	---
7945		---	7945		---
7946	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0	7946	int OpSelIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel);	0
7947	if (OpSelIdx != -1) {	0	7947	if (OpSelIdx != -1) {	0
7948	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);	0	7948	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSel);	0
7949	}	---	7949	}	---
7950		---	7950		---
7951	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	0	7951	int OpSelHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi);	0
7952	if (OpSelHiIdx != -1) {	0	7952	if (OpSelHiIdx != -1) {	0
7953	int DefaultVal = IsPacked ? -1 : 0;	0	7953	int DefaultVal = IsPacked ? -1 : 0;	0
7954	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,	0	7954	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyOpSelHi,	0
7955	DefaultVal);	---	7955	DefaultVal);	---
7956	}	---	7956	}	---
7957		---	7957		---
7958	int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);	0	7958	int NegLoIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo);	0
7959	if (NegLoIdx != -1) {	0	7959	if (NegLoIdx != -1) {	0
7960	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);	0	7960	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegLo);	0
7961	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);	0	7961	addOptionalImmOperand(Inst, Operands, OptIdx, AMDGPUOperand::ImmTyNegHi);	0
7962	}	---	7962	}	---
7963		---	7963		---
7964	const int Ops[] = { AMDGPU::OpName::src0,	0	7964	const int Ops[] = { AMDGPU::OpName::src0,	0
7965	AMDGPU::OpName::src1,	---	7965	AMDGPU::OpName::src1,	---
7966	AMDGPU::OpName::src2 };	---	7966	AMDGPU::OpName::src2 };	---
7967	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	0	7967	const int ModOps[] = { AMDGPU::OpName::src0_modifiers,	0
7968	AMDGPU::OpName::src1_modifiers,	---	7968	AMDGPU::OpName::src1_modifiers,	---
7969	AMDGPU::OpName::src2_modifiers };	---	7969	AMDGPU::OpName::src2_modifiers };	---
7970		---	7970		---
7971	unsigned OpSel = 0;	0	7971	unsigned OpSel = 0;	0
7972	unsigned OpSelHi = 0;	0	7972	unsigned OpSelHi = 0;	0
7973	unsigned NegLo = 0;	0	7973	unsigned NegLo = 0;	0
7974	unsigned NegHi = 0;	0	7974	unsigned NegHi = 0;	0
7975		---	7975		---
7976	if (OpSelIdx != -1)	0	7976	if (OpSelIdx != -1)	0
7977	OpSel = Inst.getOperand(OpSelIdx).getImm();	0	7977	OpSel = Inst.getOperand(OpSelIdx).getImm();	0
7978		---	7978		---
7979	if (OpSelHiIdx != -1)	0	7979	if (OpSelHiIdx != -1)	0
7980	OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();	0	7980	OpSelHi = Inst.getOperand(OpSelHiIdx).getImm();	0
7981		---	7981		---
7982	if (NegLoIdx != -1) {	0	7982	if (NegLoIdx != -1) {	0
7983	int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);	0	7983	int NegHiIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi);	0
7984	NegLo = Inst.getOperand(NegLoIdx).getImm();	0	7984	NegLo = Inst.getOperand(NegLoIdx).getImm();	0
7985	NegHi = Inst.getOperand(NegHiIdx).getImm();	0	7985	NegHi = Inst.getOperand(NegHiIdx).getImm();	0
7986	}	---	7986	}	---
7987		---	7987		---
7988	for (int J = 0; J < 3; ++J) {	0	7988	for (int J = 0; J < 3; ++J) {	0
7989	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	0	7989	int OpIdx = AMDGPU::getNamedOperandIdx(Opc, Ops[J]);	0
7990	if (OpIdx == -1)	0	7990	if (OpIdx == -1)	0
7991	break;	0	7991	break;	0
7992		---	7992		---
7993	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	0	7993	int ModIdx = AMDGPU::getNamedOperandIdx(Opc, ModOps[J]);	0
7994		---	7994		---
7995	if (ModIdx == -1)	0	7995	if (ModIdx == -1)	0
7996	continue;	0	7996	continue;	0
7997		---	7997		---
7998	uint32_t ModVal = 0;	0	7998	uint32_t ModVal = 0;	0
7999		---	7999		---
8000	if ((OpSel & (1 << J)) != 0)	0	8000	if ((OpSel & (1 << J)) != 0)	0
8001	ModVal \|= SISrcMods::OP_SEL_0;	0	8001	ModVal \|= SISrcMods::OP_SEL_0;	0
8002		---	8002		---
8003	if ((OpSelHi & (1 << J)) != 0)	0	8003	if ((OpSelHi & (1 << J)) != 0)	0
8004	ModVal \|= SISrcMods::OP_SEL_1;	0	8004	ModVal \|= SISrcMods::OP_SEL_1;	0
8005		---	8005		---
8006	if ((NegLo & (1 << J)) != 0)	0	8006	if ((NegLo & (1 << J)) != 0)	0
8007	ModVal \|= SISrcMods::NEG;	0	8007	ModVal \|= SISrcMods::NEG;	0
8008		---	8008		---
8009	if ((NegHi & (1 << J)) != 0)	0	8009	if ((NegHi & (1 << J)) != 0)	0
8010	ModVal \|= SISrcMods::NEG_HI;	0	8010	ModVal \|= SISrcMods::NEG_HI;	0
8011		---	8011		---
8012	Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() \| ModVal);	0	8012	Inst.getOperand(ModIdx).setImm(Inst.getOperand(ModIdx).getImm() \| ModVal);	0
8013	}	---	8013	}	---
8014	}	0	8014	}	0
8015		---	8015		---
8016	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {	0	8016	void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands) {	0
8017	OptionalImmIndexMap OptIdx;	0	8017	OptionalImmIndexMap OptIdx;	0
8018	cvtVOP3(Inst, Operands, OptIdx);	0	8018	cvtVOP3(Inst, Operands, OptIdx);	0
8019	cvtVOP3P(Inst, Operands, OptIdx);	0	8019	cvtVOP3P(Inst, Operands, OptIdx);	0
8020	}	0	8020	}	0
8021		---	8021		---
8022	//===----------------------------------------------------------------------===//	---	8022	//===----------------------------------------------------------------------===//	---
8023	// VOPD	---	8023	// VOPD	---
8024	//===----------------------------------------------------------------------===//	---	8024	//===----------------------------------------------------------------------===//	---
8025		---	8025		---
8026	ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {	0	8026	ParseStatus AMDGPUAsmParser::parseVOPD(OperandVector &Operands) {	0
8027	if (!hasVOPD(getSTI()))	0	8027	if (!hasVOPD(getSTI()))	0
8028	return ParseStatus::NoMatch;	0	8028	return ParseStatus::NoMatch;	0
8029		---	8029		---
8030	if (isToken(AsmToken::Colon) && peekToken(false).is(AsmToken::Colon)) {	0	8030	if (isToken(AsmToken::Colon) && peekToken(false).is(AsmToken::Colon)) {	0
8031	SMLoc S = getLoc();	0	8031	SMLoc S = getLoc();	0
8032	lex();	0	8032	lex();	0
8033	lex();	0	8033	lex();	0
8034	Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));	0	8034	Operands.push_back(AMDGPUOperand::CreateToken(this, "::", S));	0
8035	SMLoc OpYLoc = getLoc();	0	8035	SMLoc OpYLoc = getLoc();	0
8036	StringRef OpYName;	0	8036	StringRef OpYName;	0
8037	if (isToken(AsmToken::Identifier) && !Parser.parseIdentifier(OpYName)) {	0	8037	if (isToken(AsmToken::Identifier) && !Parser.parseIdentifier(OpYName)) {	0
8038	Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));	0	8038	Operands.push_back(AMDGPUOperand::CreateToken(this, OpYName, OpYLoc));	0
8039	return ParseStatus::Success;	0	8039	return ParseStatus::Success;	0
8040	}	---	8040	}	---
8041	return Error(OpYLoc, "expected a VOPDY instruction after ::");	0	8041	return Error(OpYLoc, "expected a VOPDY instruction after ::");	0
8042	}	---	8042	}	---
8043	return ParseStatus::NoMatch;	0	8043	return ParseStatus::NoMatch;	0
8044	}	---	8044	}	---
8045		---	8045		---
8046	// Create VOPD MCInst operands using parsed assembler operands.	---	8046	// Create VOPD MCInst operands using parsed assembler operands.	---
8047	void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {	0	8047	void AMDGPUAsmParser::cvtVOPD(MCInst &Inst, const OperandVector &Operands) {	0
8048	auto addOp = [&](uint16_t ParsedOprIdx) { // NOLINT:function pointer	0	8048	auto addOp = [&](uint16_t ParsedOprIdx) { // NOLINT:function pointer	0
8049	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);	0	8049	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[ParsedOprIdx]);	0
8050	if (Op.isReg()) {	0	8050	if (Op.isReg()) {	0
8051	Op.addRegOperands(Inst, 1);	0	8051	Op.addRegOperands(Inst, 1);	0
8052	return;	0	8052	return;	0
8053	}	---	8053	}	---
8054	if (Op.isImm()) {	0	8054	if (Op.isImm()) {	0
8055	Op.addImmOperands(Inst, 1);	0	8055	Op.addImmOperands(Inst, 1);	0
8056	return;	0	8056	return;	0
8057	}	---	8057	}	---
8058	llvm_unreachable("Unhandled operand type in cvtVOPD");	0	8058	llvm_unreachable("Unhandled operand type in cvtVOPD");	0
8059	};	0	8059	};	0
8060		---	8060		---
8061	const auto &InstInfo = getVOPDInstInfo(Inst.getOpcode(), &MII);	0	8061	const auto &InstInfo = getVOPDInstInfo(Inst.getOpcode(), &MII);	0
8062		---	8062		---
8063	// MCInst operands are ordered as follows:	---	8063	// MCInst operands are ordered as follows:	---
8064	// dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]	---	8064	// dstX, dstY, src0X [, other OpX operands], src0Y [, other OpY operands]	---
8065		---	8065		---
8066	for (auto CompIdx : VOPD::COMPONENTS) {	0	8066	for (auto CompIdx : VOPD::COMPONENTS) {	0
8067	addOp(InstInfo[CompIdx].getIndexOfDstInParsedOperands());	0	8067	addOp(InstInfo[CompIdx].getIndexOfDstInParsedOperands());	0
8068	}	---	8068	}	---
8069		---	8069		---
8070	for (auto CompIdx : VOPD::COMPONENTS) {	0	8070	for (auto CompIdx : VOPD::COMPONENTS) {	0
8071	const auto &CInfo = InstInfo[CompIdx];	0	8071	const auto &CInfo = InstInfo[CompIdx];	0
8072	auto CompSrcOperandsNum = InstInfo[CompIdx].getCompParsedSrcOperandsNum();	0	8072	auto CompSrcOperandsNum = InstInfo[CompIdx].getCompParsedSrcOperandsNum();	0
8073	for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOperandsNum; ++CompSrcIdx)	0	8073	for (unsigned CompSrcIdx = 0; CompSrcIdx < CompSrcOperandsNum; ++CompSrcIdx)	0
8074	addOp(CInfo.getIndexOfSrcInParsedOperands(CompSrcIdx));	0	8074	addOp(CInfo.getIndexOfSrcInParsedOperands(CompSrcIdx));	0
8075	if (CInfo.hasSrc2Acc())	0	8075	if (CInfo.hasSrc2Acc())	0
8076	addOp(CInfo.getIndexOfDstInParsedOperands());	0	8076	addOp(CInfo.getIndexOfDstInParsedOperands());	0
8077	}	---	8077	}	---
8078	}	0	8078	}	0
8079		---	8079		---
8080	//===----------------------------------------------------------------------===//	---	8080	//===----------------------------------------------------------------------===//	---
8081	// dpp	---	8081	// dpp	---
8082	//===----------------------------------------------------------------------===//	---	8082	//===----------------------------------------------------------------------===//	---
8083		---	8083		---
8084	bool AMDGPUOperand::isDPP8() const {	0	8084	bool AMDGPUOperand::isDPP8() const {	0
8085	return isImmTy(ImmTyDPP8);	0	8085	return isImmTy(ImmTyDPP8);	0
8086	}	---	8086	}	---
8087		---	8087		---
8088	bool AMDGPUOperand::isDPPCtrl() const {	0	8088	bool AMDGPUOperand::isDPPCtrl() const {	0
8089	using namespace AMDGPU::DPP;	---	8089	using namespace AMDGPU::DPP;	---
8090		---	8090		---
8091	bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());	0	8091	bool result = isImm() && getImmTy() == ImmTyDppCtrl && isUInt<9>(getImm());	0
8092	if (result) {	0	8092	if (result) {	0
8093	int64_t Imm = getImm();	0	8093	int64_t Imm = getImm();	0
8094	return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) \|\|	0	8094	return (Imm >= DppCtrl::QUAD_PERM_FIRST && Imm <= DppCtrl::QUAD_PERM_LAST) \|\|	0
8095	(Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) \|\|	0	8095	(Imm >= DppCtrl::ROW_SHL_FIRST && Imm <= DppCtrl::ROW_SHL_LAST) \|\|	0
8096	(Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) \|\|	0	8096	(Imm >= DppCtrl::ROW_SHR_FIRST && Imm <= DppCtrl::ROW_SHR_LAST) \|\|	0
8097	(Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) \|\|	0	8097	(Imm >= DppCtrl::ROW_ROR_FIRST && Imm <= DppCtrl::ROW_ROR_LAST) \|\|	0
8098	(Imm == DppCtrl::WAVE_SHL1) \|\|	0	8098	(Imm == DppCtrl::WAVE_SHL1) \|\|	0
8099	(Imm == DppCtrl::WAVE_ROL1) \|\|	0	8099	(Imm == DppCtrl::WAVE_ROL1) \|\|	0
8100	(Imm == DppCtrl::WAVE_SHR1) \|\|	0	8100	(Imm == DppCtrl::WAVE_SHR1) \|\|	0
8101	(Imm == DppCtrl::WAVE_ROR1) \|\|	0	8101	(Imm == DppCtrl::WAVE_ROR1) \|\|	0
8102	(Imm == DppCtrl::ROW_MIRROR) \|\|	0	8102	(Imm == DppCtrl::ROW_MIRROR) \|\|	0
8103	(Imm == DppCtrl::ROW_HALF_MIRROR) \|\|	0	8103	(Imm == DppCtrl::ROW_HALF_MIRROR) \|\|	0
8104	(Imm == DppCtrl::BCAST15) \|\|	0	8104	(Imm == DppCtrl::BCAST15) \|\|	0
8105	(Imm == DppCtrl::BCAST31) \|\|	0	8105	(Imm == DppCtrl::BCAST31) \|\|	0
8106	(Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) \|\|	0	8106	(Imm >= DppCtrl::ROW_SHARE_FIRST && Imm <= DppCtrl::ROW_SHARE_LAST) \|\|	0
8107	(Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST);	0	8107	(Imm >= DppCtrl::ROW_XMASK_FIRST && Imm <= DppCtrl::ROW_XMASK_LAST);	0
8108	}	---	8108	}	---
8109	return false;	0	8109	return false;	0
8110	}	---	8110	}	---
8111		---	8111		---
8112	//===----------------------------------------------------------------------===//	---	8112	//===----------------------------------------------------------------------===//	---
8113	// mAI	---	8113	// mAI	---
8114	//===----------------------------------------------------------------------===//	---	8114	//===----------------------------------------------------------------------===//	---
8115		---	8115		---
8116	bool AMDGPUOperand::isBLGP() const {	0	8116	bool AMDGPUOperand::isBLGP() const {	0
8117	return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());	0	8117	return isImm() && getImmTy() == ImmTyBLGP && isUInt<3>(getImm());	0
8118	}	---	8118	}	---
8119		---	8119		---
8120	bool AMDGPUOperand::isCBSZ() const {	0	8120	bool AMDGPUOperand::isCBSZ() const {	0
8121	return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());	0	8121	return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm());	0
8122	}	---	8122	}	---
8123		---	8123		---
8124	bool AMDGPUOperand::isABID() const {	0	8124	bool AMDGPUOperand::isABID() const {	0
8125	return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());	0	8125	return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm());	0
8126	}	---	8126	}	---
8127		---	8127		---
8128	bool AMDGPUOperand::isS16Imm() const {	0	8128	bool AMDGPUOperand::isS16Imm() const {	0
8129	return isImmLiteral() && (isInt<16>(getImm()) \|\| isUInt<16>(getImm()));	0	8129	return isImmLiteral() && (isInt<16>(getImm()) \|\| isUInt<16>(getImm()));	0
8130	}	---	8130	}	---
8131		---	8131		---
8132	bool AMDGPUOperand::isU16Imm() const {	0	8132	bool AMDGPUOperand::isU16Imm() const {	0
8133	return isImmLiteral() && isUInt<16>(getImm());	0	8133	return isImmLiteral() && isUInt<16>(getImm());	0
8134	}	---	8134	}	---
8135		---	8135		---
8136	//===----------------------------------------------------------------------===//	---	8136	//===----------------------------------------------------------------------===//	---
8137	// dim	---	8137	// dim	---
8138	//===----------------------------------------------------------------------===//	---	8138	//===----------------------------------------------------------------------===//	---
8139		---	8139		---
8140	bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {	0	8140	bool AMDGPUAsmParser::parseDimId(unsigned &Encoding) {	0
8141	// We want to allow "dim:1D" etc.,	---	8141	// We want to allow "dim:1D" etc.,	---
8142	// but the initial 1 is tokenized as an integer.	---	8142	// but the initial 1 is tokenized as an integer.	---
8143	std::string Token;	0	8143	std::string Token;	0
8144	if (isToken(AsmToken::Integer)) {	0	8144	if (isToken(AsmToken::Integer)) {	0
8145	SMLoc Loc = getToken().getEndLoc();	0	8145	SMLoc Loc = getToken().getEndLoc();	0
8146	Token = std::string(getTokenStr());	0	8146	Token = std::string(getTokenStr());	0
8147	lex();	0	8147	lex();	0
8148	if (getLoc() != Loc)	0	8148	if (getLoc() != Loc)	0
8149	return false;	0	8149	return false;	0
8150	}	---	8150	}	---
8151		---	8151		---
8152	StringRef Suffix;	0	8152	StringRef Suffix;	0
8153	if (!parseId(Suffix))	0	8153	if (!parseId(Suffix))	0
8154	return false;	0	8154	return false;	0
8155	Token += Suffix;	0	8155	Token += Suffix;	0
8156		---	8156		---
8157	StringRef DimId = Token;	0	8157	StringRef DimId = Token;	0
8158	if (DimId.startswith("SQ_RSRC_IMG_"))	0	8158	if (DimId.startswith("SQ_RSRC_IMG_"))	0
8159	DimId = DimId.drop_front(12);	0	8159	DimId = DimId.drop_front(12);	0
8160		---	8160		---
8161	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);	0	8161	const AMDGPU::MIMGDimInfo *DimInfo = AMDGPU::getMIMGDimInfoByAsmSuffix(DimId);	0
8162	if (!DimInfo)	0	8162	if (!DimInfo)	0
8163	return false;	0	8163	return false;	0
8164		---	8164		---
8165	Encoding = DimInfo->Encoding;	0	8165	Encoding = DimInfo->Encoding;	0
8166	return true;	0	8166	return true;	0
8167	}	0	8167	}	0
8168		---	8168		---
8169	ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {	0	8169	ParseStatus AMDGPUAsmParser::parseDim(OperandVector &Operands) {	0
8170	if (!isGFX10Plus())	0	8170	if (!isGFX10Plus())	0
8171	return ParseStatus::NoMatch;	0	8171	return ParseStatus::NoMatch;	0
8172		---	8172		---
8173	SMLoc S = getLoc();	0	8173	SMLoc S = getLoc();	0
8174		---	8174		---
8175	if (!trySkipId("dim", AsmToken::Colon))	0	8175	if (!trySkipId("dim", AsmToken::Colon))	0
8176	return ParseStatus::NoMatch;	0	8176	return ParseStatus::NoMatch;	0
8177		---	8177		---
8178	unsigned Encoding;	---	8178	unsigned Encoding;	---
8179	SMLoc Loc = getLoc();	0	8179	SMLoc Loc = getLoc();	0
8180	if (!parseDimId(Encoding))	0	8180	if (!parseDimId(Encoding))	0
8181	return Error(Loc, "invalid dim value");	0	8181	return Error(Loc, "invalid dim value");	0
8182		---	8182		---
8183	Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,	0	8183	Operands.push_back(AMDGPUOperand::CreateImm(this, Encoding, S,	0
8184	AMDGPUOperand::ImmTyDim));	---	8184	AMDGPUOperand::ImmTyDim));	---
8185	return ParseStatus::Success;	0	8185	return ParseStatus::Success;	0
8186	}	---	8186	}	---
8187		---	8187		---
8188	//===----------------------------------------------------------------------===//	---	8188	//===----------------------------------------------------------------------===//	---
8189	// dpp	---	8189	// dpp	---
8190	//===----------------------------------------------------------------------===//	---	8190	//===----------------------------------------------------------------------===//	---
8191		---	8191		---
8192	ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {	0	8192	ParseStatus AMDGPUAsmParser::parseDPP8(OperandVector &Operands) {	0
8193	SMLoc S = getLoc();	0	8193	SMLoc S = getLoc();	0
8194		---	8194		---
8195	if (!isGFX10Plus() \|\| !trySkipId("dpp8", AsmToken::Colon))	0	8195	if (!isGFX10Plus() \|\| !trySkipId("dpp8", AsmToken::Colon))	0
8196	return ParseStatus::NoMatch;	0	8196	return ParseStatus::NoMatch;	0
8197		---	8197		---
8198	// dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]	---	8198	// dpp8:[%d,%d,%d,%d,%d,%d,%d,%d]	---
8199		---	8199		---
8200	int64_t Sels[8];	---	8200	int64_t Sels[8];	---
8201		---	8201		---
8202	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	0	8202	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	0
8203	return ParseStatus::Failure;	0	8203	return ParseStatus::Failure;	0
8204		---	8204		---
8205	for (size_t i = 0; i < 8; ++i) {	0	8205	for (size_t i = 0; i < 8; ++i) {	0
8206	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	0	8206	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	0
8207	return ParseStatus::Failure;	0	8207	return ParseStatus::Failure;	0
8208		---	8208		---
8209	SMLoc Loc = getLoc();	0	8209	SMLoc Loc = getLoc();	0
8210	if (getParser().parseAbsoluteExpression(Sels[i]))	0	8210	if (getParser().parseAbsoluteExpression(Sels[i]))	0
8211	return ParseStatus::Failure;	0	8211	return ParseStatus::Failure;	0
8212	if (0 > Sels[i] \|\| 7 < Sels[i])	0	8212	if (0 > Sels[i] \|\| 7 < Sels[i])	0
8213	return Error(Loc, "expected a 3-bit value");	0	8213	return Error(Loc, "expected a 3-bit value");	0
8214	}	---	8214	}	---
8215		---	8215		---
8216	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0	8216	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
8217	return ParseStatus::Failure;	0	8217	return ParseStatus::Failure;	0
8218		---	8218		---
8219	unsigned DPP8 = 0;	0	8219	unsigned DPP8 = 0;	0
8220	for (size_t i = 0; i < 8; ++i)	0	8220	for (size_t i = 0; i < 8; ++i)	0
8221	DPP8 \|= (Sels[i] << (i * 3));	0	8221	DPP8 \|= (Sels[i] << (i * 3));	0
8222		---	8222		---
8223	Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));	0	8223	Operands.push_back(AMDGPUOperand::CreateImm(this, DPP8, S, AMDGPUOperand::ImmTyDPP8));	0
8224	return ParseStatus::Success;	0	8224	return ParseStatus::Success;	0
8225	}	---	8225	}	---
8226		---	8226		---
8227	bool	---	8227	bool	---
8228	AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,	0	8228	AMDGPUAsmParser::isSupportedDPPCtrl(StringRef Ctrl,	0
8229	const OperandVector &Operands) {	---	8229	const OperandVector &Operands) {	---
8230	if (Ctrl == "row_newbcast")	0	8230	if (Ctrl == "row_newbcast")	0
8231	return isGFX90A();	0	8231	return isGFX90A();	0
8232		---	8232		---
8233	if (Ctrl == "row_share" \|\|	0	8233	if (Ctrl == "row_share" \|\|	0
8234	Ctrl == "row_xmask")	0	8234	Ctrl == "row_xmask")	0
8235	return isGFX10Plus();	0	8235	return isGFX10Plus();	0
8236		---	8236		---
8237	if (Ctrl == "wave_shl" \|\|	0	8237	if (Ctrl == "wave_shl" \|\|	0
8238	Ctrl == "wave_shr" \|\|	0	8238	Ctrl == "wave_shr" \|\|	0
8239	Ctrl == "wave_rol" \|\|	0	8239	Ctrl == "wave_rol" \|\|	0
8240	Ctrl == "wave_ror" \|\|	0	8240	Ctrl == "wave_ror" \|\|	0
8241	Ctrl == "row_bcast")	0	8241	Ctrl == "row_bcast")	0
8242	return isVI() \|\| isGFX9();	0	8242	return isVI() \|\| isGFX9();	0
8243		---	8243		---
8244	return Ctrl == "row_mirror" \|\|	0	8244	return Ctrl == "row_mirror" \|\|	0
8245	Ctrl == "row_half_mirror" \|\|	0	8245	Ctrl == "row_half_mirror" \|\|	0
8246	Ctrl == "quad_perm" \|\|	0	8246	Ctrl == "quad_perm" \|\|	0
8247	Ctrl == "row_shl" \|\|	0	8247	Ctrl == "row_shl" \|\|	0
8248	Ctrl == "row_shr" \|\|	0	8248	Ctrl == "row_shr" \|\|	0
8249	Ctrl == "row_ror";	0	8249	Ctrl == "row_ror";	0
8250	}	---	8250	}	---
8251		---	8251		---
8252	int64_t	---	8252	int64_t	---
8253	AMDGPUAsmParser::parseDPPCtrlPerm() {	0	8253	AMDGPUAsmParser::parseDPPCtrlPerm() {	0
8254	// quad_perm:[%d,%d,%d,%d]	---	8254	// quad_perm:[%d,%d,%d,%d]	---
8255		---	8255		---
8256	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	0	8256	if (!skipToken(AsmToken::LBrac, "expected an opening square bracket"))	0
8257	return -1;	0	8257	return -1;	0
8258		---	8258		---
8259	int64_t Val = 0;	0	8259	int64_t Val = 0;	0
8260	for (int i = 0; i < 4; ++i) {	0	8260	for (int i = 0; i < 4; ++i) {	0
8261	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	0	8261	if (i > 0 && !skipToken(AsmToken::Comma, "expected a comma"))	0
8262	return -1;	0	8262	return -1;	0
8263		---	8263		---
8264	int64_t Temp;	---	8264	int64_t Temp;	---
8265	SMLoc Loc = getLoc();	0	8265	SMLoc Loc = getLoc();	0
8266	if (getParser().parseAbsoluteExpression(Temp))	0	8266	if (getParser().parseAbsoluteExpression(Temp))	0
8267	return -1;	0	8267	return -1;	0
8268	if (Temp < 0 \|\| Temp > 3) {	0	8268	if (Temp < 0 \|\| Temp > 3) {	0
8269	Error(Loc, "expected a 2-bit value");	0	8269	Error(Loc, "expected a 2-bit value");	0
8270	return -1;	0	8270	return -1;	0
8271	}	---	8271	}	---
8272		---	8272		---
8273	Val += (Temp << i * 2);	0	8273	Val += (Temp << i * 2);	0
8274	}	---	8274	}	---
8275		---	8275		---
8276	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0	8276	if (!skipToken(AsmToken::RBrac, "expected a closing square bracket"))	0
8277	return -1;	0	8277	return -1;	0
8278		---	8278		---
8279	return Val;	0	8279	return Val;	0
8280	}	---	8280	}	---
8281		---	8281		---
8282	int64_t	---	8282	int64_t	---
8283	AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {	0	8283	AMDGPUAsmParser::parseDPPCtrlSel(StringRef Ctrl) {	0
8284	using namespace AMDGPU::DPP;	---	8284	using namespace AMDGPU::DPP;	---
8285		---	8285		---
8286	// sel:%d	---	8286	// sel:%d	---
8287		---	8287		---
8288	int64_t Val;	---	8288	int64_t Val;	---
8289	SMLoc Loc = getLoc();	0	8289	SMLoc Loc = getLoc();	0
8290		---	8290		---
8291	if (getParser().parseAbsoluteExpression(Val))	0	8291	if (getParser().parseAbsoluteExpression(Val))	0
8292	return -1;	0	8292	return -1;	0
8293		---	8293		---
8294	struct DppCtrlCheck {	---	8294	struct DppCtrlCheck {	---
8295	int64_t Ctrl;	---	8295	int64_t Ctrl;	---
8296	int Lo;	---	8296	int Lo;	---
8297	int Hi;	---	8297	int Hi;	---
8298	};	---	8298	};	---
8299		---	8299		---
8300	DppCtrlCheck Check = StringSwitch(Ctrl)	0	8300	DppCtrlCheck Check = StringSwitch(Ctrl)	0
8301	.Case("wave_shl", {DppCtrl::WAVE_SHL1, 1, 1})	0	8301	.Case("wave_shl", {DppCtrl::WAVE_SHL1, 1, 1})	0
8302	.Case("wave_rol", {DppCtrl::WAVE_ROL1, 1, 1})	0	8302	.Case("wave_rol", {DppCtrl::WAVE_ROL1, 1, 1})	0
8303	.Case("wave_shr", {DppCtrl::WAVE_SHR1, 1, 1})	0	8303	.Case("wave_shr", {DppCtrl::WAVE_SHR1, 1, 1})	0
8304	.Case("wave_ror", {DppCtrl::WAVE_ROR1, 1, 1})	0	8304	.Case("wave_ror", {DppCtrl::WAVE_ROR1, 1, 1})	0
8305	.Case("row_shl", {DppCtrl::ROW_SHL0, 1, 15})	0	8305	.Case("row_shl", {DppCtrl::ROW_SHL0, 1, 15})	0
8306	.Case("row_shr", {DppCtrl::ROW_SHR0, 1, 15})	0	8306	.Case("row_shr", {DppCtrl::ROW_SHR0, 1, 15})	0
8307	.Case("row_ror", {DppCtrl::ROW_ROR0, 1, 15})	0	8307	.Case("row_ror", {DppCtrl::ROW_ROR0, 1, 15})	0
8308	.Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})	0	8308	.Case("row_share", {DppCtrl::ROW_SHARE_FIRST, 0, 15})	0
8309	.Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})	0	8309	.Case("row_xmask", {DppCtrl::ROW_XMASK_FIRST, 0, 15})	0
8310	.Case("row_newbcast", {DppCtrl::ROW_NEWBCAST_FIRST, 0, 15})	0	8310	.Case("row_newbcast", {DppCtrl::ROW_NEWBCAST_FIRST, 0, 15})	0
8311	.Default({-1, 0, 0});	0	8311	.Default({-1, 0, 0});	0
8312		---	8312		---
8313	bool Valid;	---	8313	bool Valid;	---
8314	if (Check.Ctrl == -1) {	0	8314	if (Check.Ctrl == -1) {	0
8315	Valid = (Ctrl == "row_bcast" && (Val == 15 \|\| Val == 31));	0	8315	Valid = (Ctrl == "row_bcast" && (Val == 15 \|\| Val == 31));	0
8316	Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31;	0	8316	Val = (Val == 15)? DppCtrl::BCAST15 : DppCtrl::BCAST31;	0
8317	} else {	---	8317	} else {	---
8318	Valid = Check.Lo <= Val && Val <= Check.Hi;	0	8318	Valid = Check.Lo <= Val && Val <= Check.Hi;	0
8319	Val = (Check.Lo == Check.Hi) ? Check.Ctrl : (Check.Ctrl \| Val);	0	8319	Val = (Check.Lo == Check.Hi) ? Check.Ctrl : (Check.Ctrl \| Val);	0
8320	}	---	8320	}	---
8321		---	8321		---
8322	if (!Valid) {	0	8322	if (!Valid) {	0
8323	Error(Loc, Twine("invalid ", Ctrl) + Twine(" value"));	0	8323	Error(Loc, Twine("invalid ", Ctrl) + Twine(" value"));	0
8324	return -1;	0	8324	return -1;	0
8325	}	---	8325	}	---
8326		---	8326		---
8327	return Val;	0	8327	return Val;	0
8328	}	---	8328	}	---
8329		---	8329		---
8330	ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {	0	8330	ParseStatus AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {	0
8331	using namespace AMDGPU::DPP;	---	8331	using namespace AMDGPU::DPP;	---
8332		---	8332		---
8333	if (!isToken(AsmToken::Identifier) \|\|	0	8333	if (!isToken(AsmToken::Identifier) \|\|	0
8334	!isSupportedDPPCtrl(getTokenStr(), Operands))	0	8334	!isSupportedDPPCtrl(getTokenStr(), Operands))	0
8335	return ParseStatus::NoMatch;	0	8335	return ParseStatus::NoMatch;	0
8336		---	8336		---
8337	SMLoc S = getLoc();	0	8337	SMLoc S = getLoc();	0
8338	int64_t Val = -1;	0	8338	int64_t Val = -1;	0
8339	StringRef Ctrl;	0	8339	StringRef Ctrl;	0
8340		---	8340		---
8341	parseId(Ctrl);	0	8341	parseId(Ctrl);	0
8342		---	8342		---
8343	if (Ctrl == "row_mirror") {	0	8343	if (Ctrl == "row_mirror") {	0
8344	Val = DppCtrl::ROW_MIRROR;	0	8344	Val = DppCtrl::ROW_MIRROR;	0
8345	} else if (Ctrl == "row_half_mirror") {	0	8345	} else if (Ctrl == "row_half_mirror") {	0
8346	Val = DppCtrl::ROW_HALF_MIRROR;	0	8346	Val = DppCtrl::ROW_HALF_MIRROR;	0
8347	} else {	---	8347	} else {	---
8348	if (skipToken(AsmToken::Colon, "expected a colon")) {	0	8348	if (skipToken(AsmToken::Colon, "expected a colon")) {	0
8349	if (Ctrl == "quad_perm") {	0	8349	if (Ctrl == "quad_perm") {	0
8350	Val = parseDPPCtrlPerm();	0	8350	Val = parseDPPCtrlPerm();	0
8351	} else {	---	8351	} else {	---
8352	Val = parseDPPCtrlSel(Ctrl);	0	8352	Val = parseDPPCtrlSel(Ctrl);	0
8353	}	---	8353	}	---
8354	}	---	8354	}	---
8355	}	---	8355	}	---
8356		---	8356		---
8357	if (Val == -1)	0	8357	if (Val == -1)	0
8358	return ParseStatus::Failure;	0	8358	return ParseStatus::Failure;	0
8359		---	8359		---
8360	Operands.push_back(	0	8360	Operands.push_back(	0
8361	AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyDppCtrl));	0	8361	AMDGPUOperand::CreateImm(this, Val, S, AMDGPUOperand::ImmTyDppCtrl));	0
8362	return ParseStatus::Success;	0	8362	return ParseStatus::Success;	0
8363	}	---	8363	}	---
8364		---	8364		---
8365	void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	0	8365	void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,	0
8366	bool IsDPP8) {	---	8366	bool IsDPP8) {	---
8367	OptionalImmIndexMap OptionalIdx;	0	8367	OptionalImmIndexMap OptionalIdx;	0
8368	unsigned Opc = Inst.getOpcode();	0	8368	unsigned Opc = Inst.getOpcode();	0
8369	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	8369	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
8370		---	8370		---
8371	// MAC instructions are special because they have 'old'	---	8371	// MAC instructions are special because they have 'old'	---
8372	// operand which is not tied to dst (but assumed to be).	---	8372	// operand which is not tied to dst (but assumed to be).	---
8373	// They also have dummy unused src2_modifiers.	---	8373	// They also have dummy unused src2_modifiers.	---
8374	int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old);	0	8374	int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old);	0
8375	int Src2ModIdx =	0	8375	int Src2ModIdx =	0
8376	AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);	0	8376	AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);	0
8377	bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&	0	8377	bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&	0
8378	Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;	0	8378	Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;	0
8379		---	8379		---
8380	unsigned I = 1;	0	8380	unsigned I = 1;	0
8381	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0	8381	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
8382	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0	8382	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
8383	}	---	8383	}	---
8384		---	8384		---
8385	int Fi = 0;	0	8385	int Fi = 0;	0
8386	for (unsigned E = Operands.size(); I != E; ++I) {	0	8386	for (unsigned E = Operands.size(); I != E; ++I) {	0
8387		---	8387		---
8388	if (IsMAC) {	0	8388	if (IsMAC) {	0
8389	int NumOperands = Inst.getNumOperands();	0	8389	int NumOperands = Inst.getNumOperands();	0
8390	if (OldIdx == NumOperands) {	0	8390	if (OldIdx == NumOperands) {	0
8391	// Handle old operand	---	8391	// Handle old operand	---
8392	constexpr int DST_IDX = 0;	0	8392	constexpr int DST_IDX = 0;	0
8393	Inst.addOperand(Inst.getOperand(DST_IDX));	0	8393	Inst.addOperand(Inst.getOperand(DST_IDX));	0
8394	} else if (Src2ModIdx == NumOperands) {	0	8394	} else if (Src2ModIdx == NumOperands) {	0
8395	// Add unused dummy src2_modifiers	---	8395	// Add unused dummy src2_modifiers	---
8396	Inst.addOperand(MCOperand::createImm(0));	0	8396	Inst.addOperand(MCOperand::createImm(0));	0
8397	}	---	8397	}	---
8398	}	---	8398	}	---
8399		---	8399		---
8400	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	0	8400	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	0
8401	MCOI::TIED_TO);	---	8401	MCOI::TIED_TO);	---
8402	if (TiedTo != -1) {	0	8402	if (TiedTo != -1) {	0
8403	assert((unsigned)TiedTo < Inst.getNumOperands());	0	8403	assert((unsigned)TiedTo < Inst.getNumOperands());	0
8404	// handle tied old or src2 for MAC instructions	---	8404	// handle tied old or src2 for MAC instructions	---
8405	Inst.addOperand(Inst.getOperand(TiedTo));	0	8405	Inst.addOperand(Inst.getOperand(TiedTo));	0
8406	}	---	8406	}	---
8407	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0	8407	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
8408	// Add the register arguments	---	8408	// Add the register arguments	---
8409	if (IsDPP8 && Op.isDppFI()) {	0	8409	if (IsDPP8 && Op.isDppFI()) {	0
8410	Fi = Op.getImm();	0	8410	Fi = Op.getImm();	0
8411	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	8411	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8412	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0	8412	Op.addRegOrImmWithFPInputModsOperands(Inst, 2);	0
8413	} else if (Op.isReg()) {	0	8413	} else if (Op.isReg()) {	0
8414	Op.addRegOperands(Inst, 1);	0	8414	Op.addRegOperands(Inst, 1);	0
8415	} else if (Op.isImm() &&	0	8415	} else if (Op.isImm() &&	0
8416	Desc.operands()[Inst.getNumOperands()].RegClass != -1) {	0	8416	Desc.operands()[Inst.getNumOperands()].RegClass != -1) {	0
8417	assert(!Op.IsImmKindLiteral() && "Cannot use literal with DPP");	0	8417	assert(!Op.IsImmKindLiteral() && "Cannot use literal with DPP");	0
8418	Op.addImmOperands(Inst, 1);	0	8418	Op.addImmOperands(Inst, 1);	0
8419	} else if (Op.isImm()) {	0	8419	} else if (Op.isImm()) {	0
8420	OptionalIdx[Op.getImmTy()] = I;	0	8420	OptionalIdx[Op.getImmTy()] = I;	0
8421	} else {	---	8421	} else {	---
8422	llvm_unreachable("unhandled operand type");	0	8422	llvm_unreachable("unhandled operand type");	0
8423	}	---	8423	}	---
8424	}	---	8424	}	---
8425	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0	8425	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
8426	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	0	8426	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);	0
8427		---	8427		---
8428	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0	8428	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
8429	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);	0	8429	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);	0
8430		---	8430		---
8431	if (Desc.TSFlags & SIInstrFlags::VOP3P)	0	8431	if (Desc.TSFlags & SIInstrFlags::VOP3P)	0
8432	cvtVOP3P(Inst, Operands, OptionalIdx);	0	8432	cvtVOP3P(Inst, Operands, OptionalIdx);	0
8433	else if (Desc.TSFlags & SIInstrFlags::VOP3)	0	8433	else if (Desc.TSFlags & SIInstrFlags::VOP3)	0
8434	cvtVOP3OpSel(Inst, Operands, OptionalIdx);	0	8434	cvtVOP3OpSel(Inst, Operands, OptionalIdx);	0
8435	else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {	0	8435	else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {	0
8436	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	0	8436	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);	0
8437	}	---	8437	}	---
8438		---	8438		---
8439	if (IsDPP8) {	0	8439	if (IsDPP8) {	0
8440	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);	0	8440	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDPP8);	0
8441	using namespace llvm::AMDGPU::DPP;	---	8441	using namespace llvm::AMDGPU::DPP;	---
8442	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	0	8442	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	0
8443	} else {	---	8443	} else {	---
8444	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);	0	8444	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppCtrl, 0xe4);	0
8445	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	0	8445	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	0
8446	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	0	8446	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	0
8447	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	0	8447	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	0
8448		---	8448		---
8449	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))	0	8449	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))	0
8450	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	8450	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8451	AMDGPUOperand::ImmTyDppFI);	---	8451	AMDGPUOperand::ImmTyDppFI);	---
8452	}	---	8452	}	---
8453	}	0	8453	}	0
8454		---	8454		---
8455	void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {	0	8455	void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool IsDPP8) {	0
8456	OptionalImmIndexMap OptionalIdx;	0	8456	OptionalImmIndexMap OptionalIdx;	0
8457		---	8457		---
8458	unsigned I = 1;	0	8458	unsigned I = 1;	0
8459	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	8459	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
8460	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0	8460	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
8461	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0	8461	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
8462	}	---	8462	}	---
8463		---	8463		---
8464	int Fi = 0;	0	8464	int Fi = 0;	0
8465	for (unsigned E = Operands.size(); I != E; ++I) {	0	8465	for (unsigned E = Operands.size(); I != E; ++I) {	0
8466	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	0	8466	auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),	0
8467	MCOI::TIED_TO);	---	8467	MCOI::TIED_TO);	---
8468	if (TiedTo != -1) {	0	8468	if (TiedTo != -1) {	0
8469	assert((unsigned)TiedTo < Inst.getNumOperands());	0	8469	assert((unsigned)TiedTo < Inst.getNumOperands());	0
8470	// handle tied old or src2 for MAC instructions	---	8470	// handle tied old or src2 for MAC instructions	---
8471	Inst.addOperand(Inst.getOperand(TiedTo));	0	8471	Inst.addOperand(Inst.getOperand(TiedTo));	0
8472	}	---	8472	}	---
8473	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0	8473	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
8474	// Add the register arguments	---	8474	// Add the register arguments	---
8475	if (Op.isReg() && validateVccOperand(Op.getReg())) {	0	8475	if (Op.isReg() && validateVccOperand(Op.getReg())) {	0
8476	// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.	---	8476	// VOP2b (v_add_u32, v_sub_u32 ...) dpp use "vcc" token.	---
8477	// Skip it.	---	8477	// Skip it.	---
8478	continue;	0	8478	continue;	0
8479	}	---	8479	}	---
8480		---	8480		---
8481	if (IsDPP8) {	0	8481	if (IsDPP8) {	0
8482	if (Op.isDPP8()) {	0	8482	if (Op.isDPP8()) {	0
8483	Op.addImmOperands(Inst, 1);	0	8483	Op.addImmOperands(Inst, 1);	0
8484	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	8484	} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8485	Op.addRegWithFPInputModsOperands(Inst, 2);	0	8485	Op.addRegWithFPInputModsOperands(Inst, 2);	0
8486	} else if (Op.isDppFI()) {	0	8486	} else if (Op.isDppFI()) {	0
8487	Fi = Op.getImm();	0	8487	Fi = Op.getImm();	0
8488	} else if (Op.isReg()) {	0	8488	} else if (Op.isReg()) {	0
8489	Op.addRegOperands(Inst, 1);	0	8489	Op.addRegOperands(Inst, 1);	0
8490	} else {	---	8490	} else {	---
8491	llvm_unreachable("Invalid operand type");	0	8491	llvm_unreachable("Invalid operand type");	0
8492	}	---	8492	}	---
8493	} else {	---	8493	} else {	---
8494	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	8494	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8495	Op.addRegWithFPInputModsOperands(Inst, 2);	0	8495	Op.addRegWithFPInputModsOperands(Inst, 2);	0
8496	} else if (Op.isReg()) {	0	8496	} else if (Op.isReg()) {	0
8497	Op.addRegOperands(Inst, 1);	0	8497	Op.addRegOperands(Inst, 1);	0
8498	} else if (Op.isDPPCtrl()) {	0	8498	} else if (Op.isDPPCtrl()) {	0
8499	Op.addImmOperands(Inst, 1);	0	8499	Op.addImmOperands(Inst, 1);	0
8500	} else if (Op.isImm()) {	0	8500	} else if (Op.isImm()) {	0
8501	// Handle optional arguments	---	8501	// Handle optional arguments	---
8502	OptionalIdx[Op.getImmTy()] = I;	0	8502	OptionalIdx[Op.getImmTy()] = I;	0
8503	} else {	---	8503	} else {	---
8504	llvm_unreachable("Invalid operand type");	0	8504	llvm_unreachable("Invalid operand type");	0
8505	}	---	8505	}	---
8506	}	---	8506	}	---
8507	}	---	8507	}	---
8508		---	8508		---
8509	if (IsDPP8) {	0	8509	if (IsDPP8) {	0
8510	using namespace llvm::AMDGPU::DPP;	---	8510	using namespace llvm::AMDGPU::DPP;	---
8511	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	0	8511	Inst.addOperand(MCOperand::createImm(Fi? DPP8_FI_1 : DPP8_FI_0));	0
8512	} else {	---	8512	} else {	---
8513	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	0	8513	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);	0
8514	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	0	8514	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);	0
8515	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	0	8515	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);	0
8516	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {	0	8516	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {	0
8517	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	8517	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8518	AMDGPUOperand::ImmTyDppFI);	---	8518	AMDGPUOperand::ImmTyDppFI);	---
8519	}	---	8519	}	---
8520	}	---	8520	}	---
8521	}	0	8521	}	0
8522		---	8522		---
8523	//===----------------------------------------------------------------------===//	---	8523	//===----------------------------------------------------------------------===//	---
8524	// sdwa	---	8524	// sdwa	---
8525	//===----------------------------------------------------------------------===//	---	8525	//===----------------------------------------------------------------------===//	---
8526		---	8526		---
8527	ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,	0	8527	ParseStatus AMDGPUAsmParser::parseSDWASel(OperandVector &Operands,	0
8528	StringRef Prefix,	---	8528	StringRef Prefix,	---
8529	AMDGPUOperand::ImmTy Type) {	---	8529	AMDGPUOperand::ImmTy Type) {	---
8530	using namespace llvm::AMDGPU::SDWA;	---	8530	using namespace llvm::AMDGPU::SDWA;	---
8531		---	8531		---
8532	SMLoc S = getLoc();	0	8532	SMLoc S = getLoc();	0
8533	StringRef Value;	0	8533	StringRef Value;	0
8534		---	8534		---
8535	SMLoc StringLoc;	0	8535	SMLoc StringLoc;	0
8536	ParseStatus Res = parseStringWithPrefix(Prefix, Value, StringLoc);	0	8536	ParseStatus Res = parseStringWithPrefix(Prefix, Value, StringLoc);	0
8537	if (!Res.isSuccess())	0	8537	if (!Res.isSuccess())	0
8538	return Res;	0	8538	return Res;	0
8539		---	8539		---
8540	int64_t Int;	---	8540	int64_t Int;	---
8541	Int = StringSwitch(Value)	0	8541	Int = StringSwitch(Value)	0
8542	.Case("BYTE_0", SdwaSel::BYTE_0)	0	8542	.Case("BYTE_0", SdwaSel::BYTE_0)	0
8543	.Case("BYTE_1", SdwaSel::BYTE_1)	0	8543	.Case("BYTE_1", SdwaSel::BYTE_1)	0
8544	.Case("BYTE_2", SdwaSel::BYTE_2)	0	8544	.Case("BYTE_2", SdwaSel::BYTE_2)	0
8545	.Case("BYTE_3", SdwaSel::BYTE_3)	0	8545	.Case("BYTE_3", SdwaSel::BYTE_3)	0
8546	.Case("WORD_0", SdwaSel::WORD_0)	0	8546	.Case("WORD_0", SdwaSel::WORD_0)	0
8547	.Case("WORD_1", SdwaSel::WORD_1)	0	8547	.Case("WORD_1", SdwaSel::WORD_1)	0
8548	.Case("DWORD", SdwaSel::DWORD)	0	8548	.Case("DWORD", SdwaSel::DWORD)	0
8549	.Default(0xffffffff);	0	8549	.Default(0xffffffff);	0
8550		---	8550		---
8551	if (Int == 0xffffffff)	0	8551	if (Int == 0xffffffff)	0
8552	return Error(StringLoc, "invalid " + Twine(Prefix) + " value");	0	8552	return Error(StringLoc, "invalid " + Twine(Prefix) + " value");	0
8553		---	8553		---
8554	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));	0	8554	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, Type));	0
8555	return ParseStatus::Success;	0	8555	return ParseStatus::Success;	0
8556	}	---	8556	}	---
8557		---	8557		---
8558	ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {	0	8558	ParseStatus AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {	0
8559	using namespace llvm::AMDGPU::SDWA;	---	8559	using namespace llvm::AMDGPU::SDWA;	---
8560		---	8560		---
8561	SMLoc S = getLoc();	0	8561	SMLoc S = getLoc();	0
8562	StringRef Value;	0	8562	StringRef Value;	0
8563		---	8563		---
8564	SMLoc StringLoc;	0	8564	SMLoc StringLoc;	0
8565	ParseStatus Res = parseStringWithPrefix("dst_unused", Value, StringLoc);	0	8565	ParseStatus Res = parseStringWithPrefix("dst_unused", Value, StringLoc);	0
8566	if (!Res.isSuccess())	0	8566	if (!Res.isSuccess())	0
8567	return Res;	0	8567	return Res;	0
8568		---	8568		---
8569	int64_t Int;	---	8569	int64_t Int;	---
8570	Int = StringSwitch(Value)	0	8570	Int = StringSwitch(Value)	0
8571	.Case("UNUSED_PAD", DstUnused::UNUSED_PAD)	0	8571	.Case("UNUSED_PAD", DstUnused::UNUSED_PAD)	0
8572	.Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)	0	8572	.Case("UNUSED_SEXT", DstUnused::UNUSED_SEXT)	0
8573	.Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)	0	8573	.Case("UNUSED_PRESERVE", DstUnused::UNUSED_PRESERVE)	0
8574	.Default(0xffffffff);	0	8574	.Default(0xffffffff);	0
8575		---	8575		---
8576	if (Int == 0xffffffff)	0	8576	if (Int == 0xffffffff)	0
8577	return Error(StringLoc, "invalid dst_unused value");	0	8577	return Error(StringLoc, "invalid dst_unused value");	0
8578		---	8578		---
8579	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));	0	8579	Operands.push_back(AMDGPUOperand::CreateImm(this, Int, S, AMDGPUOperand::ImmTySDWADstUnused));	0
8580	return ParseStatus::Success;	0	8580	return ParseStatus::Success;	0
8581	}	---	8581	}	---
8582		---	8582		---
8583	void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {	0	8583	void AMDGPUAsmParser::cvtSdwaVOP1(MCInst &Inst, const OperandVector &Operands) {	0
8584	cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);	0	8584	cvtSDWA(Inst, Operands, SIInstrFlags::VOP1);	0
8585	}	0	8585	}	0
8586		---	8586		---
8587	void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {	0	8587	void AMDGPUAsmParser::cvtSdwaVOP2(MCInst &Inst, const OperandVector &Operands) {	0
8588	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);	0	8588	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2);	0
8589	}	0	8589	}	0
8590		---	8590		---
8591	void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {	0	8591	void AMDGPUAsmParser::cvtSdwaVOP2b(MCInst &Inst, const OperandVector &Operands) {	0
8592	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);	0	8592	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, true, true);	0
8593	}	0	8593	}	0
8594		---	8594		---
8595	void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {	0	8595	void AMDGPUAsmParser::cvtSdwaVOP2e(MCInst &Inst, const OperandVector &Operands) {	0
8596	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);	0	8596	cvtSDWA(Inst, Operands, SIInstrFlags::VOP2, false, true);	0
8597	}	0	8597	}	0
8598		---	8598		---
8599	void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {	0	8599	void AMDGPUAsmParser::cvtSdwaVOPC(MCInst &Inst, const OperandVector &Operands) {	0
8600	cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());	0	8600	cvtSDWA(Inst, Operands, SIInstrFlags::VOPC, isVI());	0
8601	}	0	8601	}	0
8602		---	8602		---
8603	void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,	0	8603	void AMDGPUAsmParser::cvtSDWA(MCInst &Inst, const OperandVector &Operands,	0
8604	uint64_t BasicInstType,	---	8604	uint64_t BasicInstType,	---
8605	bool SkipDstVcc,	---	8605	bool SkipDstVcc,	---
8606	bool SkipSrcVcc) {	---	8606	bool SkipSrcVcc) {	---
8607	using namespace llvm::AMDGPU::SDWA;	---	8607	using namespace llvm::AMDGPU::SDWA;	---
8608		---	8608		---
8609	OptionalImmIndexMap OptionalIdx;	0	8609	OptionalImmIndexMap OptionalIdx;	0
8610	bool SkipVcc = SkipDstVcc \|\| SkipSrcVcc;	0	8610	bool SkipVcc = SkipDstVcc \|\| SkipSrcVcc;	0
8611	bool SkippedVcc = false;	0	8611	bool SkippedVcc = false;	0
8612		---	8612		---
8613	unsigned I = 1;	0	8613	unsigned I = 1;	0
8614	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0	8614	const MCInstrDesc &Desc = MII.get(Inst.getOpcode());	0
8615	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0	8615	for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {	0
8616	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0	8616	((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);	0
8617	}	---	8617	}	---
8618		---	8618		---
8619	for (unsigned E = Operands.size(); I != E; ++I) {	0	8619	for (unsigned E = Operands.size(); I != E; ++I) {	0
8620	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0	8620	AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);	0
8621	if (SkipVcc && !SkippedVcc && Op.isReg() &&	0	8621	if (SkipVcc && !SkippedVcc && Op.isReg() &&	0
8622	(Op.getReg() == AMDGPU::VCC \|\| Op.getReg() == AMDGPU::VCC_LO)) {	0	8622	(Op.getReg() == AMDGPU::VCC \|\| Op.getReg() == AMDGPU::VCC_LO)) {	0
8623	// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.	---	8623	// VOP2b (v_add_u32, v_sub_u32 ...) sdwa use "vcc" token as dst.	---
8624	// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)	---	8624	// Skip it if it's 2nd (e.g. v_add_i32_sdwa v1, vcc, v2, v3)	---
8625	// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.	---	8625	// or 4th (v_addc_u32_sdwa v1, vcc, v2, v3, vcc) operand.	---
8626	// Skip VCC only if we didn't skip it on previous iteration.	---	8626	// Skip VCC only if we didn't skip it on previous iteration.	---
8627	// Note that src0 and src1 occupy 2 slots each because of modifiers.	---	8627	// Note that src0 and src1 occupy 2 slots each because of modifiers.	---
8628	if (BasicInstType == SIInstrFlags::VOP2 &&	0	8628	if (BasicInstType == SIInstrFlags::VOP2 &&	0
8629	((SkipDstVcc && Inst.getNumOperands() == 1) \|\|	0	8629	((SkipDstVcc && Inst.getNumOperands() == 1) \|\|	0
8630	(SkipSrcVcc && Inst.getNumOperands() == 5))) {	0	8630	(SkipSrcVcc && Inst.getNumOperands() == 5))) {	0
8631	SkippedVcc = true;	0	8631	SkippedVcc = true;	0
8632	continue;	0	8632	continue;	0
8633	} else if (BasicInstType == SIInstrFlags::VOPC &&	0	8633	} else if (BasicInstType == SIInstrFlags::VOPC &&	0
8634	Inst.getNumOperands() == 0) {	0	8634	Inst.getNumOperands() == 0) {	0
8635	SkippedVcc = true;	0	8635	SkippedVcc = true;	0
8636	continue;	0	8636	continue;	0
8637	}	---	8637	}	---
8638	}	---	8638	}	---
8639	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0	8639	if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {	0
8640	Op.addRegOrImmWithInputModsOperands(Inst, 2);	0	8640	Op.addRegOrImmWithInputModsOperands(Inst, 2);	0
8641	} else if (Op.isImm()) {	0	8641	} else if (Op.isImm()) {	0
8642	// Handle optional arguments	---	8642	// Handle optional arguments	---
8643	OptionalIdx[Op.getImmTy()] = I;	0	8643	OptionalIdx[Op.getImmTy()] = I;	0
8644	} else {	---	8644	} else {	---
8645	llvm_unreachable("Invalid operand type");	0	8645	llvm_unreachable("Invalid operand type");	0
8646	}	---	8646	}	---
8647	SkippedVcc = false;	0	8647	SkippedVcc = false;	0
8648	}	---	8648	}	---
8649		---	8649		---
8650	const unsigned Opc = Inst.getOpcode();	0	8650	const unsigned Opc = Inst.getOpcode();	0
8651	if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&	0	8651	if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&	0
8652	Opc != AMDGPU::V_NOP_sdwa_vi) {	---	8652	Opc != AMDGPU::V_NOP_sdwa_vi) {	---
8653	// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments	---	8653	// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments	---
8654	switch (BasicInstType) {	0	8654	switch (BasicInstType) {	0
8655	case SIInstrFlags::VOP1:	0	8655	case SIInstrFlags::VOP1:	0
8656	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0	8656	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))	0
8657	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	8657	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8658	AMDGPUOperand::ImmTyClampSI, 0);	---	8658	AMDGPUOperand::ImmTyClampSI, 0);	---
8659		---	8659		---
8660	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0	8660	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))	0
8661	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	8661	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8662	AMDGPUOperand::ImmTyOModSI, 0);	---	8662	AMDGPUOperand::ImmTyOModSI, 0);	---
8663		---	8663		---
8664	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))	0	8664	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))	0
8665	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	8665	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8666	AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	---	8666	AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	---
8667		---	8667		---
8668	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))	0	8668	if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))	0
8669	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0	8669	addOptionalImmOperand(Inst, Operands, OptionalIdx,	0
8670	AMDGPUOperand::ImmTySDWADstUnused,	---	8670	AMDGPUOperand::ImmTySDWADstUnused,	---
8671	DstUnused::UNUSED_PRESERVE);	---	8671	DstUnused::UNUSED_PRESERVE);	---
8672		---	8672		---
8673	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0	8673	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0
8674	break;	0	8674	break;	0
8675		---	8675		---
8676	case SIInstrFlags::VOP2:	0	8676	case SIInstrFlags::VOP2:	0
8677	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	0	8677	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	0
8678		---	8678		---
8679	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))	0	8679	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))	0
8680	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);	0	8680	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);	0
8681		---	8681		---
8682	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	0	8682	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstSel, SdwaSel::DWORD);	0
8683	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);	0	8683	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWADstUnused, DstUnused::UNUSED_PRESERVE);	0
8684	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0	8684	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0
8685	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	0	8685	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	0
8686	break;	0	8686	break;	0
8687		---	8687		---
8688	case SIInstrFlags::VOPC:	0	8688	case SIInstrFlags::VOPC:	0
8689	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))	0	8689	if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))	0
8690	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	0	8690	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);	0
8691	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0	8691	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc0Sel, SdwaSel::DWORD);	0
8692	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	0	8692	addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySDWASrc1Sel, SdwaSel::DWORD);	0
8693	break;	0	8693	break;	0
8694		---	8694		---
8695	default:	0	8695	default:	0
8696	llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");	0	8696	llvm_unreachable("Invalid instruction type. Only VOP1, VOP2 and VOPC allowed");	0
8697	}	---	8697	}	---
8698	}	---	8698	}	---
8699		---	8699		---
8700	// special case v_mac_{f16, f32}:	---	8700	// special case v_mac_{f16, f32}:	---
8701	// it has src2 register operand that is tied to dst operand	---	8701	// it has src2 register operand that is tied to dst operand	---
8702	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	0	8702	if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi \|\|	0
8703	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	0	8703	Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {	0
8704	auto it = Inst.begin();	0	8704	auto it = Inst.begin();	0
8705	std::advance(	0	8705	std::advance(	0
8706	it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));	0	8706	it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));	0
8707	Inst.insert(it, Inst.getOperand(0)); // src2 = dst	0	8707	Inst.insert(it, Inst.getOperand(0)); // src2 = dst	0
8708	}	---	8708	}	---
8709	}	0	8709	}	0
8710		---	8710		---
8711	/// Force static initialization.	---	8711	/// Force static initialization.	---
8712	extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {	1	8712	extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmParser() {	1
8713	RegisterMCAsmParser A(getTheR600Target());	1	8713	RegisterMCAsmParser A(getTheR600Target());	1
8714	RegisterMCAsmParser B(getTheGCNTarget());	1	8714	RegisterMCAsmParser B(getTheGCNTarget());	1
8715	}	1	8715	}	1
8716		---	8716		---
8717	#define GET_REGISTER_MATCHER	---	8717	#define GET_REGISTER_MATCHER	---
8718	#define GET_MATCHER_IMPLEMENTATION	---	8718	#define GET_MATCHER_IMPLEMENTATION	---
8719	#define GET_MNEMONIC_SPELL_CHECKER	---	8719	#define GET_MNEMONIC_SPELL_CHECKER	---
8720	#define GET_MNEMONIC_CHECKER	---	8720	#define GET_MNEMONIC_CHECKER	---
8721	#include "AMDGPUGenAsmMatcher.inc"	---	8721	#include "AMDGPUGenAsmMatcher.inc"	---
8722		---	8722		---
8723	ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,	0	8723	ParseStatus AMDGPUAsmParser::parseCustomOperand(OperandVector &Operands,	0
8724	unsigned MCK) {	---	8724	unsigned MCK) {	---
8725	switch (MCK) {	0	8725	switch (MCK) {	0
8726	case MCK_addr64:	0	8726	case MCK_addr64:	0
8727	return parseTokenOp("addr64", Operands);	0	8727	return parseTokenOp("addr64", Operands);	0
8728	case MCK_done:	0	8728	case MCK_done:	0
8729	return parseTokenOp("done", Operands);	0	8729	return parseTokenOp("done", Operands);	0
8730	case MCK_idxen:	0	8730	case MCK_idxen:	0
8731	return parseTokenOp("idxen", Operands);	0	8731	return parseTokenOp("idxen", Operands);	0
8732	case MCK_lds:	0	8732	case MCK_lds:	0
8733	return parseTokenOp("lds", Operands);	0	8733	return parseTokenOp("lds", Operands);	0
8734	case MCK_offen:	0	8734	case MCK_offen:	0
8735	return parseTokenOp("offen", Operands);	0	8735	return parseTokenOp("offen", Operands);	0
8736	case MCK_off:	0	8736	case MCK_off:	0
8737	return parseTokenOp("off", Operands);	0	8737	return parseTokenOp("off", Operands);	0
8738	case MCK_row_95_en:	0	8738	case MCK_row_95_en:	0
8739	return parseTokenOp("row_en", Operands);	0	8739	return parseTokenOp("row_en", Operands);	0
8740	case MCK_gds:	0	8740	case MCK_gds:	0
8741	return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);	0	8741	return parseNamedBit("gds", Operands, AMDGPUOperand::ImmTyGDS);	0
8742	case MCK_tfe:	0	8742	case MCK_tfe:	0
8743	return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);	0	8743	return parseNamedBit("tfe", Operands, AMDGPUOperand::ImmTyTFE);	0
8744	}	---	8744	}	---
8745	return tryCustomParseOperand(Operands, MCK);	0	8745	return tryCustomParseOperand(Operands, MCK);	0
8746	}	---	8746	}	---
8747		---	8747		---
8748	// This function should be defined after auto-generated include so that we have	---	8748	// This function should be defined after auto-generated include so that we have	---
8749	// MatchClassKind enum defined	---	8749	// MatchClassKind enum defined	---
8750	unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,	0	8750	unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,	0
8751	unsigned Kind) {	---	8751	unsigned Kind) {	---
8752	// Tokens like "glc" would be parsed as immediate operands in ParseOperand().	---	8752	// Tokens like "glc" would be parsed as immediate operands in ParseOperand().	---
8753	// But MatchInstructionImpl() expects to meet token and fails to validate	---	8753	// But MatchInstructionImpl() expects to meet token and fails to validate	---
8754	// operand. This method checks if we are given immediate operand but expect to	---	8754	// operand. This method checks if we are given immediate operand but expect to	---
8755	// get corresponding token.	---	8755	// get corresponding token.	---
8756	AMDGPUOperand &Operand = (AMDGPUOperand&)Op;	0	8756	AMDGPUOperand &Operand = (AMDGPUOperand&)Op;	0
8757	switch (Kind) {	0	8757	switch (Kind) {	0
8758	case MCK_addr64:	0	8758	case MCK_addr64:	0
8759	return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;	0	8759	return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;	0
8760	case MCK_gds:	0	8760	case MCK_gds:	0
8761	return Operand.isGDS() ? Match_Success : Match_InvalidOperand;	0	8761	return Operand.isGDS() ? Match_Success : Match_InvalidOperand;	0
8762	case MCK_lds:	0	8762	case MCK_lds:	0
8763	return Operand.isLDS() ? Match_Success : Match_InvalidOperand;	0	8763	return Operand.isLDS() ? Match_Success : Match_InvalidOperand;	0
8764	case MCK_idxen:	0	8764	case MCK_idxen:	0
8765	return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;	0	8765	return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;	0
8766	case MCK_offen:	0	8766	case MCK_offen:	0
8767	return Operand.isOffen() ? Match_Success : Match_InvalidOperand;	0	8767	return Operand.isOffen() ? Match_Success : Match_InvalidOperand;	0
8768	case MCK_tfe:	0	8768	case MCK_tfe:	0
8769	return Operand.isTFE() ? Match_Success : Match_InvalidOperand;	0	8769	return Operand.isTFE() ? Match_Success : Match_InvalidOperand;	0
8770	case MCK_SSrcB32:	0	8770	case MCK_SSrcB32:	0
8771	// When operands have expression values, they will return true for isToken,	---	8771	// When operands have expression values, they will return true for isToken,	---
8772	// because it is not possible to distinguish between a token and an	---	8772	// because it is not possible to distinguish between a token and an	---
8773	// expression at parse time. MatchInstructionImpl() will always try to	---	8773	// expression at parse time. MatchInstructionImpl() will always try to	---
8774	// match an operand as a token, when isToken returns true, and when the	---	8774	// match an operand as a token, when isToken returns true, and when the	---
8775	// name of the expression is not a valid token, the match will fail,	---	8775	// name of the expression is not a valid token, the match will fail,	---
8776	// so we need to handle it here.	---	8776	// so we need to handle it here.	---
8777	return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;	0	8777	return Operand.isSSrcB32() ? Match_Success : Match_InvalidOperand;	0
8778	case MCK_SSrcF32:	0	8778	case MCK_SSrcF32:	0
8779	return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;	0	8779	return Operand.isSSrcF32() ? Match_Success : Match_InvalidOperand;	0
8780	case MCK_SOPPBrTarget:	0	8780	case MCK_SOPPBrTarget:	0
8781	return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;	0	8781	return Operand.isSOPPBrTarget() ? Match_Success : Match_InvalidOperand;	0
8782	case MCK_VReg32OrOff:	0	8782	case MCK_VReg32OrOff:	0
8783	return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;	0	8783	return Operand.isVReg32OrOff() ? Match_Success : Match_InvalidOperand;	0
8784	case MCK_InterpSlot:	0	8784	case MCK_InterpSlot:	0
8785	return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;	0	8785	return Operand.isInterpSlot() ? Match_Success : Match_InvalidOperand;	0
8786	case MCK_InterpAttr:	0	8786	case MCK_InterpAttr:	0
8787	return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;	0	8787	return Operand.isInterpAttr() ? Match_Success : Match_InvalidOperand;	0
8788	case MCK_InterpAttrChan:	0	8788	case MCK_InterpAttrChan:	0
8789	return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;	0	8789	return Operand.isInterpAttrChan() ? Match_Success : Match_InvalidOperand;	0
8790	case MCK_SReg_64:	0	8790	case MCK_SReg_64:	0
8791	case MCK_SReg_64_XEXEC:	---	8791	case MCK_SReg_64_XEXEC:	---
8792	// Null is defined as a 32-bit register but	---	8792	// Null is defined as a 32-bit register but	---
8793	// it should also be enabled with 64-bit operands.	---	8793	// it should also be enabled with 64-bit operands.	---
8794	// The following code enables it for SReg_64 operands	---	8794	// The following code enables it for SReg_64 operands	---
8795	// used as source and destination. Remaining source	---	8795	// used as source and destination. Remaining source	---
8796	// operands are handled in isInlinableImm.	---	8796	// operands are handled in isInlinableImm.	---
8797	return Operand.isNull() ? Match_Success : Match_InvalidOperand;	0	8797	return Operand.isNull() ? Match_Success : Match_InvalidOperand;	0
8798	default:	0	8798	default:	0
8799	return Match_InvalidOperand;	0	8799	return Match_InvalidOperand;	0
8800	}	---	8800	}	---
8801	}	---	8801	}	---
8802		---	8802		---
8803	//===----------------------------------------------------------------------===//	---	8803	//===----------------------------------------------------------------------===//	---
8804	// endpgm	---	8804	// endpgm	---
8805	//===----------------------------------------------------------------------===//	---	8805	//===----------------------------------------------------------------------===//	---
8806		---	8806		---
8807	ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {	0	8807	ParseStatus AMDGPUAsmParser::parseEndpgm(OperandVector &Operands) {	0
8808	SMLoc S = getLoc();	0	8808	SMLoc S = getLoc();	0
8809	int64_t Imm = 0;	0	8809	int64_t Imm = 0;	0
8810		---	8810		---
8811	if (!parseExpr(Imm)) {	0	8811	if (!parseExpr(Imm)) {	0
8812	// The operand is optional, if not present default to 0	---	8812	// The operand is optional, if not present default to 0	---
8813	Imm = 0;	0	8813	Imm = 0;	0
8814	}	---	8814	}	---
8815		---	8815		---
8816	if (!isUInt<16>(Imm))	0	8816	if (!isUInt<16>(Imm))	0
8817	return Error(S, "expected a 16-bit value");	0	8817	return Error(S, "expected a 16-bit value");	0
8818		---	8818		---
8819	Operands.push_back(	0	8819	Operands.push_back(	0
8820	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));	0	8820	AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTyEndpgm));	0
8821	return ParseStatus::Success;	0	8821	return ParseStatus::Success;	0
8822	}	---	8822	}	---
8823		---	8823		---
8824	bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }	0	8824	bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); }	0
8825		---	8825		---
8826	//===----------------------------------------------------------------------===//	---	8826	//===----------------------------------------------------------------------===//	---
8827	// LDSDIR	---	8827	// LDSDIR	---
8828	//===----------------------------------------------------------------------===//	---	8828	//===----------------------------------------------------------------------===//	---
8829		---	8829		---
8830	bool AMDGPUOperand::isWaitVDST() const {	0	8830	bool AMDGPUOperand::isWaitVDST() const {	0
8831	return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());	0	8831	return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm());	0
8832	}	---	8832	}	---
8833		---	8833		---
8834	//===----------------------------------------------------------------------===//	---	8834	//===----------------------------------------------------------------------===//	---
8835	// VINTERP	---	8835	// VINTERP	---
8836	//===----------------------------------------------------------------------===//	---	8836	//===----------------------------------------------------------------------===//	---
8837		---	8837		---
8838	bool AMDGPUOperand::isWaitEXP() const {	0	8838	bool AMDGPUOperand::isWaitEXP() const {	0
8839	return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());	0	8839	return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm());	0
8840	}	---	8840	}	---
8841		---	8841		---

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